(navigation image)
Home American Libraries | Canadian Libraries | Universal Library | Community Texts | Project Gutenberg | Children's Library | Biodiversity Heritage Library | Additional Collections
Search: Advanced Search
Anonymous User (login or join us)
Upload
See other formats

Full text of "Supertex-AN-H24 Expected Voltagesand Waveforms From An HV9120 Controlled Flyback Converter OCR"

Databook 1993-1994 



High Voltage Integrated Circuits 
and DMOS Transistors 




DATABOOK 
1993-1994 

1350 Bordeaux Drive 
Sunnyvale, CA 94089 
Telephone: (408) 744-0100 
Fax: (408) 734-5247 







Supertex, Inc. Life Support Policy 

As a general policy, Supertex, Inc. does not recommend the use of any of its products in any of the following: (a) life support 
applications where the failure or malfunction of the Supertex product can be reasonably expected to cause failure of the 
life support device or to significantly affect its safety or effectiveness; or (b) any nuclear facility. Supertex will not knowingly 
sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance 
agreement," satisfactory to Supertex, stating that the risks of injury or damage have been minimized, that the customer 
assumes all such risks, and that the liability of Supertex is adequately covered in the customer's insurance policy. 

Examples of devices considered to be life support devices are neonatal oxygen analyzers, nerve stimulators (for any use), 
autotransfusion devices, blood pumps, defibrillators, arrhythmia detectors and alarms, pacemakers, hemodialysis 
systems, peritoneal dialysis systems, ventilators of all types, infusion pumps, and any other devices designated as "critical" 
by the FDA. The above are representative examples only and are not intended to be conclusive or exclusive of any other 
life support device. 

Examples of nuclear facility applications are applications in (a) a nuclear reactor; or (b) any device designed or used in 
connection with the handling, processing, packaging, preparation, utilization, fabrication, alloying, storing or disposal of 
fissionable material or waste products thereof. 

General 

This catalog has been carefully checked and is believed to be reliable; however, no responsibility is assumed for possible 
omissions or inaccuracies. Specifications are subject to change without notice. 

Supertex cannot assume responsibility for use of circuitry described; no circuit patent licenses are implied; and Supertex 
reserves the right to change said circuity at any time without notice. Liability of Supertex to circuits it manufactures is limited 
to the replacement of such circuits if they are determined to be defective due to workmanship and not due to misuse or 
mishandling. 

Copyright© 1993 by Supertex, Inc. All rights reserved. Printed in the U.S.A. 



Alphanumeric Index and Ordering Information 




Corporate Profile 


wm 


Applications Notes 


MB 


Quality Assurance and Handling Procedures 


mm 


Process Flow 


M 


Selector Guides and Cross Reference 


M 


N- and P-Channel Low Threshold MOSFETs 


wm 


DMOS N-Channel Discretes 




DMOS P-Channel Discretes 




DMOS Arrays and Special Functions 


am 


High Voltage Driver/Interface ICs 


nm 


High Voltage Analog Switches and Multiplexers 


\ym 


High Voltage Power Supply ICs 


im 


CMOS Consumer/Industrial Products 


m 


Surface Mount Packages and Lead Bend Options 


um 


Package Outlines 


iim 


Die Specifications 


itm 


Representatives/Distributors 


mm 



Table of Contents 



Chapter 1 - Alphanumeric Index and Ordering Information 

Alphanumeric Index 1-1 

Product Nomenclature/Ordering Information 1-6 

Chapter 2 - Corporate Profile 

Corporate Profile 2-1 

Custom Wafer Foundry 2-2 

Chapter 3 - Applications Notes 

AN-D1 DMOS FET Electrical Performance 3-1 

AN-D2 Low-Threshold MOSFETs: Structure, Performance and Applications 3-5 

AN-H3 Basics of EL Panel Drive Techniques 3-9 

AN-C4 Cascading Encoder-Decoder 3-12 

AN-C5 DC-7, ED-5, ED-9, ED-1 1 Applications 3-1 5 

AN-C6 Encoder-Decoders for Power Line Carrier Remote Control 3-21 

AN-C7 Encoder-Decoders for Telemetry and Control 3-24 

AN-D8 High Voltage Pulser Circuits 3-29 

AN-D9 Battery Back-Up Utilizes Low Threshold MOSFETs 3-33 

AN-D1 Off-Line Compact Universal Linear Regulator 3-36 

AN-D11 ±500 Volt Protection Circuit ••• • 3-39 

AN-D12 High Voltage Ramp Generator 3-41 

AN-H13 Designing High-Performance Flyback Converters with the HV91 1 and HV91 20 3-43 

AN-D1 4 Low Dropout 3.0 Volt Linear Regulator 3-57 

AN-D15 Understanding MOSFET Data 3-62 

AN-D1 6 Constant Current Sources and Depletion-Mode FETs 3-68 

AN-D17 High Voltage Off-Line Linear Regulator 3-70 

AN-D1 8 Constant Current Sources and Depletion-Mode FETs 3-75 

AN-D19 High Voltage Level Translator for Motor Drives 3-76 

AN-H20 HVCMOS Drivers for Non-Impact Printing 3-80 

Chapter 4 - Static Handling Procedures and Quality Assurance 

Static Handling and Testing Techniques for MOS Devices 4-1 

Quality Assurance and Handling Procedures 4-2 

Chapter 5 - Process Flow 

DMOS/HVCMOS Standard Product Flow 5-1 

HVCMOS IC Process Option Flows 5-3 

DMOS Process Option Flow Chart 5-4 

DMOS High Reliability Products 5-5 

Chapter 6 - Selector Guides and Cross Reference 

DMOS Selector Guide 6-1 

MOSFET Array Selector Guide 6-3 

HVCMOS Selector Guide 6-5 

DMOS FETs Cross Reference 6-10 

Chapter 7 - N- and P-Channel Low Threshold MOSFETs 

LP07 -16.5V, 1.5 ohms 7-1 

TN01A 60, 100V, 3 ohms 7-5 

TN01L 20, 40V, 1.8 ohms 7-9 

TN05C 200, 240V, 1 ohms 7-13 



TN05D 350, 400V, 22 ohms 7-17 

TN06A 60, 1 00V, 1 .5 ohms 7-21 

TN06C 200, 240, 6 ohms 7-25 

TN06D 350, 400V, 10 ohms 7-29 

TN06L 20, 40V, 0.75 ohms 7-33 

TN07L 20V, 1 .3 ohms 1 7-37 

TN25A 60, 1 00V, 1 .5 ohms 7-41 

TN25C 200, 240V, 6 ohms 7-45 

TN25D 350, 400V, 1 2 ohms 7-49 

TN25L 20, 40V, 1 ohm 7-53 

TN25U 1 8V, 2.5 ohms 7-57 

TN26D 350, 400V, 5 ohms 7-61 

TP01 L -20, -40V, 4 ohms 7-63 

TP06A -60, -100V, 3.5 ohms 7-67 

TP06C -1 60, -200V, 1 2 ohms 7-71 

TP06L -20, -40V, 2 ohms 7-75 

TP25A -60, -1 00V, 3.5 ohms 7-79 

TP25C -160, -200V, 12 ohms 7-83 

TP25D -350, -400V, 25 ohms 7-87 

TP25L -20, 2 ohms 7-91 

Chapter 8 - DMOS N-Channel Discretes 

2N6659 35V, 1 .8 ohms 8-1 

2N6660/2N6661 60V, 3 ohms; 90V, 4 ohms 8-3 

2N7000 60V, 5 ohms 8-5 

2N7007 240V, 45 ohms 8-9 

2N7008 60V, 7.5 ohms 8-11 

DN25D 350, 400V, 25 ohms 8-13 

LND1E 500V, 1 Kohm 8-15 

VN01A 40, 60, 90V; 3 ohms 8-19 

VN01 C 1 60, 200V; 1 ohms 8-23 

VN03D 350, 400V; 2.5 ohms 8-27 

VN03E 450, 500V; 4 ohms 8-31 

VN03F 550, 600V; 6 ohms 8-35 

VN0300 30V, 1 .2 ohms 8-39 

VN05D 350, 400V; 35 ohms 8-41 

VN05E 450, 500V; 60 ohms 8-45 

VN06D 350, 400V; 1 ohms 8-49 

VN06E 450, 500V; 1 6 ohms 8-53 

VN06F 550, 600V; 20 ohms 8-57 

VN0606A/N061 60V; 3, 5 ohms 8-61 

VN0808 80V, 4 ohms 8-63 

VN10K 60V, 5 ohms 8-65 

VN 1 1 A 60, 1 00V; 0.7 ohms 8-69 

VN12A 40, 60, 1 00V; 0.3 ohms 8-73 

VN1206/VN1210 120V; 6, 10 ohms 8-77 

VN13A 40, 60, 100V; 8 ohms 8-79 

VN1706/VN1710 170V; 6, 10 ohms 8-83 

VN201 0L 200V, 1 ohms 8-85 

VN21A 60, 100V; 4 ohms 8-87 

VN22A 60, 1 00V; 0.35 ohms 8-91 

VN22C 200, 240V, 1 .25 ohms 8-95 

VN2222 60V, 7.5 ohms 8-99 

VN2406/VN241 240V; 6, 1 ohms 8-101 

VN351 5L/VN401 2L 350, 400V; 1 5, 1 2 ohms 8-1 03 



ii 



Chapter 9 - DMOS P-Channel Discretes 

VP01A -40, -60, -90V; 8 ohms 9-1 

VP01C -160, -200V; 25 ohms 9-5 

VP03D -350, -400V; 6 ohms 9-9 

VP03E -450, -500V; 7.5 ohms 9-13 

VP0300 -30V, 2.5 ohms 9-17 

VP05D -350, -400V; 75 ohms 9-19 

VP05E -450, -500V; 125 ohms 9-23 

VP06D -350, -400V; 25 ohms 9-27 

VP06E -450, -500V; 30 ohms 9-31 

VP0808/VP1 008 -80, -1 00V; 5 ohms 9-35 

VP11A -60, -1 00V; 2 ohms 9-37 

VP12A -40, -60, -100; 0.8 ohms 9-41 

VP13A -40, -60, -1 00V; 25 ohms 9-45 

VP21 A -40, -60, -1 00V; 1 2 ohms 9-49 

VP22A -40, -60, -1 00V, 0.9 ohms 9-53 

Chapter 10 - DMOS Arrays and Special Functions 

AN01 8 N-Channel Monolithic Array; 1 60, 200, 300, 320, 400V; 300, 350 ohms 10-3 

AN04 8 N-Channel Monolithic Array; 1 60, 200, 300, 320, 400V; 300, 350 ohms 10-8 

AN05 Semicustom 8 N-Channel Monolithic Array with Logic; 1 60, 320V; 350 ohms 10-11 

AP01 8 P-Channel Monolithic Array; -1 60, -200, -300, -320, -400V; 600, 700 ohms 10-13 

AP04 8 P-Channel Monolithic Array; -1 60, -200, -300, -320, -400V; 700, 600 ohms 10-18 

AP05 Semicustom 8 P-Channel Monolithic Array with Logic; -1 60, -320V; 700 ohms 10-21 

HT01 8-Channel Logic to High Voltage Level Translator 1 0-23 

TC0604WG 40V, 3 ohms 1 0-26 

TN0604WG 40V, 1 ohms 1 0-27 

TN0606N6/TN0606N7 60V, 1 .5 ohms 1 0-28 

TP0604WG -40V, 2 ohms 1 0-29 

TP0606N6ATP0606N7 -60V, 3.5 ohms 1 0-30 

TQ3001A/Q3001A/Q7254 N- and P-Channel Quad Power MOSFET Array; 40, 20V; 3 ohms 10-31 

VC01 06N6/VC01 06N7 60V, 1 1 ohms 1 0-34 

VN0104N6A/N0104N7/VN0106N6A/N0106N7 40, 60V; 3 ohms 10-35 

VP01 04N6A/P01 04N7/VP01 06N6/VP01 06N7 -40, -60V; 8 ohms 1 0-36 

VQ1 000 60V; 5.5 ohms 1 0-37 

VQ1 001 30V, 1 .0 ohms 1 0-42 

VQ1 004 60V, 3.5 ohms 1 0-44 

VQ2001 -30V, 2 ohms 1 0-46 

VQ2006 -90V, 5 ohms 1 0-48 

Chapter 11 - High Voltage Driver/Interface ICs 

High Voltage Integrated Circuit Custom Design and Process Capabilities 11-1 

HV03/HV05 64-Channel Serial to Parallel Converter with Open Drain Outputs 11-3 

HV04/HV06 64-Channel Serial to Parallel Converter with High Voltage CMOS Outputs 11-9 

HV04H/HV06H 64-Channel Serial to Parallel Converter with Ruggedized High Voltage CMOS Outputs .... 11-15 

HV31 64-Channel Serial to Parallel Converter with Open Drain Outputs 11-21 

HV33 32 + 22 Channel Matrix Printhead Driver 1 1 -26 

HV34 64-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs 1 1 -28 

HV35 275V, 64-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs 11-33 

HV36 High Voltage Pin Diode Driver 1 1 -38 

HV38 32-Channel Gray-Shade Display Column Driver 11-43 

HV41/HV42 32-Channel Serial to Parallel Converter with P-Channel Open Drain Outputs 11-51 

HV45/HV46 32-Channel Serial to Parallel Converter with P-Channel Open Drain Outputs 11-56 

HV49 64-Channel Serial to Parallel Converter with P-Channel Open Drain Outputs 11-62 



lii 



HV51 /HV52 32-Channel Serial to Parallel Converter with Open Drain Outputs 1 1 -67 

HV53/HV54 32-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs 1 1 -73 

HV55/HV56 32-Channel Serial to Parallel Converter with Open Drain Outputs 11-78 

HV57/HV58 32-Channel Serial to Parallel Converter with Push-Pull Outputs 1 1 -84 

HV500 32-Channel AC Plasma Display Driver 1 1 -89 

HV501 32-Channel AC Plasma Display Driver 1 1 -94 

HV518 32-Channel Vacuum-Fluorescent Display Driver 11-99 

HV60 32-Channel ± 40V Liquid Crystal Display Row Driver 1 1 -1 04 

HV65 32-Channel LCD Driver with Separate Backplane Output 1 1 -1 09 

HV681 1 0-Channel Serial-Input Latched Display Driver 11-114 

HV70 34-Channel Symmetric Row Driver 11-119 

HV72 40-Channel Symmetric Row Driver 1 1 -1 25 

HV77/HV577/HV79 32MHz, 64-Channel Serial to Parallel Converter with Push-Pull Outputs 1 1 -1 31 

HV78 20MHz, 64-Channel Serial to Parallel Converter with Push-Pull Outputs 1 1 -1 36 

HV701 /HV71 1 200V, 40-Channel Vacuum-Fluorescent Display Driver 1 1 -1 41 

HV702/HV712 200V, 40-Channel Vacuum-Fluorescent Display Driver 11-147 

HV83/HV84 32-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs 1 1 -1 53 

HV87/HV88 32-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs 1 1 -1 58 

HV93/HV94 32-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs 1 1 -1 63 

HV97/HV98 32-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs 1 1 -1 68 

Chapter 12 - High Voltage Analog Switches and Multiplexers 

HV1 4-Channel High Voltage Analog Switch 12-1 

HV12 8-Channel High Voltage Analog Switch 12-6 

HV14 8-Channel High Voltage Analog Switch with Decoded Switch Selection 1 2-1 3 

HV15 1 of 8 DecodeD 8-Channel High Voltage Analog Switch 12-19 

HV1 6 8-Channel High Voltage Analog Switch 1 2-25 

HV1 8 8-Channel High Voltage Analog Switch 1 2-33 

HV21 8-Channel High Voltage Analog Switch 12-41 

HV22 8-Channel High Voltage Analog Switch 1 2-50 

HV204 Low Charge Injection 8-Channel High Voltage Analog Switch 12-59 

HV217/HV218 Low Charge Injection 8-Channel High Voltage Analog Switch 12-65 

HV227/HV228 Low Charge Injection 8-Channel High Voltage Analog Switch 12-74 

HV341/HV343/HV345/HV348 High Voltage Analog Switches 12-83 

Chapter 13 - High Voltage Power Supply ICs 

HV9100/HV9101/HV9102/HV9103 High Voltage Switchmode Controller with MOSFET 13-1 

HV91 05/HV91 08 High Voltage Switchmode Controller with MOSFET 1 3-8 

HV9106/HV9109 High Voltage Switchmode Controller with MOSFET 13-15 

HV9110/HV9111/HV9112/HV9113 High Voltage Current-Mode PWM Controller 13-22 

HV91 14/HV91 1 7 High- Voltage Current-Mode PWM Controller 1 3-29 

HV91 20/HV91 23 High Voltage Current-Mode PWM Controller 1 3-31 

HV91 24/HV91 27 High Voltage Current-Mode PWM Controller 1 3-38 

HV9220 Two-Switch High Voltage BiCMOS Current-Mode PWM Controller 1 3-40 

Chapter 14 - CMOS Consumer/Industrial Products 

DC7 Programmable Data Coder 14-1 

ED5/ED9/ED9R/ED10/ED11/ED15/ED15R Programmable Encoder/Decoder 14-9 

ET1 3/ET1 3R Programmable Encoder 14-18 

ET15/ET15R Programmable Encoder 14-24 

MP690/692/694 / MP691/693/695 Microprocessor Supervisory Circuits 1 4-30 

MP696/697 Microprocessor Supervisory Circuits 1 4-46 

SD2 CMOS Photo-Electric Smoke Detector/Integrated Circuit 1 4-59 



iv 



Chapter 15 - Surface Mount Packages and Lead Bend Options 

Surface Mount Packages 15-1 

Lead Bend Options 15-3 

Carrier Tape for SOT-89 (TO-243AA) Package 15-5 

TO-92 Taping Specifications and Winding Styles 15-6 

Chapter 16 - Package Outlines 

TO-3 Metal Can Package 16-1 

TO-39 Metal Can Package 16-1 

TO-92 Plastic Package 16-1 

TO-243AA (SOT-89) Surface Mount 16-2 

TO-52 Metal Can Package 16-2 

TO-220 Power Package 16-2 

14-Lead Ceramic Side-Brazed Package 16-3 

16-Lead Ceramic Side-Brazed Package 16-3 

18-Lead Ceramic Side-Brazed Package 16-4 

20-Lead Ceramic Side-Brazed Package 16-4 

24-Lead Ceramic Side-Brazed Package 16-5 

28-Lead Ceramic Side-Brazed Package 16-5 

40-Lead Ceramic Side-Brazed Package 16-6 

14-Lead CERDIP Package 16-6 

16-Lead CERDIP Package 16-7 

18-Lead CERDIP Package 16-7 

20-Lead CERDIP Package 16-8 

24-Lead CERDIP Package 16-8 

28-Lead CERDIP Package 16-9 

40-Lead CERDIP Package 16-9 

14-Lead Plastic Dual-ln-Line Package 16-10 

16-Lead Plastic Dual-ln-Line Package 16-10 

18-Lead Plastic Dual-ln-Line Package 16-11 

20-Lead Plastic Dual-ln-Line Package 16-11 

24-Lead Plastic Dual-ln-Line Package 16-12 

28-Lead Plastic Dual-ln-Line Package 16-12 

40-Lead Plastic Dual-ln-Line Package 16-13 

28-Lead Plastic Quad "J" Bend Package 16-13 

14-Lead SO Package (Narrow Body) 16-14 

18-Lead SO Package (Narrow Body) 16-14 

20-Lead SOW Package 16-15 

28-Lead SOW Package (Wide Body) 16-15 

Type "C" Leadless 20-Terminal Chip Carrier 16-16 

36-Leaded C/C Bend Option "CS" 16-16 

64-Lead 3-Sided Ceramic Quad Flat Package ("Gullwing" Package) 16-17 

44-Lead Quad CERPAC "DJ" Package (Gold Leads) 16-17 

44-Lead CERPAC "J" - Bend M004 Suffix (Solder Dip Leads) 16-18 

80-Lead Ceramic Quad Flat Package ("Gullwing" Package) 16-18 

44-Lead Plastic "J" - Bend Package 16-19 

44-Lead Plastic Quad Flat Package ("Gullwing" Package) 16-19 

60-Lead Plastic Quad "PL" Package ("Gullwing" Package) 16-20 

64-Lead 3-Sided Plastic Quad Flat Package ("Gullwing" Package) 16-20 

80-Lead Plastic Quad Flat Package ("Gullwing" Package) 16-21 

84-Lead Quad Plastic Chip Carrier 16-21 



Chapter 17 - Die Specifications 

VF01/VF06/VF21/VF25 17-1 

VF03/VF11/VF12/VF22 17-2 

VF05/VF1 3/VF26/TN07 17-3 

AF01/AF04/HT01 17-4 

LND1/LP07 17-5 

HV03/HV05 17-6 

HV04/HV06 17-8 

HV1 0/HV1 2/HV1 4/HV1 5/HV1 6/HV1 8 17-10 

HV21/HV22 17-12 

HV31 17-13 

HV34 17-15 

HV35 17-17 

HV38 17-19 

HV41/HV42/HV45/HV46 17-20 

HV51/HV52/HV55/HV56 17-22 

HV53/HV54/HV57/HV58 17-24 

HV500 17-26 

HV501 17-27 

HV518 17-28 

HV60 17-29 

HV6506 17-30 

HV6810 17-31 

HV70 17-32 

HV77/HV78 17-33 

HV83/HV84/HV87/HV88 17-35 

HV9110/HV9111/HV9112/HV9113/HV9120/HV9123 17-37 

Chapter 18 - Representatives/Distributors 

Representatives 18-1 

Distributors 18-3 

International , 18-5 

Sales Offices 18-5 



vi 



Alphanumeric Index and Ordering Information 




Corporate Profile 


M 


Applications Notes 


MM 


Quality Assurance and Handling Procedures 


mm 


Process Flow 


M 


Selector Guides and Cross Reference 


EH 


N- and P-Channel Low Threshold MOSFETs 


wm 


DMOS N-Channel Discretes 


mm 


DMOS P-Channel Discretes 


mm 


DMOS Arrays and Special Functions 


mm 


High Voltage Driver/Interface ICs 


mm 


High Voltage Analog Switches and Multiplexers 


mm 


High Voltage Power Supply ICs 


i« 


CMOS Consumer/Industrial Products 


mm 


Surface Mount Packages and Lead Bend Options 




Package Outlines 


urn 


Die Specifications 


wm 


Representatives/Distributors 





Alphanumeric Index 



Device 


Page# 


Device 


Page # 


Device 


Page # 


Device 


Page* 


2N6659 


8-1 


AP0140ND 


10-11 


ED9WG 


14-9 


HV0606DG 


11-9 


2N6660 


8-3 


AP0140WG 


10-11 


ET13P 


14-18 


HV0606PG 


11-9 


2N6661 


8-3 


AP0416NA 


10-16 


ET13RP 


14-18 


HV0606T 


11-9 


2N7000 


8-5 


AP0416ND 


10-16 


ET1 3RWG 


14-18 


HV0606X 


11-9 


2N7007 


8-9 


AP0416WG 


10-16 


ET13WG 


14-18 


HV0608DG 


11-9 


2N7008 


8-11 


AP0420NA 


10-16 


ET15P 


14-24 


HV0608PG 


11-9 


AN0116NA 


10-1 


AP0420ND 


10-16 


ET15RP 


14-24 


HV0608T 


11-9 


AN0116ND 


10-1 


AP0430NA 


10-16 


ET15RWG 


14-24 


HV0608X 


11-9 


AN0116WG 


10-1 


AP0430ND 


10-16 


ET15WG 


14-24 


HV06H06DG 


11-15 


AN0120NA 


10-1 


AP0432NA 


10-16 


HT0130C 


10-21 


HV06H06PG 


11-15 


AN0120ND 


10-1 


AP0432ND 


10-16 


HT0130P 


10-21 


HV06H06T 


11-15 


AN0130NA 


10-1 


AP0432WG 


10-16 


HT0130WG 


10-21 


HV06H06X 


11-15 


AN0130ND 


10-1 


AP0440NA 


10-16 


HT0130X 


10-21 


HV06H08DG 


11-15 


AN0132NA 


10-1 


AP0440ND 


10-16 


HV0322DG 


11-3 


HV06H08PG 


11-15 


AN0132ND 


10-1 


AP0440WG 


10-16 


HV0322PG 


11-3 


HV06H08T 


11-15 


AN0132WG 


10-1 


AP0516 


10-19 


HV0322T 


11-3 


HV06H08X 


11-15 


AN0140NA 


10-1 


AP0532 


10-19 


HV0322X 


11-3 


HV1014C 


12-1 


AN0140ND 


10-1 


DC7P 


14-1 


HV0330DG 


11-3 


HV1014P 


12-1 


AN0140WG 


10-1 


DC7PJ 


14-1 


HV0330PG 


11-3 


HV1014X 


12-1 


AN0416NA 


10-6 


DC7WG 


14-1 


HV0330T 


11-3 


HV1016C 


12-1 


AN0416ND 


10-6 


DC7X 


14-1 


HV0330X 


11-3 


HV1016P 


12-1 


AN0416WG 


10-6 


DN2535N2 


8-13 


HV0406DG 


11-9 


HV1016X 


12-1 


AN0420NA 


10-6 


DN2535N3 


8-13 


HV0406PG 


11-9 


HV1214C 


12-6 


AN0420ND 


10-6 


DN2535N5 


8-13 


HV0406T 


11-9 


HV1214P 


12-6 


AN0430NA 


10-6 


DN2535ND 


8-13 


HV0406X 


11-9 


HV1214X 


12-6 


AN0430ND 


10-6 


DN2540N2 


8-13 


HV0408DG 


11-9 


HV1216C 


12-6 


AN0432NA 


10-6 


DN2540N3 


8-13 


HV0408PG 


11-9 


HV1216P 


12-6 


AN0432ND 


10-6 


DN2540N5 


8-13 


HV0408T 


11-9 


HV1216X 


12-6 


AN0432WG 


10-6 


DN2540N8 


8-13 


HV0408X 


11-9 


HV1414C 


12-13 


AN0440NA 


10-6 


DN2540ND 


8-13 


HV04H06DG 


11-15 


HV1414P 


12-13 


AN0440ND 


10-6 


ED10WG 


14-9 


HV04H06PG 


11-15 


HV1414X 


12-13 


AN0440WG 


10-6 


ED11P 


14-9 


HV04H06T 


11-15 


HV1416C 


12-13 


AN0516 


10-9 


ED11WG 


14-9 


HV04H06X 


11-15 


HV1416P 


12-13 


AN0532 


10-9 


ED15P 


14-9 


HV04H08DG 


11-15 


HV1416X 


12-13 


AP0116NA 


10-11 


ED15PJ 


14-9 


HV04H08PG 


11-15 


HV1514C 


12-19 


AP0116ND 


10-11 


ED15RP 


14-9 


HV04H08T 


11-15 


HV1514P 


12-19 


AP0116WG 


10-11 


ED15RPJ 


14-9 


HV04H08X 


11-15 


HV1514X 


12-19 


AP0120NA 


10-11 


ED15RWG 


14-9 


HV0522DG 


11-3 


HV1516C 


12-19 


AP0120ND 


10-11 


ED15RX 


14-9 


HV0522PG 


11-3 


HV1516P 


12-19 


AP0130NA 


10-11 


ED15WG 


14-9 


HV0522T 


11-3 


HV1516X 


12-19 


AP0130ND 


10-11 


ED15X 


14-9 


HV0522X 


11-3 


HV1614C 


12-25 


AP0132NA 


10-11 


ED5P 


14-9 


HV0530DG 


11-3 


HV1614CS 


12-25 


AP0132ND 


10-11 


ED9P 


14-9 


HV0530PG 


11-3 


HV1614P 


12-25 


AP0132WG 


10-11 


ED9RP 


14-9 


HV0530T 


11-3 


HV1614PJ 


12-25 


AP0140NA 


10-11 


ED9RWG 


14-9 


HV0530X 


11-3 


HV1614X 


12-25 



1-1 



Device 


Page# 


Device 


Page# 


Device 


Page # 


Device 


Page # 


HV1 bl bu 


12-25 


HV^l or 


1 O CO 

1 £-bU 


nvo4oivivvu 


in on 
1 £-oo 




1 1 ft7 
lib/ 


HV1616CS 


12-25 


HV2216PJ 


12-50 


HV348P 


12-83 


HV5222PG 


11-67 


HV1616P 


12-25 


HV2216X 


12-50 


HV348WG 


12-83 


HV5222PJ 


11-67 


HV1616PJ 


12-25 


HV22714C 


12-74 


HV348X 


12-83 


HV5222X 


11-67 


HV1616X 


12-25 


HV22714P 


12-74 


HV3527DG 


11-33 


HV5308DJ 


11-73 


n v i o 1 40 


1 O OQ 


UI\/0071 /I D 1 

rxvddi 14rJ 


1 O T>l 


LJ\/0 C07Dr 


I 1 oo 

II -oo 


nvooUoro 


1 1 7Q 

1 1 -to 


HV1814CS 


12-33 


HV22714WG 


12-74 


HV3527T 


11-33 


HV5308PJ 


11-73 


HV1814P 


12-33 


HV22714X 


12-74 


HV3527X 


11-33 


HV5308X 


11-73 


HV1814PJ 


12-33 


HV22716C 


12-74 


HV3622C 


11-38 


HV5408DJ 


11-73 


HV1814X 


12-33 


HV22716P 


12-74 


HV3806DG 


11-43 


HV5408PG 


11-73 


Ul\/1 D1RP 
nv lol Ou 


1 O OQ 




1 O 7/1 


n VooUoru 


11 /I O 
11 -4o 


U\ ICA HOD I 


1 1 7Q 

11 -/o 


HV1816CS 


12-33 


HV22716WG 


12-74 


HV3806X 


11-43 


HV5408X 


11-73 


HV1816P 


12-33 


HV22716X 


12-74 


HV4122DJ 


11-51 


HV5522DJ 


11-78 


HV1816PJ 


12-33 


HV22814C 


12-74 


HV4122PJ 


11-51 


HV5522PG 


11-78 


HV1816X 


12-33 


HV22814P 


12-74 


HV4122X 


11-51 


HV5522PJ 


11-78 






liwooqi /I D 1 


1 1 7/1 

1^-/4 




1 1 d 




1 1 7Q 

J l -to 


HV20420P 


12-59 


HV22814WG 


12-74 


HV4222PJ 


11-51 


HV5530DJ 


11-78 


HV20420PJ 


12-59 


HV22814X 


12-74 


HV4222X 


11-51 


HV5530PG 


11-78 


HV20420X 


12-59 


HV22816C 


12-74 


HV4522DJ 


11-56 


HV5530PJ 


11-78 


HV2114C 


12-41 


HV22816P 


12-74 


HV4522PG 


11-56 


HV5530X 


11-78 


U\/01 -t AD 


l*i-4 1 


UIV/OOQ1 CD I 

nv^ol or J 


1 O "7/1 

1^-/4 


Ll\MEOOD 1 

nV4o^rJ 


1 1 cc 

11 -bb 




1 1 7Q 


HV2114PJ 


12-41 


HV22816WG 


12-74 


HV4522X 


11-56 


HV5622PG 


11-78 


HV2114X 


12-41 


HV22816X 


12-74 


HV4530DJ 


11-56 


HV5622PJ 


11-78 


HV2116C 


12-41 


HV3137PG 


11-21 


HV4530PG 


11-56 


HV5622X 


11-78 


HV2116P 


12-41 


HV3137X 


11-21 


HV4530PJ 


11-56 


HV5630DJ 


11-78 


Uf\/01 1 CD I 


1 £-41 


n VooU4UJ 


A 1 Oft 
1 1 -£b 


uvMcQnv 
nV4ooUA 


1 1 cc 

n-bb 


nvbboUru 


1 1 7Q 
11-/0 


HV2116X 


12-41 


HV3304PJ 


11-26 


HV4622DJ 


11-56 


HV5630PJ 


11-78 


HV21714C 


12-65 


HV3304X 


11-26 


HV4622PG 


11-56 


HV5630X 


11-78 


HV21714P 


12-65 


HV3418DG 


11-28 


HV4622PJ 


11-56 


HV5708DJ 


11-84 


HV21714PJ 


12-65 


HV3418PG 


11-28 


HV4622X 


11-56 


HV5708PJ 


11-84 


Ul\ /O i 7 "1 /I \A/^* 

nv£l /14Wu 


1 2-65 


1— 1\ /Q A 1 QT 

n V J4 I O I 


1 1 -28 


nV4boUUJ 


11-56 


Ul\/C7r\QV 

nvo/UOA 


11-84 


HV21714X 


12-65 


HV3418X 


11-28 


HV4630PG 


11-56 


HV57708DG 


11-131 


HV21716C 


12-65 


HV341C 


12-83 


HV4630PJ 


11-56 


HV57708PG 


11-131 


HV21716P 


12-65 


HV341MC 


12-83 


HV4630X 


11-56 


HV57708X 


11-131 


HV21716PJ 


12-65 


HV341MWG 


12-83 


HV4937PG 


11-62 


HV5808DJ 


11-84 


nV<i I / I DVVo 


-tO 

1^-OD 


n V o4 1 r 


1 O QO 


U\/^QQ7V 

nV4yo/A 


1 1 CO 


U\/C£>nDD 1 

nvDoUorJ 


11-84 


HV21716X 


12-65 


HV341WG 


12-83 


HV500D 


11-89 


HV5808X 


11-84 


HV21814C 


12-65 


HV341X 


12-83 


HV500DJ 


11-89 


HV6008DJ 


11-104 


HV21814P 


12-65 


HV343C 


12-83 


HV500P 


11-89 


HV6008PG 


11-104 


HV21814PJ 


12-65 


HV343MC 


12-83 


HV500PJ 


11-89 


HV6008PJ 


11-104 


kJ\/01 Q1 AVtiir* 

rlv^i 1 o 14Wu 


1 2-65 


HVo4JlVrVVL3 


12-83 


nvoOUA 


11-89 


HvoOOoX 


11-104 


HV21814X 


12-65 


HV343P 


12-83 


HV501D 


11-94 


HV6506PJ 


11-109 


HV21816C 


12-65 


HV343WG 


12-83 


HV501 DJ 


11-94 


HV6506X 


11-109 


HV21816P 


12-65 


HV343X 


12-83 


HV501P 


11-94 


HV6810D 


11-114 


HV21816PJ 


12-65 


HV345C 


12-83 


HV501 PJ 


11-94 


HV6810P 


11-114 


UW01 111 fi\A/iO 


1 O fil^ 

I t-oo 






nvoUl A 


11-94 


nVool UrJ 


11 11/1 


HV21816X 


12-65 


HV345MWG 


12-83 


HV5122DJ 


11-67 


HV6810WG 


11-114 


HV2214C 


12-50 


HV345P 


12-83 


HV5122PG 


11-67 


HV701PG 


11-141 


HV2214P 


12-50 


HV345WG 


12-83 


HV5122PJ 


11-67 


HV701X 


11-141 


HV2214PJ 


12-50 


HV345X 


12-83 


HV5122X 


11-67 


HV7022DJ 


11-119 


HV2214X 


12-50 


HV348C 


12-83 


HV518P 


11-99 


HV7022PJ 


11-119 


HV2216C 


12-50 


HV348MC 


12-83 


HV518PJ 


11-99 


HV7022X 


11-119 



Device Page # 


Device 


Page# 


Device 


Page# 


Device 


Page# 


HV702PG 


11-147 


HV9110PJ 


13-22 


HV9708PJ 


11-168 


RBHV343C 


12-83 


HV702X 


11-147 


HV9110X 


13-22 


HV9708X 


1 1 -1 68 


RBHV345C 


12-83 


HV711PG 


11-141 


HV9111C 


13-22 


HV9808DJ 


11-168 


RBHV348C 


12-83 


HV711X 


11-141 


HV9111NG 


13-22 


HV9808PJ 


11-168 


RBHV3806DG 


11-43 


HV712PG 


11-147 


HV9111P 


13-22 


HV9808X 


11-168 


RBHV4122DJ 


11-51 


HV712X 


11-147 


HV9111PJ 


13-22 


LND150N3 


8-15 


RBHV4222DJ 


11-51 


HV7225D(ji 


11-125 


■ iv i r\ a a a \y 

HV9111X 


13-22 


LND150N8 


8-15 


i—j r—> I i\/rrtArv 

RBHV500D 


11-89 


nV7225Po 


11-125 


HV9112C 


13-22 


LND150ND 


8-15 


RBHV500DJ 


11-89 


HV7225X 


11-125 


HV9112NG 


13-22 


LP0701N3 


7-1 


RBHV501D 


11-94 


HV7708DO 


11-131 


HV9112P 


13-22 


LP0701ND 


7-1 


RBHV501DJ 


11-94 


HV7708PG 


11-131 


HV9112PJ 


13-22 


MP690MD 


14-30 


RBHV5122DJ 


11-67 


1 IV /77AQV 

HV7708X 


11-131 


HV9112X 


13-22 


MP690MP 


14-30 


RBHV5222DJ 


11-67 


HV7808UC3 


1 1 -1 36 


HV9113C 


13-22 


MP690P 


14-30 


RBHV5308DJ 


11-73 


HV7808PC3 


11-136 


HV9113NG 


13-22 


MP691MD 


14-30 


RBHV5408DJ 


11-73 


HV7808X 


11-136 


HV9113P 


13-22 


MP691MP 


14-30 


RBHV5708DJ 


11-84 


HV7908DG 


11-131 


HV9113PJ 


13-22 


MP691MWG 


14-30 


RBHV57708DG 


11-131 


HV7908PG 


11-131 


lit tf\A A IV 

HV9113X 


13-22 


MP691 P 


14-30 


r-* i—j i i \ /rnnA l~\ I 

RBHV5808DJ 


11-84 


HV7908X 


11-131 


HV9114C 


13-29 


MP691WG 


14-30 


RBHV6810D 


11-114 


HV8308DJ 


11-153 


HV9114NG 


13-29 


MP692P 


14-30 


RBHV7022DJ 


11-119 


HV8308PJ 


11-153 


HV9114P 


13-29 


MP692MD 


14-30 


RBHV7225DG 


11-125 


HV8308X 


11-153 


HV9114X 


13-29 


MP692MP 


14-30 


RBHV7708DG 


11-131 


i iv /o ji Ann i 

HV8408DJ 


11-153 


HV9117C 


13-29 


ft A |-fc /^r~\r-\tL A T~\ 

MP693MD 


14-30 


RBHV7808DG 


11-136 


HV8408PJ 


11-153 


HV9117NG 


13-29 


MP693MP 


14-30 


RBHV7908DG 


11-131 


HV8408X 


11-153 


HV9117P 


13-29 


MP693MWG 


14-30 


RBHV9308DJ 


11-163 


HV8708DJ 


11-158 


HV9117X 


13-29 


MP693P 


14-30 


RBHV9408DJ 


11-163 


HV8708PJ 


11-158 


HV9120C 


13-31 


MP693WG 


14-30 


RBHV9708DJ 


11-168 


HV8708X 


11-158 


HV9120P 


13-31 


MP694MD 


14-30 


RBHV9808DJ 


11-168 


ui/oonon i 

HV8808DJ 


11-158 


HV9120PJ 


13-31 


MP694MP 


14-30 


RCMP690D 


14-30 


uuoonoD I 

HV8808PJ 


11-158 


HV9120X 


13-31 


MP694P 


14-30 


RCMP691D 


14-30 


HV8808X 


11-158 


HV9123C 


13-31 


MP695MD 


14-30 


RCMP692D 


14-30 


HV9100C 


13-1 


HV9123P 


13-31 


MP695MP 


14-30 


RCMP693D 


14-30 


HV9100P 


13-1 


HV9123PJ 


13-31 


MP695MWG 


14-30 


RCMP694D 


14-30 


HV9100PJ 


13-1 


HV9123X 


13-31 


MP695P 


14-30 


RCMP695D 


14-30 


HV9101 P 


13-1 


HV9124C 


13-38 


MP695WG 


14-30 


RCMP696D 


14-46 


t_j\ A4 n i 

HV9101PJ 


13-1 


HV9124P 


13-38 


MP696MD 


14-46 


RCMP697D 


14-46 


HV9102C 


13-1 


HV9124PJ 


13-38 


MP696MP 


14-46 


SD2P 


14-59 


HV9102P 


13-1 


HV9124X 


13-38 


MP696MWG 


14-46 


SD2WG 


14-59 


HV9102PJ 


13-1 


HV9127C 


13-38 


MP696P 


14-46 


TC0604WG 


10-24 


HV9103U 


13-1 


HV9127P 


13-38 


MP696WG 


14-46 


TN0102N2 


7-9 


HV9103P 


13-1 


HV9127PJ 


13-38 


MP697MD 


14-46 


TN0102N3 


7-9 


HV9103PJ 


13-1 


HV9127X 


13-38 


MP697MP 


14-46 


TN0102ND 


7-9 


HVy l UoP 


13-8 


HV9220C 


13-40 


MP697MWG 


14-46 


TN01 04N2 


7-9 


LJWfH ACD I 

nvyi UorJ 


13-8 


HV9220P 


13-40 


MP697P 


14-46 


TN0104N3 


7-9 


Hvy 1 Uor 


13-15 


HV9220PJ 


13-40 


MP697WG 


14-46 


TN0104N8 


7-9 


HV9106PJ 


13-15 


HV9220X 


13-40 


RBHV0322DG 


11-3 


TN0104ND 


7-9 


HV9108P 


13-8 


HV9308DJ 


11-163 


RBHV0408DG 


11-9 


TN0106N2 


7-5 


|_J \ /OH AOD 1 

HV9108PJ 


13-8 


HV9308PJ 


11-163 


RBHV04H08DG 


11-15 


TN0106N3 


7-5 


HV9109P 


13-15 


HV9308X 


11-163 


RBHV0522DG 


11-3 


TN0106ND 


7-5 


HVQIflQP 1 
nvi7 i uuru 


I o- I o 


HV9408DJ 


11-163 


RBHV0608DG 


11-9 


TN0110N2 


7-5 


HV9110C 


13-22 


HV9408PJ 


11-163 


RBHV06H08DG 


11-15 


TN0110N3 


7-5 


HV9110NG 


13-22 


HV9408X 


11-163 


RBHV3304DJ 


11-26 


TN0110ND 


7-5 


HV9110P 


13-22 


HV9708DJ 


11-168 


RBHV341C 


12-83 


TN0520N2 


7-13 



1-3 



Device 


Page # 


Device 


Page # 


Device 


Page # 


Device 


Page # 


1 INUD^iUINo 


7 If) 




1 -to 




7-87 


\ZNim4RMP 

V INUO^tOIN^i 


8-31 


TN0520ND 


7-13 


TN2524ND 


7-45 


TP2535ND 


7-87 


VN0345N5 


8-31 


TN0524N2 


7-13 


TN2535ND 


7-49 


TP2540N3 


7-87 


VN0345ND 


8-31 


TN0524N3 


7-13 


TN2540N8 


7-49 


TP2540N8 


7-87 


VN0350N1 


8-31 


TN0524ND 


7-13 


TN2540ND 


7-49 


TP2540ND 


7-87 


VN0350N2 


8-31 


! INUOooINo 


7 17 


1 INUOOOINO 


7 R1 


t VJoUU I INO 


1 n 9Q 
i u-^y 


V INUoOUINO 


ft Q1 
O O I 


TN0535ND 


7-17 


TN2635ND 


7-61 


TQ3001N7 


10-29 


VN0350ND 


8-31 


TN0540N3 


7-17 


TN2640N3 


7-61 


TQ3001 NF 


10-29 


VN0355N1 


8-35 


TN0540ND 


7-17 


TN2640ND 


7-61 


VC0106N6 


10-32 


VN0355N5 


8-35 


TN0602N2 


7-33 


TP0102N2 


7-63 


VC0106N7 


10-32 


VN0355ND 


8-35 




7-9ft. 




7-63 


V I VU I <JH\ *C. 


R-1Q 
o i y 




o-oo 


TN0602ND 


7-33 


TP0102ND 


7-63 


VN0104N3 


8-19 


VN0360N5 


8-35 


TN0604N2 


7-33 


TP0104N2 


7-63 


VN0104N5 


8-19 


VN0360ND 


8-35 


TN0604N3 


7-33 


TP0104N3 


7-63 


VN0104N6 


8-19 


VN0535N2 


8-41 


TN0604ND 


7-33 


TP0104N8 


7-63 


VN0104N6 


10-33 


VN0535N3 


8-41 


1 INUOU'tVVO 


7 ft9 




7 fi^ 
/ -DO 




ft-1 Q 




o -£ f I 


TN0604WG 


10-25 


TP0602N2 


7-75 


VN0104N7 


10-33 


VN0540N2 


8-41 


TN0606N2 


7-21 


TP0602N3 


7-75 


VN0104N9 


8-19 


VN0540N3 


8-41 


TN0606N3 


7-21 


TP0602ND 


7-75 


VN0104ND 


8-19 


VN0540ND 


8-41 


TN0606N5 


7-21 


TP0604N2 


7-75 


VN0106N2 


8-19 


VN0545N2 


8-45 


1 INUOUOINO 


7 91 
l-c. I 


I rUOU'UNO 


7 7^ 
f-fO 


V INU I UOINO 


ft 1Q 

o- i y 


V INUO'tOINO 


ft AR 


TN0606N6 


10-26 


TP0604ND 


7-75 


VN0106N5 


8-19 


VN0545ND 


8-45 


TN0606N7 


7-21 


TP0604WG 


7-75 


VN0106N6 


8-19 


VN0550N2 


8-45 


TN0606N7 


10-26 


TP0604WG 


10-27 


VN0106N6 


10-33 


VN0550N3 


8-45 


TN0606ND 


7-21 


TP0606N2 


7-67 


VN0106N7 


8-19 


VN0550ND 


8-45 


t INUO 1 UIN^ 


7 91 
l-c. I 


1 rUOUOINO 


7 ft7 


V INU I UOIN / 


1 n 

I u-oo 


VINUDUDL 


ft R1 
O D I 


TN0610N3 


7-21 


TP0606N5 


7-67 


VN0106N9 


8-19 


VN0610LL 


8-61 


TN0610N5 


7-21 


TP0606N6 


7-67 


VN0106ND 


8-19 


VN0635N2 


8-49 


TN0610ND 


7-21 


TP0606N6 


10-28 


VN0109N2 


8-19 


VN0635N3 


8-49 


TN0620N2 


7-25 


TP0606N7 


7-67 


VN0109N3 


8-19 


VN0635N5 


8-49 


1 INUO^UINO 


7 9R 


1 nUOUOIN * 




V INU I uyiNO 


ft-1 Q 
o i y 


V INUDOOINU 


ft-<4Q 


TN0620N5 


7-25 


TP0606ND 


7-67 


VN0109N9 


8-19 


VN0640N2 


8-49 


TN0620ND 


7-25 


TP0610N2 


7-67 


VN0109ND 


8-19 


VN0640N3 


8-49 


TN0624N2 


7-25 


TP0610N3 


7-67 


VN0116N2 


8-23 


VN0640N5 


8-49 


TN0624N3 


7-25 


TP0610N5 


7-67 


VN0116N3 


8-23 


VN0640ND 


8-49 


I IMUD£*HMO 


7 OR 


1 rUD 1 UINU 


7 R7 
f-XDf 


V INU I I DINO 


ft 9*3 


V INUD'fOlN^ 


ft f^T 


TN0624ND 


7-25 


TP0616N2 


7-71 


VN0116ND 


8-23 


VN0645N3 


8-53 


TN0635N3 


7-29 


TP0616N3 


7-71 


VN0120N2 


8-23 


VN0645N5 


8-53 


TN0635ND 


7-29 


TP0616N5 


7-71 


VN0120N3 


8-23 


VN0645ND 


8-53 


TN0640N3 


7-29 


TP0616ND 


7-71 


VN0120N5 


8-23 


VN0650N2 


8-53 


I IMUDf UINU 


7 9Q 

/ -^y 


I rUO^iUINii 


7 71 


\/Mm onMn 

V INU I *iUINLJ 


ft OQ 


v INUDOUINo 


ft 

o-oo 


TN0702N3 


7-37 


TP0620N3 


7-71 


VN0300B 


8-39 


VN0650N5 


8-53 


TN0702ND 


7-37 


TP0620N5 


7-71 


VN0300L 


8-39 


VN0650ND 


8-53 


TN2501 N8 


7-57 


TP0620ND 


7-71 


VN0335N1 


8-27 


VN0655N2 


8-57 


TN2501ND 


7-57 


TP2502N8 


7-91 


VN0335N2 


8-27 


VN0655N3 


8-57 


TM9^n9Mn 
1 Ivi^OU^lNL^ 


/ JO 


TP9^fl9Mn 

1 "tOUtlNU 


7 Q1 

/-y i 


V INUooOIND 


ft Q7 


V INUOOOINO 


ft t^7 


TN2504N8 


7-53 


TP2506ND 


7-79 


VN0335ND 


8-27 


VN0655ND 


8-57 


TN2504ND 


7-53 


TP2510N8 


7-79 


VN0340N1 


8-27 


VN0660N2 


8-57 


TN2506ND 


7-41 


TP2510ND 


7-79 


VN0340N2 


8-27 


VN0660N3 


8-57 


TN2510N8 


7-41 


TP2516ND 


7-83 


VN0340N5 


8-27 


VN0660N5 


8-57 


TN2510ND 


7-41 


TP2520N8 


7-83 


VN0340ND 


8-27 


VN0660ND 


8-57 


TN2520ND 


7-45 


TP2520ND 


7-83 


VN0345N1 


8-31 


VN0808L 


8-63 



1-4 



Device 


Page# 


Device 


Page# 


Device 


Page* 


Device 


Page# 


VN10KN3 


8-65 


VN2410L 


8-101 


VP0350ND 


9-13 


VP1310N2 


9-45 


\/mi nk'WQ 


ft 

O-DO 


WMOC1 CI 


OH ftO 
o* I UO 


V r UOOOIN^l 


Q-1Q 

y i y 


\/P1 T1 ON'} 
V r I O 1 UINO 


Q AR 


VN1106N2 


8-69 


VN4012B 


8-103 


VP0535N3 


9-19 


VP2104N3 


9-49 


VN1106N5 


8-69 


VN4012L 


8-103 


VP0535ND 


9-19 


VP2104ND 


9-49 


VN1106ND 


8-69 


VP0104N2 


9-1 


VP0540N2 


9-19 


VP2106N3 


9-49 


VN1110N2 


8-69 


VP0104N3 


9-1 


VP0540N3 


9-19 


VP2106ND 


9-49 


V IN I I I UINO 


ft-fiQ 
O OS 


V rU I UM-IMO 


Q-1 

3 I 




Q-1 Q 

y- 1 y 


V r c. I I UINo 


Q-AQ 

y-fy 


VN1110ND 


8-69 


VP0104N6 


9-1 


VP0545N2 


9-23 


VP2110ND 


9-49 


VN1204N2 


8-73 


VP0104N6 


10-34 


VP0545N3 


9-23 


VP2204N2 


9-53 


VN1204N5 


8-73 


VP0104N7 


9-1 


VP0545ND 


9-23 


VP2204N3 


9-53 


VN1204ND 


8-73 


VP0104N7 


10-34 


VP0550N2 


9-23 


VP2204ND 


9-53 


V IN I iUDD 


ft-77 
o-/ / 


v rvj i u^+ino 


Q-1 


V ruooUINO 


Q.OQ 

y-d.o 




y-oo 


VN1206D 


8-77 


VP0104ND 


9-1 


VP0550ND 


9-23 


VP2206N3 


9-53 


VN1206L 


8-77 


VP0106N2 


9-1 


VP0635N2 


9-27 


VP2206ND 


9-53 


VN1206N2 


8-73 


VP0106N3 


9-1 


VP0635N3 


9-27 


VP2210N2 


9-53 


VN1206N5 


8-73 


VP0106N5 


9-1 


VP0635N5 


9-27 


VP2210N3 


9-53 




8-73 


VrUI VJOIND 


Q-1 


V rUDODINU 


Q-97 

y t / 


V rc.c. I UINU 


y-oo 


VN1210L 


8-77 


VP0106N6 


10-34 


VP0640N2 


9-27 


VQ1000N6 


10-35 


VN1210N2 


8-73 


VP0106N7 


9-1 


VP0640N3 


9-27 


VQ1000N7 


10-35 


VN1210N5 


8-73 


VP0106N7 


10-34 


VP0640N5 


9-27 


VQ1001P 


10-40 


VN1210ND 


8-73 


VP0106N9 


9-1 


VP0640ND 


9-27 


VQ1004J 


10-42 


V IN I OU*+IN£ 


ft-7Q 
o-/» 


V rU 1 UOINLJ 


Q-1 


VrUDtDlNt 


Q T1 

y-o i 




1 n ao 


VN1304N3 


8-79 


VP0109N2 


9-1 


VP0645N3 


9-31 


VQ2001P 


10-44 


VN1306N2 


8-79 


VP0109N3 


9-1 


VP0645N5 


9-31 


VQ2006P 


10-46 


VN1306N3 


8-79 


VP0109N5 


9-1 


VP0645ND 


9-31 


VQ3001N6 


10-29 


VN1310N2 


8-79 


VP0109N9 


9-1 


VP0650N2 


9-31 


VQ3001N7 


10-29 


VM1 T1 flNIT 

V IN 1 O I UINO 


R-7Q 

o / y 


v ru i uyiMU 


Q-1 

y i 


v ruoouiNO 


Q *31 

y-o i 


VvJoUUl INr 


1 Pi OQ 


VN1706B 


8-83 


VP0116N2 


9-5 


VP0650N5 


9-31 


VQ7254N6 


10-29 


VN1706D 


8-83 


VP0116N3 


9-5 


VP0650ND 


9-31 


VQ7254N7 


10-29 


VN1706L 


8-83 


VP0116N5 


9-5 


VP0808B 


9-35 






VN1710L 


8-83 


VP0116ND 


9-5 


VP0808L 


9-35 






V IN^U 1 UL 


o-oo 


\/Dni onMo 
VrU l tL\j\\c. 


y-o 


vrl UUob 


9-35 






VN2106N3 


8-87 


VP0120N3 


9-5 


VP1008L 


9-35 






VN2106ND 


8-87 


VP0120N5 


9-5 


VP1106N2 


9-37 






VN2106NF 


8-87 


VP0120ND 


9-5 


VP1106N5 


9-37 






VN2110N3 


8-87 


VP0300B 


9-17 


VP1106ND 


9-37 








ft fl7 

o-o/ 


\/DnQCini 
VrUJUUL 


y-i / 


\/D1 1 i nMo 


9-37 






VN2110NF 


8-87 


VP0335N1 


9-9 


VP1110N5 


9-37 






VN2206N3 


8-91 


VP0335N2 


9-9 


VP1110ND 


9-37 






VN2206ND 


8-91 


VP0335N5 


9-9 


VP1204N2 


9-47 






VN2210N3 


8-91 


VP0335ND 


9-9 


VP1204N5 


9-41 






\/M99i rtMn 

V v\£.£. \ UNU 


H Q1 

o-y i 


V rUO'tUIN 1 


Q Q 

y-y 


\/pi nftdMn 
vrl £U4InU 


9-41 






VN2220N2 


8-95 


VP0340N2 


9-9 


VP1206N2 


9-41 






VN2220N3 


8-95 


VP0340N5 


9-9 


VP1206N5 


9-41 






VN2220ND 


8-95 


VP0340ND 


9-9 


VP1206ND 


9-41 






VN2222LL 


8-99 


VP0345N1 


9-13 


VP1210N2 


9-41 






WM00O4MO 
V IN^^^tlN^ 


ft QC. 

o-yo 


V nUo^fOtN^ 


Q 1 Q 

y- 1 o 


\/P1 OiriMC 
Vr l£l UINO 


9-41 






VN2224N3 


8-95 


VP0345N5 


9-13 


VP1210ND 


9-41 






VN2224ND 


8-95 


VP0345ND 


9-13 


VP1304N2 


9-45 






VN2406B 


8-101 


VP0350N1 


9-13 


VP1304N3 


9-45 






VN2406D 


8-101 


VP0350N2 


9-13 


VP1306N2 


9-45 






VN2406L 


8-101 


VP0350N5 


9-13 


VP1306N3 


9-45 







1-5 



Product Nomenclature/Ordering Information 



DMOS Pro 



Products 



sx 



sxv . 



SJ = 



sc = 



RB = 



HI-REL 

Similar to 
JANTX 

Similar to 
JANTXV 

Similar to 
JAN 

Commercial 
Burn-in 

MIL-STD-883 
for Arrays 



FAMILY TYPE 

A = Lateral 

DMOS Arrays 

D = Vertical 

Depletion-Mode 
DMOS Discretes 

L = Lateral 

DMOS Discretes 
(Depletion-Mode 
and Enhance- 
ment-Mode) 

T = Low Threshold 
DMOS 
Discretes 

V = Vertical DMOS 
Discretes & 
Quads 



SX V 



N 01 09 N3 



POLARITY 

N = N-Channel 

P = P-Channel 

C = Complementary 
(2N & 2P) 

Q = Arrays 



FAMILY 


BVDSS 




PACKAGE TYPE 


NUMBER 


DIVIDED BY 10 












N1 




TO-3 


01 


01 


N2 




TO-39 


03 


02 


N3 




TO-92 


05 


04 


N5 




TO-220 


06 


06 


N6 




14 Pin Plastic DIP 


07 


09 


N7 




14 Pin Ceramic DIP 


11 


10 


N8 




TO-243AA(SOT-89) 


12 


16 


N9 




TO-52 


13 


20 


NA 




18 Pin Plastic DIP 


21 


24 


ND 




Die in Waffle Pack 


22 


30 


NF 




20 Terminal 


25 


35 






Ceramic LCC 


26 


40 


NW 




Die in Wafer Form 




45 


WG 




20 Lead SOW 




50 










55 










60 









(e.g., 09 = 90V) 



CMOS Products 

Encoder/Decoder 



E D - 5 P 





FAMILY 


NUMBER OF 


PACKAGE 




TYPE 


ADDRESS BITS 


TYPE 


ED 


= Programmable 


ED-5 = 


5 


PJ = Molded Plastic Surface Mount 




Encoder/Decoder 






J-Lead Chip Carrier 






DC-7 = 


7 


DC 


= Data Coder 






P = Molded Plastic DIP 






ED-9 = 


9 




ET 


= Encoder/ 






X = Dice 




Transmitter 


ED-11 = 


11 












WG = Small Outline Surface Mount 






ET-13 = 


13 








ED-15 = 


15 





1-6 



Smoke Detectors 



SD 2 P 



FAMILY TYPE PRODUCT PACKAGE TYPE 

DESIGNATOR 

SD = Smoke P = Molded Plastic DIP 

Detectors 2 

X = Dice 



HVIC Products 



RB HV 54 08 DJ 



J 



HI-REL 



FAMILY TYPE 



PRODUCT 



RB 



RC 



ABSOLUTE 





DESIGNATOR 


MAX VOLTAGE 


MIL-STD-883 HV = High Voltage IC 








DIVIDED BY 10 


processing 


03 


45 


93 








04 


46 


94 


04 


18 


MIL-STD-883 


05 


49 


97 


06 


20 


processing 


06 


51 


98 


except burn-in 


10 
12 


52 
53 


217 
218 


08 


22 




14 


54 


227 


10 


25 




15 


55 


228 


12 


27 




16 


56 


341 




18 


57 


343 


14 


30 




21 


58 


345 


16 


37 




22 


60 


348 




25 


65 


500 


(e.g., 22 


= 220V) 




26 


68 


501 




30 


70 


518 








31 


72 


577 








33 


77 


622 








34 


78 


701 








35 


83 


702 








36 


84 


711 








38 


87 


712 








41 


88 










42 


91 









PACKAGE TYPE 

P = Plastic DIP 

C = Ceramic Side Brazed 

D = CERDIP 

T = T.A.B. Tape 

X = Dice 

CS = Ceramic Chip Carrier - 
STD Bent Leads 

DG = CERDIP Gullwing 

NG = Narrow Body Gullwing 

PG = Plastic Gullwing 

WG = S.O.W. Gullwing 

DJ = Quad CERDIP J Lead 

PJ = Quad Plastic J Lead 



1-7 



Alphanumeric Index and Ordering Information 

Corporate Profile 

Applications Notes ie 

Quality Assurance and Handling Procedures Wi 

Process Flow |« 

Selector Guides and Cross Reference I* 

N- and P-Channel Low Threshold MOSFETs Wi 

DMOS N-Channel Discretes |; 

DMOS P-Channel Discretes l! 

DMOS Arrays and Special Functions i[l 

High Voltage Driver/Interface ICs ill 

High Voltage Analog Switches and Multiplexers iK 

High Voltage Power Supply ICs iK 

CMOS Consumer/Industrial Products H 

Surface Mount Packages and Lead Bend Options i\j 

Package Outlines Hi 

Die Specifications ift 

Representatives/Distributors ill 



Corporate Profile 



Success Through Innovation 



Supertex designs and manufactures complex proprietary and 
industry-standard integrated circuits (ICs). Ourcustomers include 
the medical, data processing, military, telecommunications, instru- 
mentation, and consumer product industries. Throughout the 
years the company has developed several advanced technologies 
utilizing high-performance Complementary Metal Oxide Semicon- 
ductors (CMOS) and Double-Diffused MOS (DMOS) processes. 

In 1 980, Supertex pioneered high voltage integrated circuitry with 
its proprietary HVCMOS ' technology, a merging of the CMOS and 
DMOS process technologies onto one chip. Supertex HVCMOS 
chips have the "brains" and low power consumption of CMOS ICs 
and the high voltage output of DMOS FET transistors. 



These advanced HVCMOS ICs, as well as Supertex's families of 
CMOS and DMOS products, provide performance and cost ben- 
efits, giving customers a competitive edge in developing their 

Supertex now focuses on two process technologies, DMOS and 
HVCMOS, which allows for a diversified product mix of integrated 
circuits and MOS field effect transistors (FETs) and arrays. The 
Company's products are targeted for application-specific markets 
such as ultrasound imaging for medical electronics, flat-panel 
display terminals and high reliability products for military systems. 
Supertex has earned domestic as well as international recognition 
as a demonstrated technological leader in high voltage semicon- 
ductor products. 



Product Development Milestones 



Supertex has continued the commitment to product and techno- 
logical development to enhance and complement our existing 
product lines. Supertex is a recognized world leader in high voltage 
ICs and MOSFET innovations. While responding to market de- 
mands for state-of-the-art products, the Company maintains a 
leadership position as an industry innovator, evidenced by the 
product development milestones listed below: 

1976 Industry leader in CMOS wafer foundry technology and 
production. 

1977 Patent filed for silicon-gate high power VMOS process. 

First in the industry to introduce both N and P-channel 
silicon-gate VMOS power FETs. 

1 978 State-of-the-art high voltage 500V power VMOS FET intro- 
duced. 

1 979 Development of combined bipolar and DMOS technologies 
(Superfet™). 

High Voltage DMOS/CMOS IC technology developed for 
medical ultrasonic imaging applications. 

Widest product offering for CMOS encoder/decoder ICs, 
using Manchester coding. 

1980 First in the industry to introduce high voltage DMOS lateral 
arrays. 

1981 First to develop fully TTL-compatible CMOS logic ICs. 

1 982 First fully integrated electroluminescent (EL) flat panel dis- 
play driver chip set, including gray scales. 



1983 First to introduce 64-line density EL display driver ICs. 

1984 First HVCMOS IC to be used in a major plotter program. 

MVIC (40-volt) and HVIC technologies developed for wafer 
foundry production. 

1985 First Hi-Rel HVCMOS display driver IC in the industry. 

Introduction of industry'sfirstlowthresholdN-channel power 
MOSFET family. 

1986 Introduction of low cost, low power 32-channel flat panel 
display driver ICs. 

Introduction of industry's first low threshold P-channel power 
MOSFET family. 

First to introduce 8-channel high voltage level translator 
chip. 

1 987 Introduction of 32-channel complements (N and P-channel) 
for high voltage, high current push-pull applications. 

Introduction of low power 32-channel AC plasma flat panel 
display driver ICs. 

1 988 Introduction of 32-channel 300V complementary (N and P- 
channel) high voltage ICs for electrostatic plotters and ATE 
bareboard testers. 

Joint market introduction of microprocessor supervisory 
chips. 

Introduction of first commercial gray-shade/video analog 
display driver ICs. 

(continued) 



2-1 



Product Development Milestones (con 

1989 Introduction of second generation low power high voltage 
analog multiplexers with CMOS control logic. 

Introduction of single chip 225V push-pull IC with CMOS 
control logic. 

Introduction of 64-channel second generation 80V push-pull 
ICs with CMOS control logic and 400V open drain ICs. 



1990 Implementation of macro-cell custom capability in high 
voltage ICs. 




1992 Introduction of current mode power supply family utilizing 
high and low voltage bi-CMOS processes. 



Custom Wafer Foundry 



Supertex specializes in HVCMOS and DMOS Wafer Foundry 
production providing state-of-the-art wafer fabrication for Cus- 
tomer-Owned-Tooling (COT) production. Standard as well as 
modified processes can be produced per specific customer re- 
quirements. Engineering and pre-production volumes can be run 



with very short throughput times. Supertex can also support the 
customers' needs for back-end packaging and testing. 

In addition, Supertex can also run standard metal-gate CMOS and 
PMOS processes. 



2-2 



Alphanumeric Index and Ordering Information HI 

Corporate Profile p 

Applications Notes ic 

Quality Assurance and Handling Procedures E 

, ■ , Process Flow ■« 

Selector Guides -and Cross Reference I» 

N- and P-Channel Low Threshold MOSFETs WM 

DMOS N-Channel Discretes M»M 

DMOS P-Channel Discretes M 
DMOS Arrays and Special Functions 

High Voltage Driver/Interface ICs if H 

High Voltage Analog Switches and Multiplexers iMB 

High Voltage Power Supply ICs iKfl 

CMOS Consumer/industrial Products iiSf 
Surface Mount Packages and Lead Bend Options 

Package Outlines i[*H 

Die Specifications IM 

Representati ves/D istri butors i 



Chapter 3 - Applications Notes 

AN-D1 DMOS FET Electrical Performance 3-1 

AN-D2 Low-Threshold MOSFETs: Structure, Performance and Applications 3-5 

AN-H3 Basics of EL Panel Drive Techniques 3-9 

AN-C4 Cascading Encoder-Decoder 3-12 

AN-C5 DC-7, ED-5, ED-9, ED-11 Applications 3-15 

AN-C6 Encoder-Decoders for Power Line Carrier Remote Control 3-21 

AN-C7 Encoder-Decoders for Telemetry and Control 3-24 

AN-D8 High Voltage Pulser Circuits 3-29 

AN-D9 Battery Back-Up Utilizes Low Threshold MOSFETs 3-33 

AN-D10 Off-Line Compact Universal Linear Regulator 3-36 

AN-D11 ±500 Volt Protection Circuit 3-39 

AN-D12 High Voltage Ramp Generator 3-41 

AN-H13 Designing High-Performance Flyback Converters with the HV9110 and HV9120 3-43 

AN-D14 Low Dropout 3.0 Volt Linear Regulator 3-57 

AN-D15 Understanding MOSFET Data 3-62 

AN-D1 6 Constant Current Sources and Depletion-Mode FETs 3-68 

AN-D17 High Voltage Off-Line Linear Regulator 3-70 

AN-D1 8 Constant Current Sources and Depletion-Mode FETs 3-75 

AN-D19 High Voltage Level Translator for Motor Drives 3-76 

AN-H20 HVCMOS Drivers for Non-Impact Printing 3-80 



Supertax inc. 



DMOS 
Application Note 

AN-D1 



DMOS FET Electrical Performance 



The electrical behavior of MOSFETs has been explained by 
numerous authors. A different, and non-traditional way of viewing 
their behavior arises when the device structure is closely exam- 
ined. The source and body regions comprise one side of a diode, 
with the drain region being the other side. A voltage on the gate 
allows carriers to flow from source to drain through an induced 
surface channel. Figure 1A shows the forward and reverse 
current vs. voltage characteristics of a diode, while Figure 1B 
shows the current vs. voltage characteristics of a MOSFET. 









V GS = 6V 








V GS = 4V 


,6V 




.6V 


V GS = 2V 




— v GS = ov 




- — 450V — ► 




- — 450V — ► 



1.2 




0' I I I ' I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 

-50 -25 +25 +50 +75 100 125 150 175 200 



Temperature (°C) 

Figure 3: 

Normalized V vs. Temperature for the VN03 Transistor 



A. Diode Characteristics B. Gated Diode Characteristics 
Figure 1 

A MOSFET is characterized by a set of parameters different in 
many ways from a bipolar transistor. The parameters specified in 
a MOSFET data sheet are defined and briefly explained below: 

A. V QS(TH) -The gate threshold voltage. It is defined as the voltage 
from gate to source required to produce a specified drain 
current. For ease of measuring, the drain is commonly shorted 
to the gate. (The measurement circuit is shown in Figure 2.) 




Figure 2: 

N-Channel V QS(TH) 
Measurement 



Threshold current is usually measured at a current in the range of 
1 to 10mA. (Threshold voltage measurement can be normalized 
to the amount of source perimeter when comparing different size 
transistors. Full current is usually obtained at V GS = V GS(TH) + 8 volts 
(N-channel). The threshold voltage is af unction of temperature as 
shown in Figure 3 for a 500 volt Supertex transistor. The decrease 
in the measured value of V is primarily caused by thermally 
generated carriers or leakage current that add to the induced 
surface current flow, thus decreasing the amount of applied 
voltage needed to obtain a specified current. 



B. I GSS - The gate to body leakage current. It is measured with 
drain and source at ground, and gate biased to specified 
voltage. NOTE: Due to input capacitance, large die size 
MOSFETs may prove difficult to measure with automatic test 
equipment, unless a preconditioning test is performed to 
charge the gate capacitance prior to test. (See Figure 4 for the 
measurement circuit.) 

This leakage current results from current flow through the insulat- 
ing layer of silicon dioxide surrounding the gate. Typical DC- 
leakage currents are in the picoampere range between the 
temperatures of -55°C and +200° C. This value is well below the 
level of concern in most power conversion circuits. When an on- 
chip diode is incorporated between the gate and the source, the 
leakage current, which is that of a reverse-biased diode, doubles 
approximately every 10°C. 

C. I DSS - The zero gate voltage drain current or offstate leakage 
current. It is determined by applying specified voltage from 
drain to source (with gate shorted to source) and measuring 
the resulting current. (See Figure 5 for the measurement 
circuit.) 

This leakage current is that of a reverse-biased diode. As with a 
reverse-biased diode, this current is a measure of the integrity of 
the structure and may degrade under extremes of voltage and 
temperature. 

D. BV DSS - The breakdown voltage of drain to source with gate 
shorted to source. It is determined by forcing a specified 
current from drain to source and measuring the resulting 
voltage. Properly designed MOSFETs should not have a 
latchback breakdown and a low current measurement is 
sufficiently accurate. (See Figure 6 for the measurement 
circuit.) 



3-1 




SOURCE 





DMOS Applications 

GATE 

O 



Figure 4: N-Channel I Measurement 




Figure 5: N-Channel l DSS Measurement 




Figure 6: N-Channel BV DSS Measurement 



Ids + Aln 





Figure 8: Parameters Affecting MOSFET Transconductance 

These parameters are shown in Figure 8. The forward transcon- 
ductance is proportional to source perimeter, hence proportional 
to chip area. For a given device area, maximizing the source 
perimeter results in a maximum value of g m . This parameter is also 
increased by decreasing the gate dielectric thickness, but this 
approach limits the total voltage swing on the gate because of 
the dielectric strength of silicon dioxide (60V/1000A of Si0 2 ). 
Typical gate oxide thicknesses are in the 1000A range. In 
MOSFETs, the transconductance vs. V GS varies as shown in 
Figure 9 for a 500 Volt VNQ3 MOSFET. 




V OS = 10V 
300usec pulse 
2% duty cycle 



Figure 7: N-Channel G (s Measurement 



2 4 6 8 10 

l D(ON) — Drain Current On-State (Amps) 



This parameter is most likely to degrade if exceeded for an 
extended period of time in high voltage applications, because of 
the large current (and, hence, high power dissipation that may 
occur). A lower clamping breakdown voltage diode from source- 
to-drain will prevent degradation of the parameter. 

E. g fs org m -The small signal forward transconductance. It is the 
ratio of AI D /AV GS measured for a 10% change in drain current 
at a specified quiescent drain bias point. 

This parameter depends on device structure as shown in the 
equation below (see Figure 7 for measurement circuit): 
uoff Ze ox 



where _Z 
L 

Ho* 

u 



Source perimeter 
Channel length 
Effective carrier mobility 
Gate Dielectric constant 
Gate oxide thickness 



o 

£ 

E. 

ED 
O 

c 

co 2 



H 1 

I 

E 

CD 















































/ 


























r v DS - iuv 
300usec pulse 














2°, 


i du 


y cy 


cle 









































































































8 



10 



V es — Gate-Source Voltage (Volts) 
Figure 9: Transconductance vs. Drain Current or 
Gate-Source Voltage for the VN03 



3-2 



DMOS Applications 




Figure 10: N-Channel R DS(0N) Measurement 



F. R DS(ON) - The static drain-source on-state resistance. It is 
measured as the drain-source voltage divided by the drain 
current at specified values of drain current and gate source 
voltage. (See Figure 10 for the measurement circuit.) 

The on-state resistance of a high voltage MOSFET is dominated 
by the resistance of the drain region. For a given breakdown 
voltage and device area, there is a minimum value of R DS(ON) - The 
variations in source geometries and body-to-drain breakdown 
structures discussed earlier are all aimed at realizing this mini- 
mum R DS(ON) value. In device operation, R DS(ON) may appearto be 
considerably higher than at room temperature. This behavior 
occurs because the heating of the device decreases the carrier 
mobility, thus reducing the current for a given voltage. This 
behavior for a 500 volt VN03 MOSFET is shown in Figure 1 1 . This 
negative feedback characteristic is the key to MOSFETs thermal 
stability. 

G. l D(ON| - The on-state drain current. It is measured at specified 
values of drain-source and gate-source voltage. NOTE: To 
reduce heating of the device, this should be performed in a 
pulse mode, or with an adequate heat sink. (See Figure 1 2 for 
measurement circuit.) 



2.21 




-50 -25 25 50 75 100 125 175 200 
T — Temperature (°C) 
Figure 1 1 : R DS(ON) as a Function of Temperature for the VN03 



Transfer Characteristics 



10 

I 
E 

~ 8 
o 

§ 

co 

§ 6 



c 
Q 

I 2 

























300u.sec pulse 
2% duty cycle 





















































































































































































50 V n 



20 V D 



10 V n 



4 6 8 

- Gate-Source Voltage (volts) 



10 



Figure 13: l n(0N) as a function of 

Gate-Source Voltage for the VN03 

The on-state drain current is proportional to the amount of source 
perimeter and the total chip area. Since current flow causes 
device heating, the pulsed value of l D(ON) is considerably greater 
than the steady state value because of the increasing value of 
r dsion) witn temperature. This specific behavior is shown by the 
dotted line for the VN03 in Figure 13. 

H. Capacitances - MOSFETs are characterized by three capaci- 



1 . C lss : Input capacitance 

2. C oss : Common source capacitance 

3. C RSS : Reverse transfer capacitance 

These measured capacitances are related to device structure as 
shown in Figure 14. We see from this figure that the value of C |ss 



Gate 




Ciss = C GS + C DG (unguarded) 
Crss = Cdg (guarded) 
Coss = C DS + C DG (unguarded) 

1 Drain c D 

Figure 14: DMOS Transistor Capacitance 




Figure 12: N-Channel I Measurement 



Gate 

O 



^ds s r DS IqGfs'Vg 



' 



Drain 

-O 



■s^GS < r DS 



Source 

Figure 15: FET Equivalent Circuit — Small Signal 



3-3 



for a dual layer access structure will be correspondingly greater 
per unit area than an interdigitated structure. With these capaci- 
tances, a simple small signal equivalent circuit may be derived as 
shown in Figure 15. This equivalent circuit is also useful in more 
elaborate transient analysis. These three capacitances have 
been measured over temperature, with no appreciable tempera- 
ture dependence found. 



DMOS Applications 

Conclusion 

The MOSFET is a device with its own set of electrical parameters. 
These parameters depend on the device structure. The success 
with which MOSFETs are used will depend on a designer's 
understanding of these electrical parameters and their limits. This 
article has attempted to link the performance of MOSFETs to their 
optimum design and processing and to establish some physical 
limits for optimum performance. 





TN/TP Series 
Application Note 

AN-D2 



Low-Threshold MOSFETs: 
Structure, Performance and Applications 



Since an increasing amount of attention is being focused on 
system interface from low-level logic, the need for higher current 
and/or low on-resistance at drive levels of only 3-5 volts has 
become a major concern. Supertex has always known of the 
importance of the gate drive consideration and has been offering 
N-channel low-threshold devices with threshold voltages of 2.4 
and 1 .6 volts for many years. Additionally, standard and low- 
threshold versions of P-channel DMOS devices are available. To 
understand the reasons that low-threshold processing requires 
very specialized techniques, one needs to understand the DMOS 
structure. 



DMOS Structure 

Most double-diffused MOS (DMOS) structures have very similar 
cross-section characteristics, as shown in Figure 1 . For conduc- 
tion to occur, a channel of electrons is needed between the gate 
and the source. This potential produces an inversion layer called 
the channel. The depth of this layer is the limiting factor in allowing 
current flow between the drain and source terminal. The greater 
the voltage applied, the deeper the induced channel; resulting in 
more current flow. The voltage needed to invert the channel 
region is called the threshold voltage V GS(lh) . However, when 
examining most manufacturers' databooks, one finds V G de- 
fined as the voltage needed to produce a specified drain current 
(l D ). This differs from the theoretical definition of knowing when a 
channel is produced, which is of little interest to MOSFET users. 
Comparing V GS at the same l D simplifies the analysis of 
databook parametric guarantees, allowing the designer to com- 
pare the product to actual needs. 

The control of the threshold voltage is dependent on many factors, 
such as dopant concentration, gate-to-silicon work function and 
surface change. The greater the body dopant concentration, the 
larger the applied voltage needed to produce a channel, which 
translates to a higher threshold voltage. One method of reducing 
threshold voltage is to reduce the body dopant concentration until 
the required V GS is met. This technique by itself is dangerous 
because it degrades other device parameters. The first and most 
important of these is drain-source breakdown (BV DSS ), which is a 
result of certain conditions, most commonly punch-through. 



Poly 



Punch-through is defined as the drain voltage needed to create an 
electric field connecting the drain and source, as shown in Figure 
2, at voltages less than the actual BV DSS rating. 

The susceptibility to punch-through increases dramatically as the 
body dopant concentration is lowered. There is an optimum body 
dopant level that is needed in order to stay away from the punch- 
through mechanism, but this concentration is too high for low 
thresholds. This is one of the reasons why P-channel devices 
typically have higher thresholds, because the optimum body 
dosage is higher than N-channel FETs. 

Another technique, used by some manufacturers, is to lower 
threshold by reducing the gate oxide thickness. Again, there are 
trade-offs using this method: (1 ) The input capacitance increases 
which will effect the switching speed efficiency and (2) the 
maximum gate voltage rating is decreased, making it more 
susceptible to input voltage spikes. 

Supertex has developed a proprietary technique to successfully 
lower threshold voltage without these major trade-offs. This 
method mainly depends on modifying the diffusion profile and 
altering the charge distribution to produce low-threshold N- and P- 
channel devices. This process, which makes use of Supertax's 
interdigitated design structure, allows typical thresholds of 1.1 
volts for N-channel and 1 .8 volts for P-channel, DMOS devices. 

An added benefit of Supertax's design is the lower input capaci- 
tance achieved by the interdigitated geometry, rather than the 
more conventional closed cell approach. Less charge is needed 
to control the device input. Therefore, it can be concluded that a 
lower threshold device will start conducting earlier for a given gate 
drive and allow control of larger drain current than a higher 
threshold device. 

The availability of such low-threshold DMOS devices insures the 
performance needed to be driven by low level logic systems, in 
which the maximum voltage available is only 3-5 volts. 
















— n 



drain 

Figure 1: Double Diffused MOS (DMOS) 



Figure 2: Electric Field Connecting Drain and Source 



TN/TP Series Applications 



Part Number 


IRF 520 


VN12105 


Unit 


Parameter 


Min 


Max 


Conditions 


Min 


Max 


Conditions 


V 

GS(lt>) 

Gate Threshold Voltage 


2.0 


4.0 


V DS = V GS . l D = 250uA 


0.8 


2.4 


V ds = V gs. l D = 10mA 


V 


id ,on) On-State 
Drain Current 


8.0 




^DS > 'd(ON) X 
R DS(ON) maX 

v GS = iov 


20.0 




V ds = 25V 

v GS = iov 


A 


5.0 




V ps = 25V 
V gs = 5V 


A 


r ds ( on) state Drain - 
to-Source On Resistance 




0.3 


v GS = iov 

l D = 4.0A 




0.3 


v GS = iov 

l n = 10.0A 


Q 


0.45 


V os = 5V 
l D = 2.0A 


a 



Table 1 : Comparison between MOSFET and standard threshold Supertex device 



Performance Advantages 

With the first device shipped in 1 982, Supertex was the pioneer in 
low-threshold DMOS FET technology and still maintains a per- 
formance edge over other manufacturers. Supertex currently 
supplies the lowest threshold MOSFETs in the industry. A thresh- 
old voltage of 1 .6 volts for N-channel and 2.4 volts maximum for 
P-channel clearly supports this claim. 

Supertex measures threshold voltages at l D = 1 mA, 2.5mA, and 
10mA for small, medium and large-sized devices, respectively. 
Although some manufacturers use test conditions as low as l D = 
250uA for large devices, Supertex devices, in comparison, still 
have lower values of threshold voltages at highervalues of l D . See 
Table 1 for a comparison between a popular MOSFET and a 
standard-threshold Supertex device. 

A true comparison can be made by normalizing the value of the 
l D test condition. The threshold voltage for VN1210N5 will be 
lower than 2.4 volts, maximum, when it is tested at l D = 250uA. 
Supertax's test conditions therefore portray a realistic picture of 
the device's capabilities at low V conditions. 



300 



a 



100 









TN0 


















J 





12 3 4 

V GS (volts) 



Figure 3: Typical Transfer Characteristics 



The threshold voltage is an important indicator of performance at 
low V GS conditions because a device that starts conducting at a 
very low bias will exhibit good characteristics under such condi- 
tions. In fact, R DS(ON) , maximum, and I minimum, at low V QS 
conditions are much more important than just the threshold 
voltage value because quiescent gate voltage conditions are 
usually at least a few volts above the V QS value. Figure 3 shows 
the transfer characteristics of a standard-threshold and a low- 
threshold device. For example, if the drain current requirement is 
100mA, TN0520N3 will typically need V QS = 1.8 volts and 
VN0220N3 will require 2.8 volts to achieve this value. In case a 2.8 
volts drive is not available, as in many applications, a VN0220N3 
will be incapable of functioning in the circuit. In spite of the TN05 
die being half the size of a VN02, the TN0520N3 performance is 
far superior at low gate to source voltages. 

When confronted by low gate drive voltage, a designer basically 
has two choices: 

Approach 1 : Use a large industry-standard-threshold device to 
obtain the required low R n „,„.„, maximum and L,„ K ,,, 

^ DS(ON)' D(ON)' 

minimum values. L__. can be obtained from the 

D(ON) 

transfer characteristics and R„.,_.,. values will be 

DS(ON) 

read off the typical saturation or output characteris- 
tics. 

Approach 2: Compared to the device used in Approach 1 , use a 
relatively small (die size), low-threshold device to 
achieve the desired l D(0N) and R DS(ON) at the given 
minimum gate-to-source voltage. 

Comparison of Approach 1 and 2 

1 . Large die always have larger parasitic capacitance and conse- 
quently slower switching speeds. This could pose a restriction 
in many applications, where limited gate drive charging current 
is available. 

2. Large die must be accommodated in large packages, and this 
may result in unnecessary waste of board space. For example, 
the total volume occupied by a TO-220 package including 
stand off could be 8 to 1 times more than a TO-92 package. 



3-6 



TN/TP13 Series Applications 



•noi: 



Power Supply/ 
Battery Charger 
with float 
and equalize mode 




Figure 4: Motor of a Fluid Injection Pump 



3. A judicious choice using smaller die in a smaller package can 
result in considerable cost savings. With more silicon and 
several times the raw material content for packaging, a low- 
threshold TO-92 will definitely be a much more cost-effective 
alternative. 

Supertex publishes R DS(ON) , maximum, and l D minimum, speci- 
fications at V GS = 5 volts (see Table 1 ). This data is very useful to 
a designer because it is always desirable to rely on guaranteed 
values instead of typical curves. Typical curves are based on a 
high statistical probability of the majority of devices closely 
meeting values on the curves. They do not 100% guarantee 
performance of all devices. Manufacturing tolerances and some 
variations from one fabrication lot to another are likely to cause 
lower than expected values of these parameters. Depending 
entirely on curves tends to be risky for production runs even if 
prototypes built earlier perform satisfactorily. 

The combined effect of low-threshold voltage and low-input 
capacitance is ease of drive, which is a key consideration in most 
circuits employing MOSFETs. What better trait can a designer 
expect than a small amount of charge controlling high voltages 
and large currents? These low-threshold FETs from Supertex are 
ideally suited to interface low-voltage logic to the outside world. 

Applications 

Low-threshold MOSFETs play a key role in circuit design when- 
ever there is a low gate-to-source voltage situation. Conventional 
devices are often very inefficient and sometimes unusable in 
some applications as follows: 



• Handheld, battery-operated equipment requiring satisfactory 
operation at low/end-of-discharge voltages. This is necessary 
for complete utilization of battery energy. Inadequate turn-on of 
a FET can cause two problems: A) loss of control signal or 
data; or B) loss of power due to resistive losses. Supertex TN/ 
TP series devices are being used for a variety of data acquisi- 
tion and remote-control applications. 

• Medical equipment with battery backup is another popular 
application. Figure 4 shows the motor of a fluid injection pump 
powered by the utility supply and backed by a NiCad battery. 
The V„ = 6 volts condition demands careful attention, because 

GS 

the R Dg(ofg) has to be low in order to ensure a low drain to source 
voltage drop. A large voltage drop can A) affect motor perfor- 
mance, and B) cause high l 2 R losses, reducing system effi- 
ciency and battery back-up time. 




, i U— J 1 o 

Figure 6: Charge Pump Converting 5VDC to 12VDC 



Photovoltaic 
Diode Stack 



Control I I 
Signal I I 



4^ 

AS i 



Figure 5: Photovoltaic Drive Scheme 



• Solid-state relays utilize optically-isolated drive schemes for 
isolation purposes. Figure 5 shows a commonly-used pho- 
tovoltaic drive scheme. Usually a low voltage is available to turn 
on the FET to meet the relay's assured R DS(ON) specifications. 
Precautions are taken to avoid excessive drive since the charge 
applied during turn-on must be quickly discharged during turn- 
off. Turn-off circuitry is not shown in this simplified schematic. 

• Figure 6 shows a simple charge pump converting 5V dc to 1 2V dl! . 
The key parameter for efficient functioning of this circuit is 
R DS, ON > at V gs = 5 volts - 

• Telephone handsets encounter wide variations of voltage dur- 
ing normal operation (Figure 7). While the DC voltage appear- 



3-7 



ing across the unit may vary from approximately 3 to 25 volts 
when the phone is off the hook, high voltage AC ringer signals 
and associated transients have to be handled safely. Moreover, 
atmospheric disturbances (e.g., lightning and RF radiations) 
are picked up by the lines, inducing high voltages which are 
suppressed by MOVs, gas discharge tubes, etc. (not shown in 
the figure). 

Supertex low-threshold TN05 devices used for the pulser and 
mute switch operate satisfactorily, even at voltages as low as 3 



TN/TP Series Applications 

volts. A TN0524N3S guaranteed I minimum = 100mA at V QS 
= 3 volts is more than adequate for this purpose. 

Advances in low-threshold MOSFET technology offer several 
useful choices to a designer. Circuit design for many applications 
are simplified and use of components is minimized. Conse- 
quently, system complexity is reduced and reliability enhanced. 
All these benefits, combined with the cost-effectiveness of the 
devices, make the low-threshold FETs an excellent choice. 



Receiver 




Figure 7: MOSFETs in a Telephone Handset 



3-8 



^ Super tex inc. 



HVCMOS 
Application Note 

AN-H3 



Basics of EL Panel 



Thin film electroluminescent (EL) panels operate on a principle of 
successive pulses of opposite polarity. These pulses must ex- 
ceed a threshold of approximately 200V for the panel to emit light. 

A flat panel display is a sandwich of phosphor material with 
dielectric coating on either side; transparent ITO (Indium Tin 
Oxide) row electrodes on one side and column electrodes on the 
opposite side. These layers are built up on a sheet of glass to form 
a very thin, lightweight display panel. 

Since the drive electrodes are dielectrically isolated from the 
phosphor material, and each other, the display panel exhibits a 
capacitive load to the drive electronics. On larger panels this 
capacitance can be quite high. Surge currents can be large; 
therefore, coupling from the row to the column electrodes should 
be considered. 

The drive electronics used to operate the panel are organized in 
a manner to surround the display panel with contacts as shown in 
Figure 1 . 

Generally, the row electrode electronics supply the major portion 
of the threshold voltage, called the scan pulse, and the opposite 
polarity "refresh" pulse , which is necessary for the panel to emit 
light. The refresh pulse is usually applied to all rows at one time 



Drive Techniques 

while the scan pulse is applied to one row at a time (starting with 
row #1 ), similar to a television raster scan. 

Depending on the data to be displayed in each column, the 
column electrode electronics supply a voltage of opposite polarity 
to the row scan pulse. This combination of row and column voltage 
across the phosphor will exceed the threshold and cause the 
phosphor in areas between the energized row electrodes and the 
energized column electrodes to glow. This sequence, applied to 
successive rows, causes certain portions of the display to be 
illuminated. 

Because the phosphor requires successive pulses of opposite 
polarity to operate, an opposite polarity refresh pulse is applied to 
all row electrodes simultaneously while the column drivers are 
kept at ground. The sequence then begins again at row #1 with the 
next frame of data. Figure 2 is a representative timing diagram of 
the signals applied to a TFEL panel showing the first four rows and 
the first column. 

Due to the fact that the phosphor illumination threshold has a 
slope of illumination versus applied voltage within a short range, 
the column drive electronics can be made to vary the applied 
voltage within this range, dictated by the intensity of light desired 
for a particular element on the display. By this means, a gray 
shade image can be created using the EL display. 



Lett Row 
Enable/Data o- 



Right Rowo- 
Enable/Clock 



Coupling 
Circuitry 



v scan' ref o — 



Top 
Data 



uatao-, nop 

HV77 



Bottom Data Input o- 
Column Clock c— 
Coiumn Enable o- 
Column Latch c— 




It 



likJ 



Electroluminescent display 
(512 x 256 pixels) 



TIF 



JL 



TIF 



J [ 



Figure 1: Block diagram of the driver system for a TFEL (Thin Film Electroluminescent) panel. 
Note that the column drivers have two data lines with interleaved pixel data. 



^ Q 



HVCMOS Applications 



Row 3 



Column 1 





v Scan 
V PP 



VRel 



Vscai 



J"|_ 



Figure 2: Simplified diagram illustrating row and column timing to operate an EL Panel. 

V HEF only lights pixels that were turned on by V SCAN and V pp pulses in the previous frame of information. 



Row Drivers (HV51, HV52, HV70) 

To allow the open drain outputs to provide the opposite polarity 
pulses to the panel, the sources of the output MOSFETs must be 
switched between the different voltages required for the panel. 

Since these MOSFET source connections are connected to chip 
ground, the entire device needs to be isolated or "floated" from the 
system ground. The control signals to the row driver chips 
therefore must be opto-isolated from the system ground. Figure 
3 shows a simplified way to accomplish this. 

The two high voltage supplies are switched to the row substrate 
(driver chip ground) using MOSFET switches. Application of the 
voltages to the panel is as follows: The refresh pulse is applied to 
the entire panel at the same time by pulsing on "C," forward 
biasing the body-drain diodes on all row outputs. The panel is 
returned to ground by pulsing "D" while having all the row driver 
outputs on . The scan pulse is applied, one row at a time, by pulsing 
on "A" while the selected row output is on. The selected row is 
returned to ground by turning on "B." The next row to be scanned 
is then selected, and the scan is repeated; first "A," then "B." When 
the entire panel has been scanned, the refresh sequence is 



executed; first "C," then "D." The scan cycle then begins again. 
In this way the proper voltages and sequences are applied to the 
panel for operation. 

Monolevel Column Driver (HV77) 

The column drivers are used to apply the data to be displayed onto 
the panel. The data for each row of picture elements (pixels) is 
loaded into all the column drivers serially and latched into the 
output latches. The outputs are thus turned to their desired state, 
and then the high voltage (V pp ) is applied. Columns selected for 
data display are connected to V pp through the CMOS output and 
are pulled up to V pp . The combination of the column V pp and the 
selected row voltage will cause selected pixels to light in that 
particular row. 

During the time that the data for one row is being displayed, the 
data for the next row is being loaded into the shift registers, 
awaiting the display of the next row. When a row is completed, the 
column driver V pp is brought low and the data waiting in the shift 
register is loaded into the output latches. The cycle then begins 
again for each successive row. 



3-10 



HVCMOS Applications 



The column drivers are designed with a serial shift register output 
for use in cascading the column drivers together. This allows the 
data for one row to be loaded serially, using one serial input at the 
first column driver device. 

Gray Scale Column Driver (HV38) 

This device is designed to take four data inputs in parallel into four 
shift registers. The data is then taken from equivalent stages of 
each shift register and converted to an analog level, 1 of 16 
between ground and V pp . This is done by a digital counter using 
four bits of input data. The counter is preset with data counting 
down to turn off a transistor. This transistor isolates a ramp input 
(VR) from an internal storage capacitor, which controls a CMOS 
output stage. The output voltage therefore represents the value of 
the ramp voltage (VR) at the time the counter for each output 
counted down. This voltage, applied to the column of the panel, 
combines with the row scan voltage to vary the light output from 
each pixel in the selected row. 



Panel Brightness 

The varying brightness of an EL panel by voltage variation can 
only achieve a limited range. Dramatically increased panel output 
such as required by panels to be operated in direct sunlight, 
requires another method of increasing output. This is done by 
increasing the panel frame rate, or refresh rate. Normal CRT 
based systems work on a 60Hz frame rate. Most applications of 
EL panels replacing CRTs, then, also operate at this rate. This is 
fine for office and home use but does not provide enough 
brightness to accommodate most military applications. By in- 
creasing the refresh rate up to tenfold, a dramatic increase in 
brightness can be achieved. 

This increase in refresh rate requires some changes in the column 
driver configuration. Instead of cascading all the column drivers 
together, each column driver shift register input is driven in parallel 
by the controlling system at the same time. This increases the 
number of data lines required but allows the data to be loaded 
much faster, enabling the faster frame rates desired. The row 
drivers are used at a much slower rate, so no changes are 
required to achieve faster operation. 




Row 
Logic 
Supply 



Logic 
Opto 
Isolator 



n 

L 



Control 
Logic 



iriver i 



._ J 



Row 

Electrode 



Q1.Q4 = VN0345N5 450V 
Q2.Q3 = VN0335N5 350V 



-190V Scan 

Figure 3: Row driver panel switching block diagram. 



3-11 



©ED Series 
Supertax fflC Application Note 



AN-C4 



Encoder-Decoder 



The Supertex family of encoder-decoder devices allows address 
matching of up to 32,768 different codes. Four bits of data can be 
sent to up to 2048 different receive devices. This has been 
adequate for the vast majority of applications. Some applications, 
however, require even more addressing capability than the larg- 
est part can offer. 

A cable TV control system, with which a cable company would 
want to control operation of all the decoders in their area, is one 
application in which the possible remote addresses could number 
more than 32,768. Another possible use is remote meter reading 
of domestic and industrial power meters by the local utility 
company. This offers tremendous savings in labor costs over 
manual meter reading. Both of these applications require a low 
cost, simple means of implementing single unit identity coding of 
a large number of remote devices. The Supertex ED devices offer 
this capability. 

Mode of Operation 

Figure 1 shows a simple means of cascading two ED devices to 
allow more than 1 .07 x 1 9 addresses. The basic requirement for 
using this design is that the transmission into the receiver consists 
of two ED-style data packets (preamble and data) separated by 
a short interval. The first data packet will go to the primary ED 
device (ED #1) and the second data packet will go to the 
secondary ED device (ED #2). These groups of two data packets 
must be separated by a much longer delay. Figure 2 is a timing 
diagram of the operation of this cascaded receiver. 



14538 > FU, 




Figure 1 



Primary Address 

Data Packet #1 
Preamble #1 Data #1 

J L_J 



Address Group 

A 



Secondary Address^ 
Data Packet #2 
Preamble #2 Data #2 



J 



ED #1 DV 



1 



IC #1 Q 



ED #1 D/DO ' 1 

Address Match 

ED #2 D/DO ! f 

Address Match 



ED #2 SDI 



Figure 2 

3-12 



ED Series Applications 



On initial condition, in which the receiver is waiting for an address 
group to arrive, one-shot IC #1 enables the incoming signal into 
the Start/Data Input (SDI) of ED #1 while disabling the path to ED 
#2. When the group arrives, the first data packet is input into ED 
#1 . When this data packet, both preamble and data, have been 
received by ED #1, the Data Valid (DV) signal will go high, 
triggering the one-shot. This will disable the SDI input to ED #1. 
If the data in data packet 1 matched the address data on the ED 
#1 data pins, then ED #1 Decode/Data Output (DDO) pin will also 
go high. This and the triggered one-shot enables the path from the 
signal input to the SDI pin of ED #2. The second data packet will 
then be received by ED #2 and compared to the data input pins. 
If the address matches, the ED #2 DDO will go high. 

The one-shot timing must be set to allow data packet 2 to be 
completely received before the one-shot times out and returns to 
the off condition. This time period will vary depending on the 
transmission speed of the communication link and the ED speed 
used. After both data packets have been received and the one- 
shot has timed out on all the receivers in the system, the 
transmitter can then send out a new address group. 

Address Decode 

The circuit shown in Figure 1 and described in the previous 
section implements the address decodefunction. The DDO pin on 
ED #2 should be connected to a device that operates on a positive 
going edge to signal the correct addressing of both ED #1 and 
ED #2. 



Different combinations of ED devices can give a different number 
of possible addresses. The following table illustrates these pos- 
sibilities: 



ED #1 


ED #2 


# of possible addresses 


ED-15 


ED-15 


1,073,741,824 


ED-15 


ED-9 


16,777,220 


ED-15 


ED-5 


1,048,576 



The ED-9 cannot be used in the ED #1 position because it does 
not have a DV output available. 



Address and Data 

Often it is necessary not only to address a particular device within 
a large number of devices in a system, but also to send some 
amount of data only to that device. The ED-1 1 and DC-7 devices 
easily implement this capability in the cascaded design. Figure 3 
illustrates a data transmission variation of the cascade circuit. 

The input controls for ED #1 and #2 operate the same as for the 
address matching case. In this case, however, the Serial Data 
Output (SDO) and Data Clock (DC) of ED #2 are connected to a 
4094 serial to parallel shift register. The SDO is connected to the 
Data In pin, while the DC is connected to the Clock pin to clock the 
data into the shift register. The rising edge of the ED #2 DDO 
signal is converted to a pulse and used to transfer the data from 
the shift register to the parallel output latches of the 4094 if the 




ED Series Applications 



address match is detected. The DDO pulse is also available from 
the receiver system as an interrupt to the external circuitry 
signalling the arrival of data from the transmitter. 



cn #1 
CD tF 1 


ED #2 


Data RItQ 


AriHrocc fnmhinatirinQ 
HUUIcbb ^Ul 1 1 Ul 1 Id UUIIo 


ED-15 


ED-11 


4 


67,108,864 


ED-15 


DC-7 


8 


4,194,304 


ED-15 


ED-5 


15 


32,768 "special case 


ED-5 


ED-11 


4 


65,536 


ED-5 


DC-7 


8 


4,098 


ED-5 


ED-5 


15 


32 "special case 



The special cases noted above represent a situation in which 1 5 data bits must 
be received. This is implemented by using ED #1 only for address matching 
and using ED #2 only for data reception. To receive 1 5 bits, two 4094s must be 
serially connected to form a 16 bit shift register. The Data Valid (DV) output of 
ED #2 would be connected in place of the DDO output to strobe the data into 
the latches of the 4094s. 



Transmitter 



The transmitter used to address this receiver design would 
normally be microprocessor controlled, with a peripheral adapter 
port connected to the data pins of an ED-1 5 device. The data pins 
could be changed to implement the data packet #1 and #2 by the 
much faster microprocessor. Alternatively, two ED-1 5s could be 
OR-gated to a transmission media and controlled by normal logic. 

Conclusion 

This application should help implement a simple low cost means 
to address a large number of remote devices in an addressing 
system. If there are any questions or suggestions for improve- 
ment, please contact the applications engineering department at 
Supertex. 



3-14 



Supertax inc. 



ED Series 
Application Note 

AN-C5 



DC-7, ED-5, ED-9, ED-11 Applications 



The Supertex "ED Family" of remote control encoder/decoder 
chips has almost unlimited uses. To make the user aware of some 
of the salient features of these unique ICs, we have put together 
this application note. When used in conjunction with the data 
sheet for these parts, most of the questions that may arise from 
attempts to design systems around them may be answered. 

Remote Control Systems 

As electronic systems become increasingly more sophisticated, 
the need to perform certain functions at a distance becomes 
increasingly important. In many cases, the need arises for central 
automatic control of remote operations. Here, too, remote control 
devices are necessary. Until recently, remote control of various 
functions required a plethora of discrete circuits, raising the cost, 
in many cases, to prohibitive levels. Recently the MOS LSI 
industry has responded with integrated circuits of varying useful- 
ness and complexity. Most of these ICs are geared to perform a 
single task such as opening garage doors, controlling TV func- 
tions, and the like. Until now, all remote control ICs were sold in 
a set; i.e., a separate encoder and decoder. The Supertex EDs on 
the other hand are a single chip. The encode/decode function is 
determined by a programming pin, which is tied to V DD for the 
encode function and V ss for the decode function. Having only one 
chip reduces the complexity of purchasing remote control. Spares 
are easier to stock, and reliability is enhanced. 

The Supertex EDs 

In addition to the "lock-and-key" feature of ED codability, the 
ED-1 1 has the feature of being able to transmit and receive 4 
additional bits of binary data which are available at the decoder's 




.025rT^3? 27 ^ 



uF T 10K 



6 25 
23 



4 ft 26 Data Valid 



- Data Clock 
" Decode Out 

-Data Out 



= =.045 uF 



4049 or 4069 
Trigger Circuit 
=1 KHz 



Figure 1 : Basic two-wire ED system 



output. The DC-7 has 8 bits of data. These can be used to perform 
tasks such as channel recognition (with digital readouts), micro- 
processor interface and event sequencing. This feature makes 
the ED family of encoders/decoders extremely versatile. 

Simple, Two-Wire Interface Utilizing ED-1 5s 

The basic application for the ED-1 5 is the simple two wire 
interface. This configuration is useful for optimizing ED parame- 
ters such as encoder/decoder frequency stability, and lockup 
time. It is also a useful way of observing waveforms and can be 
invaluable for troubleshooting a more complicated system using 
other transmission media. 

In Figure 1 , the output is not latched and will stay high only so long 
as the trigger circuit keeps cycling the encoder. The CMOS 
oscillator is necessary to produce the start pulse. By utilizing an 
oscillator, it is possible to get a continuous data stream. This is 
useful for observing all waveforms involved. The start pulse 
oscillator can even be used to trigger the scope, making the 
waveforms easy to sync. The wire used can be just a jumper when 
both encoder and decoder are on the same breadboard, but 
twisted pair or shielded cable should be used for long runs. 

ED-11, DC-7 System Utilizing 
Hardwire Transmission and 
Output Latches for Additional Data 

As stated earlier, one of the great features of the ED family of 
encoder/decoders is the ability of the ED-11 and ED-5 to transmit 
4 bits of binary code along with the "lock-and-key" recognition bits, 
the DC-7 to transmit 8 bits of binary code along with the "lock-and- 
key" recognition bits, and these 4 or 8 bits to appear at the data 
clock output of the receiver. This feature allows the transmission 
of useful data instead of just the "code valid" output common to 
otherso-called remote control encoder/decoders. The following is 
an adaptation of the hard-wired system seen above. The differ- 
ence is that even though an ED-1 5 is used for the encoder, an 
ED-1 1 is used for the receiver, and this data is decoded for use as 
a parallel latched data bus. Of course, since the last 4 bits in the 
ED-1 1 are used as actual transmitted non-dedicated data, it has 
only 2048 different possible code combinations instead of the 
32,768 combinations possible with the ED-1 5 system. The trigger 
circuit is the same as above and will be represented from here on 
only as a block diagram. 

In Figure 2, an ED-1 1 can be used for the transmitter as well as 
for the receiver. An ED-1 5 is shown to illustrate the compatibility 
of the ED family of encoder/decoders. The 401 5 in the circuit is a 
serial to parallel converter and the 4042 is a quad 4-bit latch. The 
data valid pinjs used to clock the parallel data into the latch and 
Q as well as Q outputs are available on this IC. The bit sequence 
chart is given below the schematic to show the relationship of the 
"key-code" bits to the last 4 data bits. 



3-15 



ED Series Applications 




TRIGGER 
CIRCUIT 









MXMXDxKKMXX^KKXK 



FOR 
VCONTROL 
OR 
DISPLAY 



Figure 2: ED system with latched parallel data out 



GND 



C T=f 



Start Signal 



FIXED 




ADDRESS 











XIXIXIXIXIXIXIXIXIXIXIXIXIXIX 



D 7 




Output 
Enable 
GND or V DD 



Figure 3: DC-7 system with latched parallel data out 



3-16 



ED Series Applications 



In Figure 3, a DC-7 can be used for the transmitters as well as for 
the receiver. An ED-15 is shown to illustrate the compatibility of 
the ED family of encoder/decoders. The 4094 in the circuit is a 
serial to parallel converter and an 8-bit latch. This circuit demon- 
strates the use of the DC-7 in which both the data and address can 
be transmitted from one location to another and both the data and 
address of the transmitter recovered. In an application in which 
only the data is to be recovered and a special address assigned 
to the receiver, the D/DO signal should be connected to the 4094 
and only the TOP 4094 used. In a system in which all incoming 
data and addresses are to be decoded the DV signal would be 
connected to both 4094s as shown. The bit sequence chart is 
given below the schematic to show the relationship of the "key- 
code" bits to the last 8 data bits. 

Infrared Transmission 

Often it is necessary to transmit data over some distance without 
wires. In such an instance it is necessary to couple the data (in this 
case from ED-series encoder/decoders) by way of some trans- 



mission media. Here is a simple but effective way to use IR as a 
medium for signalling between two EDs. 

The circuit in Figure 4 is designed so that the ED-1 5 is operating 
at 25KHz. The output of the chip (Pin 7) is applied to an NPN 
transistor gated with a 3.3KQ base resistor to act as a switch. The 
data stream turns the 2N4401 hard on or off depending upon the 
coded state. This in turn switches on and off the Monsanto 
MV5000 series infrared LEDs. Three of the LEDs are used to 
make aiming at the receiver easier. 

The receiver circuit consists of a three-stage amplifier (the CA 
3035) with Siemens BP1 04IR photo diodes arrayed for maximum 
coverage of the reception area. The output of the CA3035 is then 
applied to the ED-1 5 receiver chip and the signal is decoded in the 
normal way. The range of this set-up should be about 1 meters. 

Even though in this application the ED-15 is shown, it will work 
equally well with any of the other ED ICs. This application can be 
combined with the application in Figure 2 to provide 4 bits of 
parallel data or Figure 3 to provide 8 bits of parallel data to operate 
displays, relays, etc. 




+9V 

?SPST 
Momentary 



2N4401 



+15V 



+15V 



4 IR LEDS 
Monsanto 
MV 5000 Series 
or Equivalent 



Vdd 

Q 




Figure 4: IR remote control transmitter/receiver 

Vdd 






NC- 
NC- 
NC- 
NC- 



7 « 6 
Transmission 
Media 



0.1 
D 2 

D 3 
D 4 
Ds 
D 6 
Oj 
D 6 

D 9 _ 

D10 

Bii 

D12 
D13 
D 14 

D,5 

Data In 



DV 
DRS 
DO 
SDO 



SERIAL TO 
PARALLEL 
DECODER 
LATCH 

SEE FIG. 2 



-oO, 



^>0 4 



Figure 5: Block Diagram showing basic configuration for transmitting 
microprocessor data over remote control system using ED-1 1s as encode/decode 

3-17 



ED Series Applications 




Figure 6: ED system illustrating "handshaking" capabilities of Supertex ED-1 1s 



Normal or Receive Mode 
DB 6 /. 1 



Transmit Enable 



DB 5 



Trigger Pulse 

_nZ 



D/DO 



JHJlJnJTJTXlJXrTJTJlJlJ-L 

Preamble Burst 



t_J 11 . !& 



Lock and Key Data 

Figure 7: Possible timing diagram for circuit shown in Figure 5 



Microprocessor Interface to ED-11, ED-5 

It is possible to use the ED-11 and the ED-5 in conjunction with an 
8-bit microprocessor to remotely control functions at a distance. 

Because of the Supertex ED system's "single chip" approach to 
encode-decode remote control, it is possible to use these ICs in 
a "hand-shaking" arrangement, allowing for 2-way communica- 
tion between 2 or more microprocessors with a 4-bit data word. To 
do this, an 8-bit up is required, 4 bits are used as data, and the 
remaining bits control the EDs and associated logic required to 
change the system from a data transmission system to a data 
receiving system. 

In Figure 6, an 8-bit microprocessor such as a 6502 or 6800 is 
used to enable the ED-1 1 or ED-5 to transmit data to another 8- 
bit microprocessor telling it to perform some function. When the 
transmitting uP is finished sending its message, it returns to the 
"receiver" mode. The interrogated uP then performs its function 
and switches itself to the "transmit" mode and sends confirmation 
back to the first uP. 

In Figure 7, a "possible" timing diagram is shown for such an 
application. One can see that DB6 or transmit enable is actuated 
first. With all of the gates shown in Figure 6 now in the "transmit" 
mode, DB5 sends out a trigger pulse to the ED chip. This initiates 
a data transmission (shown as D/DO in the timing diagram). At the 
end of this data transmission DB6 drops back low, returning the 
ED and data systems to the "receive" mode. For RF transmission 
the DB6 signal can also be used (via a buffer) to drive a relay to 



key the RF transceiver to the transmit mode. The uP software for 
such an application would have to be developed by the user, and 
the circuit diagram shown here is only a suggestion. Microproces- 
sor information used in this circuit is from the 6502 or 6800 
literature and assumes its use. 



ED "Carrier Current" One-Way 
Remote Control System 

In the following application (Figure 8), the AC power lines running 
through a house or office building are used to transmit data from 
one ED to another. Such a system is an ideal way to interconnect 
multiple smoke alarms, turn on or off appliances from a central 
location, or monitor energy use in the home or plant. 

This particular circuit (Figure 9) utilizes 160KHz as the transmis- 
sion frequency. The reason that this frequency is used is that it has 
been shown that "around" 160KHz is the best compromise 
between noise and capacitive attenuation of typical building 
wiring. One of the major problems with "carrier current" commu- 
nication devices is that house wiring is a very difficult transmission 
medium. Most building codes require that buildings be wired with 
a large two-conductor solid wire called "ROMEX." Since both 
conductors are jacketed together, the capacitance between them 
is quite high and the attenuation of high frequencies is consider- 
able. To compound this problem many building codes require that 



3-18 



ED Series Applications 



the wiring be conduited. This will be found mostly in commercial 
and multiple-dwelling buildings, but since the conduit is ground, 
the capacitance is even greater. Another problem with building 
wiring as a communication medium is the fact that many appli- 
ances hooked to the wiring are large inductive loads (motors, 
power transformers, etc.). When these inductors are in parallel 
with the ROMEX, very effective high frequency filters are formed. 



External Oscillator for 
ED-15, ED-11, ED-5, DC-7 

Often it is desired to drive the ED-series devices with an external 
clock. Due to external considerations it is not recommended in the 
general case. 

+18V V 

>560, V2 Watt 

•"""^L^Att J W - MNIer No. 905B 
K-,VN0104N2 Subminiature RF Coil 
D f 650uH — 1 .3mH 




18V i 



Figure 8: Carrier Current Transmitter 



.0005uF 




+18V 



IN4001 



If 



1000uF 

^ 25V 



— 300, 

1/2 Wattf 
+18V 



001|xF_ 



7654321 
565PLL 

8 9 1011 12 13 14 



-18V 



~1 System 
J_ ~=GND 
1000nF 
25V 



+18V 



-18V 




6V Zener 



V74050 



> OUT 




7 6 4 3 2 1 
ED-15 Decoder 

27 28 



I 



0.1 uF 



Figure 9: Carrier Current Receiver. 1 60KHz transformer consists of an 1 8x1 1 mm ungapped pot core (Siemens, ferrocube, etc.) 

utilizing magnetics incorporated type "F" material wound with 80-1/2 turns of No. 35 wire for the secondary and 4-1/2 turns 
for the primary. This gives a turns ratio of approximately 15 to 1 . 

3-19 



However, the ED-1 5, ED-1 1 , ED-5 and DC-7 device types may be 
externally driven in the transmission mode if certain precautions 
are taken. Using the circuit in Figure 10 will allow driving of the 
transmitter chip. The external oscillator MUST be gated on only 
during the transmission time after the START pulse. During all 
other times the O/l pin MUST be held high. The DRS signal in the 
transmit mode is a convenient signal to use as a gate for this 
purpose. A 1 K£i resistor in series will minimize possible current 
spikes inside the device. The gates shown in Figure 1 should be 
CMOS logic and share the same V DD used on the ED device. 

The synchronizing characteristics of the ED series in the receive 
mode do not allow an external oscillator to be used. The use of the 
data sheet curves will allow calculation of the resistor and capaci- 
tor network to use on the receiver to match frequencies with the 
external clock of the transmitter. 



OSC 
Input 



ED Series Applications 
1K 



NC OC 



NC 



OR 



DRS 



Figure 10: External oscillator gate for ED-1 5, ED-11, ED-5, 
DC-7 transmission mode only. 



ED Series 
Application Note 

AN-C6 



Encoder-Decoders for Power Line Carrier Remote Control 



Power Line Carrier Communication is starting to emerge as a 
viable, cost effective means for control and information exchange 
in both consumer and industrial applications. 

Energy Management Systems for heating, air conditioning and 
lighting control are obvious examples of the use of the power line 
as a communication link. A system is shown in Figure 1 using 
Supertex Encoders and Decoders for transmitting and receiving 
control information overthe power line. The prototype system was 
designed to allow remote On/Off and brightness control for a 
fluorescent lighting fixture using a dimming ballast. The design 
was simple and implemented in about a week's time. 



System Description 

The system uses an ED Encoder-Decoder chip set to generate 
the Power Line control messages and to decode the messages for 
appropriate action. The system transmitter is able to selectively 
address 32 different receivers and transmit 16 different control 
commands to the receivers that are connected to the AC power 
line. 

The control message is coupled to the AC power line by a 
Signetics NE5050 Power Line Modem. The modem takes a serial 
bit stream, generated by the ED-9, and turns it into a series of 
1 25KHz bursts. Each burst represents a digital "1 " in the serial bit 
stream. This series of 125KHz bursts is transmitted overthe AC 
power line to any receiver that is coupled to the AC line. 

The series of 1 25KHz bursts are received by a second Power Line 
Modem and translated back into the original serial bit stream 
generated by the ED-9. This serial bit stream message contains 
address and control information. The message is decoded by an 
ED-5 to determine address match and control command. If the 
address does not match, then the rest of the message is ignored. 



When there is an address match at the receiver, the ED-5 will 
serially transmit the data information into the serial to parallel shift 
register. The data can then be decoded to determine which of the 
16 control commands was transmitted. 



Transmitter (Figure 2) 

The ED-9 performs address matching only. In this application, the 
9 bits that are available for addressing are split into 5 bits of 
address (D4, D5, D6, D7, D9) and 4 bits of control data (D1 2-D1 5). 
The 5 bits of address are set with dip switches, and the 4 data bits 
can be set with dip switches or a rotary selector switch. 

The transmission of a message is initiated by a pulse on the Start/ 
Data input (SDI). The message baud rate, f., is determined by the 
RC combination of 1 0K ohms and .039nf at the Ol, OR, and OC 
pins of the ED-9. 

f c = 0.375/RC = .961 KHz 

T c = 1/f c = 1.04ms 

Data Bit Width = 2T r = 2.08ms 



Data Clock Width : 



0.5T C = .52ms 



Power 
Line 
Modem 



Address Control 
Data Data 
Bits Bits 



AC Power Line 



ED-9 


d 

r 


ED-5 




D/DO 




SBI 


Power 
Line 
Modem 

Transmit 




Power 
Line 
Modem 

Receive 



Shift 
Register 



Figure 1 . System Diagram 



Figure 2. Transmit Circuit 



Message Format (Figure 3) 

The message (shown in Figure 3) consists of a preamble burst 
and a data transmission. The preamble burst is used to synchro- 
nize the receiver with the transmitter. 

The data transmission consists of 15 bits of information. In this 
application only 5 bits are used for address information and 4 bits 
for control information. The data transmission is Manchester 
encoded. Manchester coding uses the transition from low to high 
to represent a binary "1" and a transition from high to low to 
represent a binary "0." With this technique, the first half of each 
data bit time is always the logical inverse of the second half. This 



3-21 



ED Series Applications 



provides for a level transition during each data-bit time, and allows 
a synchronized receiver to easily read the correct data, even 
when large noise spikes are present. 



JTJTJTJT-TL^jT-TI T 

Sync Burst 

I 126 TC 



Input Bits D1-D15 




Figure 3. Message Format 
Receiver (Figure 4) 

The receiver uses an ED-5 in the receive mode by first checking 
the address of the incoming message against the preset 5-bit 
address in the receiver unit. If the address in the message 
matches the receiver address, then the 4-bit control data is 
serially shifted into the serial-to-parallel shift register. This 4-bit 
word is now available for further decoding and control. 

The message enters the device on the Start/Data Input (SDI) pin. 
The ED-5 then matches the message address information with 
the address of the receiver, and if the bits match, the Decode/Data 
Out (D/DO) pin goes high until the next stream of serial data 
arrives at the SDI pin. D/DO going high pulses the strobe input to 
the CD4094. This action resets the shift register, and the DC 
output from the ED-5 clocks the entire message into the shift 
register. The last four bits of the message (D1 2-D1 5) contain the 
control information (refer to Figure 5). The control information will 
be at the outputs of the shift register (Q1 -Q4) at the completion of 
the receive sequence. 



The AC Power Line 

The constraints imposed by the power line interface dictate the 
overall system operation. The power lines are a hostile environ- 
ment for signals. The noise on the power line can be put into two 
categories: broad band and impulse. The broad band noise 
levels vary from a few to hundreds of millivolts. Impulse noise 
levels can range from millivolts to tens of volts. Examples of noise 
sources are light dimmers, universal motors, hair dryers, induc- 
tion motors, radio and television receivers, and fluorescent lights. 
In general, noise levels in a factory environment will be much 
r than in a residential environment. 



The system described in this application note can, depending on 
the noise level, be affected by impulse noise on the power line. 
The communication link between the transmitter and receiver is 
an open loop one way command link. An impulse could cause 
false command decode if the impulse happened at the time when 
the receiver was decoding the control data section of the data 
transmission. The receiver would have to have properly received 
and decoded the address for the command to be improperly 
executed. 



T/R 



D/DO 



SDI 



ED-9 Transmitted Data Bits 



Ho 


o|o|x|x|x|x 





> 








I x 


X 


X | X | 


D1 
ED-5 


Received Address Bits 














D15 


hi. 


o|o|x|x|x|x 


o 




o 





I- 




D|.0| 



Address Bits 
D4-D7.D9 



Data Bits 
D12-D15 



r 
t 



D4-D7, D9 


— 1 


CD4094 




Control 






D/DO 


Strobe 

Data 

Clk 


Str 


Drivers 


ED5 


SDO 


Da 






DC 


Clk 








T/R 




XX 





















Power 
Line 
Modem 



| AC Power Line 

Figure 4. Receive Circuit 

Power Line Interface 

The Power Line Modem was calibrated to transmit a 125KHZ 
burst at a signal level of 7.5 volts p-p into a 50 ohm load. 
Impedances of residential wiring may be over 50 ohms while 
industrial impedances may be less than 1 ohm, with the receiver 
sensitivity set at 15 millivolts. 



Figure 5. Data Patterns 



Impulse noise could also cause errors in the address section of 
the data transmission, in which case the control command would 
be ignored due to improper address match. The effect of impulse 
noise on the operating system is not as much a problem with the 
encoder/decoder section but with the power line modem, which is 
improperly decoding the 125KHz bursts. 

The impedance of the line is likewise ill-defined. It may be 
resistive, inductive or capacitive. Line attenuation is difficult to 
estimate because it is extremely load dependent. A high-power 
load can significantly reduce the impedance of the line at the point 
of connection and thus dominate attenuation for all points of 
communication that occur beyond the offending load unless that 
load is isolated with chokes. Capacitive loads can be equally 
troublesome and are not necessarily associated with high-power 
loads. Another large component of the net attenuation can be the 
signal loss incurred in coupling across the multiple windings of a 
power distribution transformer. This alone can amount to 20 to 40 
db, depending on carrier frequency and transformer construction. 
The system described in this application will have problems 
communicating to the receiver units if the line attenuation is large 
enough to load the transmitted signal to a level below the receive 
sensitivity of the power line modem. 



ED Series Applications 



Designing for the Power Line Environment 

The application described in this paper is a relatively simple use 
of existing technology to achieve a low cost means of control 
communication over the AC power line. The system is very flexible 
with regards to the ability to add microprocessor intelligence to the 
transmit and receive ends of the communication link. This added 
intelligence may be used to overcome some of the problems 
associated with power line noise. 

The microprocessor could be used to allow both receive and 
transmit at the same location. The microprocessor would enable 
the use of a closed-loop communication link with the unit that is to 
be controlled. This ability could be used to obtain status reports 
from the control unit, to make sure the unit properly responded to 
control information. In the case of a unit not properly responding 
to control messages, the controller would simply resend the 
control message until the unit properly responds. The micropro- 
cessor software could also include algorithms that detect power 
line noise or other power line communication. When noise or 
communication is detected, the microprocessor would simply wait 
until the power line was quiet enough for it to transmit its control 
message. 



There are numerous methods for overcoming the problems 
associated with power line impedance. If the problem is due to the 
transmitted signal level, then line drivers can be added to boost 
the transmitted signal level. If the problem is due to cross phase 
attenuation caused by transformers, then a capacitor can be used 
to couple the communication signal across the windings. 

The primary problem that everybody is faced with when interfac- 
ing to the power line is that the communication media (power line) 
is different at each installation. The key is to offer a system that is 
flexible enough to adapt to the demands of the environment. 



Summary 

Flexibility of the Supertex Encoder-Decoder devices can be 
utilized to make practical a simple power line interface design that 
has the capability to transmit data bidirectionally as well as the 
simple address match On/Off function. This design is only a 
representation of the many possible new product designs that can 
result from the use of the Supertex Encoder-Decoder in power line 
systems. 



3-23 



ED Series 
Application Note 

AN-C7 



Encoder-Decoders for Telemetry and Control 



Today's industrial environment is the site of a modern revolution 
-the newest technology in control electronics is available for even 
the simplest task, at a reasonable price. New techniques of 
measurement offer increased speed and accuracy with low-cost 
simplicity. But, interfacing these components in the electrically 
noisy environment of a modern factory has proved to be a difficult 
problem. Motors, switches and other high-voltage, high current 
components used in afactory create a difficult environment forthe 
transmission of the digital signals of the new electronics technology. 

A device for maintaining digital data integrity while allowing simple 
transmission in a factory environment is needed. This device 
should be easy to interface with (or without) a microprocessor, 
offer serial transmission to minimize wiring, and be inexpensive. 
Additional features would include address recognition, so that 
several devices could be attached to the same control loop, and 
two-way communication capability. 

A family of products meets these requirements. Designed origi- 
nally for garage-door openers, this series of Encoder-Decoders 
has performed in many control and telemetry applications, includ- 
ing control loops, cordless phones, security systems, wildlife 
tracking, pagers, etc. Control loops are addressed here. 

Device Description 

ED Encoder-Decoders use an address-matching technique. They 
use CMOS technology to provide low power consumption for 
battery-operated systems. 

Table 1 lists the basic characteristics. The ED-9 performs ad- 
dress-matching only, in the smallest package for lowest cost. The 
DC-7 allows a combination of 7-bit data transmission for micro- 
processor applications. 

All can be used in either the Transmit or Receive mode by 
changing the logic level of the T/R pin. This allows the same 
device to be switched fortwo-way communications, thus reducing 
the cost and parts count. 

The devices have an on-chip oscillator, using only a resistor and 
capacitor to set the clock frequency for device operation. The 
basic clock frequency is 20KHz, with a serial transmission fre- 
quency being 1/4 that. The actual data flow rate, which must allow 
for preamble and delay times, works out to be one "word" every 
6.7ms. 



Device 


Number of 
Address Bits 


Number of 
Data Bits 


Serial 
Output 


ED5 


5 





Yes 


DC7 


7 


8 


Yes 


ED9 


9 





No 


ED11 


11 


4 


Yes 


ED15 


15 





Yes 



Table 1 . ED Series of Encoder-Decoders 



Data Transmission 

The data transmission for the ED family is a 15-bit serial data 
"packet" with a 1 2-bit preamble. The data is Manchester encoded 
to provide noise immunity. 

Manchester code (as implemented in the ED series) divides the 
time for each data bit in the serial string into two halves. A binary 
1 becomes a transition from low to high; a binary becomes a 
transition from high to low (Figure 1 ). The first half of each data bit 
time is always the logical inverse of the second half. This provides 
for a level of transition (high-to-low or low-to-high) during each 
data-bit time, and allows a synchronized receiver to easily read 
the correct data, even when large noise spikes are present. Figure 
1 illustrates the Manchester-encoding method. 

Each preamble burst, which is sent before the data bits, consists 
of 1 2 consecutive bits. The preamble is sent because the receiver 
of the transmitted signal, another ED family device, has no way of 
inherently synchronizing with the transmitter. The preamble burst 
allows a digital phase-locked loop (used in the Receive mode) to 
"lock in" to the transmitted signal. Then, when the actual data 
arrives, after the preamble, the Receive device can correctly 
extract the data from the bit stream. The Receive device also 
generates a clock signal which is in phase with the data stream 
(described later). 

In the Transmission mode of operation a pulse on the Start/Data 
Input (SDI) will initiate the transmission of the data packet. The 
device will send a complete data packet (preamble and data) for 
each pulse on the start pin. 

In the Receive mode, three functional options are available, 
depending on which device is selected: address matching, data 
recovery, or a combination of the two. All devices, when enabled 
in the Receive mode, accept a serial data packet generated by 
any other ED device. The serial data enters the device on the 
Start/Data Input (SDI) pin. The 12-bit preamble burst, which 
arrives first, is routed to the digital phase-locked loop to start and 
synchronize the R-C oscillator on the device. The 1 5-bit data word 
is the next to arrive. This is where the functional types differ. 

Matching Operation 

In the Receive mode, the data input pins are used to input data to 
be matched with the data received from the serial transmission. 
Each device is designed to "match" a different number of bits. If 
the bits on the data pins exactly match the received data, the 
Decode/Data Out (DDO) pin goes high until the next stream of 
serial data arrives at the SDI pin. If the data bits do not match, the 
DDO pin remains low. This is how the original application to 
garage-door openers was implemented, and it is the only function 
that the ED-9 can perform. As shown in Table 1 , the ED-9 has no 
serial data output. 



Courtesy Measurement and Controls Magazine 



3-24 



ED Series Applications 



Normal Serial 



ED Family — ( 
Manchester Code 



Valid Data Times 



Figure 1 . Manchester code converts a binary 1 into a low-high transition, and a binary into a high-low transition. 



Data Recovery 

All the other ED series devices (ED-1 5, ED-1 1 , ED-5, DC-7) can 
be used for data recovery. In these, the received data is carried 
through the device unaltered, and output on the Serial Data Out 
(SDO) pin. At the same time, the clock signal is output at the Data 
Clock (DC) pin. The leading edge of each clock pulse is situated 
during the time that the data on the SDO pin is correct (valid). The 
data clock signal can thus be used to load the correct received 
data into an external shift register for other uses. 

This function does not depend on the data-making function, and 
can be used regardless of whether the data on the data pins 
matches the received data. When a data word is received, 
matched or not, the Data Valid (DV) pin goes high to signal the 
reception of a complete data word. This signal can be used to 
signal an awaiting system that data is present in the shift register. 

Two of these devices (ED-11, DC-7) can use both functions 
simultaneously to achieve more capability. Both have 15 data 
input pins, one for each data bit in the Transmission mode. In the 
Receive mode, however, not all 1 5 data input pins are matched to 
the incoming data. In the ED-1 1 , only the 1 1 most-significant data 
bits are matched; the 4 least-significant bits are ignored. The DC- 
7 matches only the 7 most-significant bits of the data; the 8 least- 
significant bits (1 byte) are ignored. This allows these devices to 
be used to transmit data (4 bits or 8 bits) to a receiver that is 
selected by the matching codes (1 1 bits or 7 bits). The use of this 
capability will be explained. 

Communication media can be via (1) RF transmission (as in 
garage-door openers), (2) a long direct wire hookup, with digital 
line drivers, (3) infrared optical link or (4) fiber optic line. Use of the 
devices is independent of the communication medium used; 
presentation of a digital serial signal to the receiver input is all that 
is required. In the following application examples, although one 
particular communication medium is described, others could be 
substituted wherever desired. 

Microprocessor Interfacing 

ED devices are easily interfaced to microprocessor systems for 
either transmission or reception. If you are working directly with 
the microprocessor device and using assembly language, the 
task is made simpler because the microprocessor is fast com- 



pared to the ED devices. For data transmission, direct hookup to 
a Peripheral Interface Adapter (PIA), of the correct number of 
parallel bits to correspond to the data input pins on the ED device 
is the simplest interface. An alternative would be using one output 
from a PIA into a serial shift-register corresponding to the ED data 
input pins. A simple start pulse generated by the microprocessor 
after the data bits are set will then send the data out. Figure 2 
illustrates these methods. 

For the Receive mode, several types of interface are possible, 
depending on the receive function required. For address-match 
recognition only, the Data Input pins would be set by manual dip 
switches, and the Decode pin DDO would be connected to the 
microprocessor, either on a PIA pin or an Interrupt input. This 
would tell the microprocessor that a transmitter had called its 
"name." 

For reception of data through an ED device to a microprocessor 
directly, the ED device would be connected to a serial shift register 
through the SDO and DC function, to latch the data into parallel 
format. This shift register would be connected to an input PIA. 
Either the Data Valid (DV) or Decode (DDO) signal would be used 
to signal the microprocessor (via an Interrupt input) that data was 
available to the PIA. The DDO signal would be used only with the 
ED-1 1 or DC-7, which combine the matching function with data 
transmission. 

An alternate method of interfacing the ED series device to a fast 
microprocessor is to connect the serial data output directly to a 
PIA pin, and use the Data Clock (DC) output as an interrupt to tell 
the microprocessor that the nest data bit is available. Fast 
response is necessary in this case. 

A third method of interface for data reception is to use a tri-state 
output shift register, attached directly to the data bus of the 
microprocessor. An interrupt input from the DDO or DV will let the 
microprocessor read the data from the shift register in a similar 
manner as data is read from memory. 

These are some of the more common interface possibilities 
available. Interface to a bundled system where an external 
parallel port is used may limit input flexibility due to the software 
overhead involved in using higher-level languages, but effective 
interface is still easily accomplished. 



3-25 



ED Series Applications 



M P 



Address 
Bus 



Data 
Bus 



I/O 
Output 



I/O 
Port 



SDI 



DO-14 
ED-15 



Address 
Bus , 



Data 
Bus 



I/O 
Output 

IA I/O 
Output 
I/O 
Output 



IN 

PAR 

Out 

CLK 

Shift Reg. 



ED-1 5 



DO DDO 
D14 



Figure 2. Peripheral Interface Adapter (PIA) interfaces microprocessor and ED-15 for data transmission. 



Basic Systems 

The simplest use of the ED device is where one transmitter is used 
with one receiver. For address matching (such as a garage-door 
opener), the devices are used as shown in Figure 3. The start 
pulse is generated by a simple push-button. Switch bounce is not 
a problem because these devices "restart" the transmission each 
time the SDI pin pulses. Therefore, the last "bounce" will send a 
complete data packet, which will be received correctly. When the 
transmission is completed, the Data Valid (DV) pin goes high to 



signal a successful reception of a correctly formatted signal. If the 
input data stream also matches the receive device Data Input 
pins, the Decode Output (DDO) pin also goes high at this time. 

A similar simple application for data transmission would use an 
ED device with serial Data Output and Data Clock to allow data 
collection at the receiver. In Figure 4, one DC-7 and one ED-15 
are used, with the data byte latched into a 4094 sertal-to-parallel 
shift register. 







Transmit 






17 
18 

, ED-9 

2 


GND _L 


0! 




OB 

OC 






Start Signal 


SDI 





VDO 



O/OO 



3j ■ Ol 
CT 



rjr. loR 



SDI 



17 




18 




1 


ED-9 


2 




4 f 


14 



>VD0 



. GND 



0/00 



Address Address 

Figure 3. Address matching use. 



Transmit 



GND 



r 



Start Signal 



Fixed 
Bit 

I h 



1 


(OR 


T 


OC 


SDI 



1 26 

2 27 

3 ED-15 7 

4 22 



o VUU 

^rJ gndX 



I 



SDI 



DC-7 

25 



6 23 
8 14 



T 



Key Code 



0/00 



To Interrupt Logic 



Clock 



5 
6 
7 

4094 14 

13 
12 



TT 



GND 



-07 
-06 
-05 
-04 
-03 
-02 
-01 

-oo 



Output 
Enable 
orVDC 



mxixixixixixixixixixixixixix) 

AO A6 DO D7 

Figure 4. Addressed data transmission. Data is loaded into a shift register and latched if the transmitted address matches the receive address. 



ED Series Applications 



Multipoint Control Network 

ED-1 1 or DC-7 devices can be used to implement a simple, low 
cost multipoint control network using a serial loop daisy-chained 
to each controlled system. Figure 5A illustrates this Interconnect 
scheme. One transmission device is connected to a common 
serial data bus with multiple receivers, one per controlled system. 
The number of receive devices possible is determined by the 
number of address bits implemented in the transmit and receive 
devices. The DC-7 can address 128 receivers; the ED-11 can 
address 2048 receivers. 

The transmitting ED device in this type of network is normally 
connected to a microcomputer of some kind, while the receivers 
may interface directly to the controlled system. In operation, the 
microprocessor will select the data word to initiate the desired 
function in that system. This information is then placed on the Data 



Input pins orthe transmission ED device, and a Start pulse applied 
to the SDI pin. The serial transmission will be received by all ED 
devices in the network; however, only the device with a similar 
address pin code will match and raise the DDO pin high. The SDO 
pins of the receiver EDs are each connected to serial-parallel shift 
registers to capture the data word portion of the transmission. The 
system with the address match will read the command word form 
the shift register and execute the command. 

The serial wire loop is only one implementation of this type of 
control network. A multipoint "star" type of network (Figure 5B), 
ideal for a factory floor where visibility is good, could be imple- 
mented easily using an infrared transmitter at the control station. 
Each receiver station would use a infrared detector to receive the 
signal; no wiring is necessary. Additional receive stations are 
easily added to the network. 





Controller 
C 




E-D 
Receiver # 1 
SDI 




E-D 
Receiver # 2 
SDI 




E-D 

Receiver # 3 
SDI 




























DDO 
























Twisted Pair Cable 



E-D 
Receiver # 1 



E-D 

Receiver # 2 



l-R 
Recvr 



l-R 

Recvr 



E-D 

Receiver # 3 



l-R 
Recvr 



E-D 
Reciever # 4 



l-R 

Recvr 



Infra-red 
Trans 



E-D Controller 



Infra-red 
Optical Link 



Figure 5. Multipoint one-way control network. 



3-27 



ED Series Applications 



A Bidirectional Network 

An enhancement to the network described in the previous section 
is to implement two-way communication. Many applications re- 
quire this flexibility, where a controller needs to monitor the status 
of a remote system, or have a remote instrument make a mea- 
surement and report the results to the central controller. This type 
of network, where the controller sends out a request and receives 
a response, is called a "polled" system; it is the simplest way to 
implement two-way communication. No interrupt conflicts are 
involved, and the controller selects the priority in which the 
controlled systems are queried. 

The capability of ED devices to be switched between transmitter 
and receiver allows low-cost implementation of two-way commu- 
nication with a minimum number of parts. Using a microprocessor 
with the ED data input pins attached to a Peripheral Interface 
Adapter (PIA) port is the simplest method, although discrete logic 
is usable for less complex requirements. Figure 6 shows one 
possible configuration. 

The interaction between a controller and a remote system is 
straightforward. The controller will transmit an address and data 
word, as in the one-way network explained previously. It will then 
switch the ED device to Receive mode, connecting the SDI pin to 
the network transmission medium and monitoring the Data Valid 



(DV) pin for a signal that a transmission has been received. The 
SDO and DC pins of the controller are connected to a shift register 
to receive the information from the remote system. 

The remote system, with its ED device in the Receive mode, 
receives the transmission from the controller and matches the 
address to the status of its Data Input pins. At the same time, the 
data word is latched into a shift register through the SDO and DC 
pins. If an address match is found, the remote system then takes 
the data word from the shift register and executes the command. 
If data or status is to be sent back to the controller, the remote 
system will then apply the data to be sent back to the controller on 
the Data Input pins associated with the data bits of the transmitted 
packet. The Decode Data Out (DDO) pin is connected to the 
transmission media, and Start pulse is applied to the SDI pin. The 
remote ED device then will transmit the address and data to the 
controller. The remote system transmits its own address back to 
the controller with the data to prevent other remote systems from 
receiving and decoding the transmission in error. 

In this type of network interaction, some timing constraints must 
be met. The controller, when sending out a request and awaiting 
an answer, must have a time-out feature to prevent lockup of the 
system if the receiver does not receive the request. After the 
controller sends its message, it should wait an appropriate time 
and then re-send the message. 




Figure 6. Bidirectional communication. 



VN/VP13 Series 
Application Note 

AN-D8 



High Voltage Pulser Circuits 



Introduction 

The high voltage pulser circuit shown in Figure 1 utilizes Supertex 
complementary N- and P-channel DMOS transistors to achieve 
excellent performance and efficiency with minimal components. 
The output voltage swings are -100V to +100V. Rise and fall 
times are less than 1 nsec while sourcing and sinking over 0.75 
and 1 .0 amps respectively. The output is conveniently controlled 
by TTL or CMOS input signals. 

High voltage, high speed, and high current pulses at low duty 
cycles are required in several applications. Ultrasound cleaning 
equipment, flaw detection, medical imaging, and test instruments 
are but a few examples. Complementary N- and P-channel DMOS 
transistors, VN1304N3, VP1304N3, TN0102N3, TP0102N3, 
TP0620N3, and TN0620N3 are used for their low threshold volt- 
ages, low input capacitances and high output current capabili- 
ties. These are essential features to generate high voltage pulses 
with high speeds and currents. Another aspect considered was 
their cost-effective TO-92 package, which saves board space. 



v DD = iov 



Vp P = +100V 



VP1304N3 l— I- 



1K | 

TP0102N3 < R $ 
O.OIuF 



G P 



TP0620N3 



Inputs 



VN1304N3 



V DD =10V 



jH| TN0102N3 




VOUT 



H*j TN0102N3 $ R 
h ~f 1K 



15V 



TN0620N3 



V NN = -100V 

Figure 1. High Voltage Pulser 



Circuit Description/Design Considerations 

The high voltage pulser in Figure 1 consists of 3 basic stages: 
(A) input signal interface, (B) high current buffer and level trans- 
lation, and (C) high voltage and current output drivers. Each stage 
has its own specific requirements for device parameters, which 
will be discussed in the following section. 

Stage 1 : 

Stage 1 , consisting of VN1304N3 and VP1304N3, is an 
input stage to interface directly with TTL or CMOS logic 
signals. Low input capacitance and fast switching speed 
are the most important considerations in this stage. The 
VN1304N3 and VP1304N3 are chosen for their low in- 
put capacitance, 35pF maximum, and their 2nS typical/ 
5nS maximum td(on), tr, td(off) and tf switching speed. 
This will minimize loading and distortion on the input 
drive signals. Often the input signals are from fairly re- 
sistive sources, which may be in the order of 100's of 
ohms, creating large RC constants. Low C lss and C RSS 
will allow the gate voltage to charge past the transistors' 
threshold voltage rapidly, to accomplish high speed 
switching. 

The low threshold ratings will accommodate TTL and 
CMOS compatibility. Max threshold ratings, V GS(th) , for 
VN1304N3 and VP1304N3 are 2.4V and -3.5V 
respectively. For the 'worst case' design consideration, 
VN1304N3 will turn on when the input signal voltage 
reaches 2.4V. For a given input signal voltage rise and 
fall time of 50 nsec for to 1 0V, the time required for the 
input to reach 2.4V is 12 nsec. For VP1304N3, time re- 
quired to turn on is about 35 nsec. Once the devices are 
turned on, the output voltage rising and falling edges 
will have a waveform similar to that of an RC circuit where 
R is the on-resistance of the transistor and C is the total 
equivalent capacitance the transistor is driving. 

In addition to performing the interface to TTL and CMOS 
signals and improving rise and fall times, Stage 1 is also 
a high current low impedance buffer. Output currents of 
more than 250mA source and 500mA sink (based on 
l D(ON) specifications of these devices) are available to 
adequately drive the inputs of the 2nd stage. 



3-29 



VN/VP13 Series Applications 



Stage 2: 



Stage 2 provides high output peak currents, improves rise 
and fall times, and performs high voltage level translation. 
This stage consists of device types TN01 02N3 & TP01 02N3. 
The Supertex low threshold DMOS transistors TN01 02N3 
and TP0102N3 provide typical output peak currents of 2.8 
amps sink and 1.7A source. Such high currents are re- 
quired to adequately drive the input capacitances, including 
Miller effect of the output transistors, to accomplish fast 
switching speeds. The low threshold guaranteed maximum 
limits of 1.6V and -2.4V for TN0102N3 and TP0102N3 
respectively will further improve rise and fall time transi- 
tions. Resistor R and Capacitor C provide the DC level 
shifting. Value of C should be much larger than C, N of the 
output stage where C, N is equal to C, ss plus Miller effect: C, N 
= C| SS + C RSS (G FS . R L ). Resistor value R is selected such 
that time constant RC is much greater than the output high 
voltage pulse width required. 

With the source at +1 00V, gate voltage driving the P-chan- 
nel of the output stage are +100V and +90V to provide 
gate-to-source drives of OV and -10V. Similarly for the N- 
channel, with the source at -1 00V, gate voltages are -1 00V 
and -90V to provide 0V and +10V gate-to-source drives. 



Stage 3: 



Stage 3 is the output stage and consists of Supertex low 
threshold DMOS discrete transistors TP0620N3 and 
TN0620N3. These devices have a breakdown voltage rat- 
ing of 200V minimum. Output voltage swings can switch 
from -100V to +100V. Input capacitance is increased due 
to Miller effect, C IN = C, ss + C RSS (G FS . R L ). Low C RSS & 
C| SS capacitance, high output current, low on-resistance 
and 200V breakdown voltage are required parameters for 
the output transistors. The Supertex TP0620N3 and 
TN0620N3 are ideally suited. Their guaranteed param- 
eters are listed in Table 1 : 



During power up and power down conditions, it is possible for tran- 
sient voltages greater than 20V to appear across the gate-to-source 
on the output transistors. Maximum gate-to-source voltage, V GS , is 
rated at ±20V. 15V zener diodes are connected across the gate 
and source of the output transistors to protect against such tran- 
sient voltages. These diodes will not be zenering during normal 
operation. 

The zener protection diodes can be omitted if V PP and V NN can be 
ramped slowly to their rail voltages during power up. 

Input signals and corresponding voltages are shown in Figure 2. 
Actual output waveforms with a 1 00Q load for a 60 nsec and a 1 00 
nsec positive and negative pulse are shown on Figures 3A to 3D. 
V PP and V NN voltages can be varied without additional changes 
within the circuitry. For example, V NN can be -10V and V PP +190V 
for -10V to +190V pulses. Higher voltages and currents can be 
accomplished with minimal changes. 



Gp 



10V ■ 

ov 

10V 

ov 

100V ■ 
90V 
-90V 



u 



U 



Gn 



n 



100V 

Vqut ov 



-100V 



Us 



Figure 2. Input / Output Signals 



Table 1 





BV DSS (V) 


RdS(ON)(^) 


'□(ON) W 


Ciss 


(PF) 


Crss 


(PF) 


DEVICE 


min 


typ 


max 


min 


typ 


max 


typ 


max 


TN0620N3 


200 


4.0 


6.0 


1.0 


110 


150 


10 


35 


TP0620N3 


-200 


9.0 


12.0 


-0.75 


110 


150 


10 


35 



3-30 



12/9/91 



VN/VP13 Series Applications 




Figure 3A. 60 nsec Output Pulse 




Figure 3C. Positive Going Pulse 



Optional Variations 

The high voltage pulser in Figure 1 can be easily modified to suit 
various high voltage pulser needs. Figures 4A to 4D show some 
examples. 

Figure 4A is a positive high voltage pulser with one end pulling to 
ground. Basically, components R and C are not needed to drive 
the N-Channel. 

Figures 4B and 4C are high and low side open drain pulsers. Su- 
pertex VP0650N3 and VN0650N3 are used to satisfy applications 
with 500V pulse requirements. 

Figure 4D utilizes Supertex VN0550N3 and VP0550N3 for high 
voltage +250V push-pull 100mA requirements. Max input capaci- 



1 


■ 
m 
m 


■ 
■ 

m 
■ 


MMM 

191 

■■■ 

■■■ 

inn 


■■■ 
■■■ 

IHHI 


- 






u 


mm 


1 










■■■ 












■■■ 



Figure 3B. 100 nsec Output Pulse 




Figure 3D. Negative Going Pulse 



tances of VN0550N3 and VP0550N3 are only 55pF and 60pF 
respectively. These can be driven directly from Stage 1 with mini- 
mal loss in switching speed. 

Conclusion 

Supertex DMOS transistors are ideal for high speed, high voltage, 
high current pulsing applications. Bipolar transistors require base 
currents and time to recover from the saturation region. MOSFETs 
do not require any DC gate current thus enabling them to be easily 
driven with a simple AC coupling scheme. Because of Miller effect 
on the high voltage outputs, large peak currents are essential for 
the second stage to drive the outputs hard for fast switching speeds. 
The Supertex line of DMOS transistors has low input capacitance 
ratings making them ideal candidates for high speed, high voltage 
pulsing applications. 



12/9/91 



VN/VP13 Series Applications 



I 



V DD =10V 



V PP = +100V 



H 



1K ( 

TP0102N3 ( Ri 
0.01MF 



Inputs 



Ki VN1304N3 

1 

V DD = 10V 



^ TP0620N3 
H 



K] TN0102N3 

i 



5 — jH 

VP1304N3 



H 



K] VN1304N3 

1 



VoUT 



HKi TN0102N3 



'1 



TP0620N3 



Figure 4A. Push-Pull Positive High Voltage Pulser 



Vpp = 10V 



3 — 3 

I— r* 1 VP1304N3 r— h*J 



Input 



H 



K VN1304N3 



0.01 uF 
—II 



1 



H 



K*l TN0102N3 5r 
,_i 1K> 



I 



| VquT 



VN0650N3 



V NN = -500V 



Input 



J 



V DD = 10V 



Vpp = +500V 



H 



K VN1304N3 

1 



1K 

TP0102N3 ^ R 

0.01 uF 
II 



H 



H*i TN0102N3 
1 



VP0650N3 



L VQUT 



Figure 4B. High Side Open Drain High Voltage Pulser 



Vpp = 10V 



Vpp = 250V 



1K ! JK 

R> S 1 



o.oiuF 



Inputs 



Vpp = 10V 



VP0550N3 



0.01 uF 



K| VN1304N3 

1 



VOUT 



Ki VN0550N3 



R < S 



V NN = -250V 



Figure 4C. Low Side Open Drain High Voltage Pulser 



Figure 4D. Push-Pull ±250V High Voltage Pulser 



3-32 



TN06 Series 
Application Note 

AN-D9 



Battery Back-Up Utilizes 
Low Threshold MOSFETs 



Introduction 

The simple battery back-up circuit shown in Figure 1 utilizes 
Supertex low threshold DWIOS devices to achieve excellent 
efficiency. 

In fact, one of the main reasons why MOSFETs are gaining 
popularity is that very low voltage drops, which surpass the 
performance of various kinds of diodes and bipolar transistors, can 
be achieved. Many other benefits of low gate threshold MOSFETs 
are explained in the text. 

Circuit Description and Operation 

The battery back-up circuit has two modes: 1) Battery charging, 
and 2) Battery back-up. 

1) Battery charging mode 

The 120VAC is stepped down via transformer and full-wave 
rectified by D1, D2, and C1 to 7.5VDC. This 7.5VDC supplies 
power to RL as well as providing the charging current to the 
batteries. R1 , D3, and D4 generate a 1 .2V reference for COMP 1 
and 2. D5, R2, R3, C2, and COMP 2 keep Q1 and Q2 off when 
switch S is closed. The battery, consisting of 5 nickel cadmium 



cells in series, is being charged with a current set by R8 and the 
intrinsic drain to source diode of Q2. For fully discharged batteries, 
there will be a high charge current for a few seconds, rapidly 
decaying to a slow charge. 

As the battery becomes almost fully charged to 6.8V, the current 
is reduced to a trickle charge current of a few milliamperes. The 
trickle charge current is further reduced to microamperes when 
V BATT exceeds 7.0 volts. This is because the voltage across the 
diode of Q2 is 0.5 volts and will allow only a small amount of current 
flow. This maintains full charge of the battery, when not in use, over 
an extended period of operation. 

2) Battery back-up mode 

When switch S is opened, simulating power outage, unplugged 
equipment, or blown fuse, the circuit goes into battery back-up 
mode. COMP 2 turns Q1 and Q2 on. As V BATT supplies the 60 ohm 
load, COMP 1 monitors the V BATT voltage keeping it from fully 
discharging, as complete discharge and subsequent cell voltage 
reversal can degrade the performance of the NiCd battery. The 
circuit is designed for the COMP 1 to turn Q1 and Q2 off if V BATT 
is less than 5.5V and on if greater than 6.5V. The hysteresis is 
designed to avoid oscillation and is set by R4, R5, R6, and R7. 



0.1 nF 




Figure 1. Battery Back-up Circuit 



3-33 



Design Considerations 
and Component Selection 

The design of this circuit utilizes standard, readily available com- 
ponents. The number and different types of components are 
minimized. Diodes D1 to D5 are 1 N4001 . All resistors are standard 
1/4 watt, 5% tolerance. National Semiconductor's Dual Compara- 
tor LM393N is used for its low biasing current. The battery consists 
of 5 Eveready nickel cadmium cells in series. The cells are AA size, 
CH15 with a C rating of 500 mAH. 

The most important factor to be considered in the design is the 
selection of the MOSFETs Q1 and Q2, which are configured as an 
analog switch. In the battery back-up mode, the voltage drop 
across the MOSFETs must be low to minimize resistive voltage 
drop and power loss, consequently enhancing battery life. 

SupertexTN0602N3, low threshold N-channel DMOS transistors, 
are selected for their guaranteed low on resistance at low gate 
drive. Another aspect considered was their cost-effective TO-92 
package, which saves board space. 



Device 
Type 


R DS(ON) 

Typical 


RdS(ON) 

Maximum 


Test 

Conditions 


TN0602N3 


0.9 ohms 
0.6 ohms 


1.5 ohms 
0.75 ohms 


V GS =5V, l D = 750mA 
V GS =10V, l D = 1.5A 



Q1 and Q2 are easily turned on with a simple pull-up resistor, R7. 
For a "worst case" design, R DS (on) = 1 5 ohms and a load current 
of 125 mA are used. Maximum voltage drop across Q1 and Q2 
works out to only 375 mV. In actual operation, this voltage drop is 
substantially lower because the typical value of R ds(0 n) is 8 
ohms. The voltage drop across Q1 and Q2 was measured to be 
200 mV. 

Figure 2 is a discharge curve of V BATT vs Time showing battery 
back-up operation of approximately 4 hours. Figure 3 is a charge 
curve of the battery. 



Vbatt vs Time 



& 

O 5.5 
> 

fc 

5.0 



60 



180 



120 

t (minutes) 
Figure 2. V BATT Discharge Curve 



240 



TN06 Series Applications 
VbaTT vs Time 



7.5 



o 6.5 



.£? 6.0 



5.0 



4.0 8.0 12.0 16.0 

t (hours) 

Figure 3. V BATT Charge Curve 

The component selection ensured that basic charging current 
guidelines for Nicad cells were not violated. Assuming the worst 
case, using fully discharged batteries, the maximum charging 
current will be 227mA. 

Rectified D.C. voltage - diode drop 7.5 - 0.7 



R8 



= 227mA 



30 



This current will last only for a few seconds, and is completely safe 
for the battery as well as Q2. 

In the charging mode, the battery voltage will be between 6.5V to 
6.7V for the majority of the time. The charging current will be from 
7.5-6.5-0.7 „ 7.5-6.7-0.7 



30 



: 1 0mA to 



The charge rate will be from 
3.3mA 



10mA 



30 

,= 0.02Cto 



3.3mA 



500mAH 



500mAH 

= 0.007C which is very safe for the Nicad cells. 



Optional Features 

When space is at a premium, Supertex's TN2504N8 provides 
performance almost identical to TN0602N3, in the SOT-89 
(TO-243AA) surface mount package. 

Added features such as battery back-up mode indicator, low 
battery voltage early warning, or battery shutdown indicator can be 
incorporated by using one or more of the optional circuits shown 
in Figure 4A through 4C. These can be easily modified to interface 
with a microprocessor in more complex systems. 

Nickel cadmium batteries are quite rugged. However, they are 
prone to damage due to cell voltage reversal if fully discharged. 
Other kinds of batteries are more sensitive, and may be damaged 
below a certain voltage per cell, e.g., 1 .75V for lead acid. 

The circuits shown can be modified to suit other kinds of recharge- 
able batteries, e.g. lead acid, lead calcium (gel), lithium, etc. For 
lead acid, the threshold voltage, to disconnect the load from the 
battery can be adjusted to 1 .75 volt per cell. 



3-34 



TN06 Series Applications 



Vbatt 



PIN 6 o 
PIN 5 o 




Vbatt 



Vbatt 




pin 3 o- 
Vref o- 



30on 



A) Battery Back-up Mode Indicator 



B) Low Battery Voltage Early Warning 
Figure 4. Optional Circuitry 



C) Battery Shutdown Indicator 



Conclusion 

Very low drain to source voltage drops can be achieved with 
MOSFETs. Bipolar transistor performance is limited by VCE (sat) 
and diodes by VF, depending upon the semiconductor material 
used. This circuit utilized the following features of MOSFETs: 

1) Low drain to source voltage drop. 

2) Complete turn-on/off of bidirectional currents. 

3) Turn-on with low biasing voltages. 

4) No biasing power compared to base current loss in 
bipolar transistors. 

5) Utilization of the intrinsic drain to source diode for limiting 
charging currents to efficient and safe levels. 



The battery back-up circuit described demonstrates the benefits of 
Supertex N-channel low gate threshold devices. These are avail- 
able in either surface mount (TN2504N8) or TO-92 (TN0602N3) 
packages. These are ideally suited for battery powered applica- 
tions. Very often, circuit designs require low on resistance to 
prolong battery life, low gate drive to meet battery voltage limita- 
tions, and small packages to accommodate board space limita- 
tions. The Supertex low threshold DMOS discrete transistor family 
were designed to satisfy such requirements. 



3-35 



LND1 Series 
Application Note 

AN-D10 



Off-Line Compact Universal Linear Regulator 



Introduction 

An off-line compact universal linear regulator is shown in Figure 1 . 
The regulating device is the Supertex LND1 50N3. The LND1 is a 
500V N-channel depletion mode MOSFET with gate-to-source 
ESD protection. The regulated voltage, V 0UT , is an ideal supply for 
CMOS ICs and a variety of other circuits that require low current. 

Circuit Description 

The 120V AC input voltage is rectified by a full bridge, consisting 
of diodes D, , D 2 , D 3 , and D 4 A small filter or smoothing capacitor, 
C, , is used to hold the rectified voltage to approximately +1 70VDC. 

The unregulated 1 70VDC is connected to the drain of the LND1 . 
The LND1 and trimpot R, are configured as a 1 .0mA constant 
current source. The 1.0mA constant current flows through R 2 
which is a 5. 1 Kohm resistor to ground. A constant voltage drop of 
5.1 V is developed across R 2 . V OUT is taken as the voltage across 
R 2 and is used to supply, for example, a simple CMOS timer circuit. 

Capacitor C 2 is a low voltage bypass capacitor to supply any peak 
current required by the CMOS timer circuit during switching 
transitions. D 5 is a 5.6V zener diode used to clamp transient 
voltages that may occur during powering upthe 1 20V AC input line. 
D 5 does not conduct during normal operation. 



Calculations for Component Values 

C, is a 0.1 jiF 200V capacitor, chosen to minimize ripple on the 
170VDC which would affect the regulated output voltage. The 
minimum value of C, is calculated as follows: 



Vin = A Sin2irft; A = 170V, f = 60Hz 
dv 



UClf ;l=j.0mA 
dv = AV = A - V UT " [lD(ON) • RDS(ON)]; dt = At = ^ 

I 2(60Hz) ) 

/ 



Ci > I At = (1 .0mA) I 2(60Hz) 

AV Vl70V-5.1V-(10mA)(1K£2) 



Ci > 0.054uF 

The LND1 can maintain a virtually constant current over a wide 
input voltage range. Large ripple voltages on the drain of the LND1 
will have very little effect on the output current. The device can also 
withstand transient voltages up to 500V. 



Vin 




al " F |r J *1.0mA 

LND150N3 



Di, D 2 , D 3 , D 4 , D 6i D 7 : IN4005 



Rl ■ 
10K 



5.6V A 1 R2 | 
-I 05 1 



C 2 J_ 
5.1 K X 10 ^ F 



1500pF 

Br" 

1500pF 
-tVdD 



X 

3M 



CK 



Reset 



MCI4030 
14-BIT 
Counter 

100K _L 



$D6 



VN0650N3 



Potter & 
Brumfield 
\ KUMP 

11A-1 8-240 



Load 



CMOS Timer 



Figure 1. Linear Regulator 

3-36 



AND1 Series Applications 



The value of the constant current source is a function of R, , V p , and 
l DSS where V P and l DSS are characteristics of the device. R, is a 
variable resistor adjusted for 1 .0 mA and is approximated by: 

where, l D = desired constant current value, 

V P = pinch-off voltage, and 

'dss - saturation current at V GS = V. 

V P and l DSS may vary from lot to lot. The range of adjustment for R, 
is calculated for operation over the range of LND1 values for V P 
and l DSS . 



Symbol 


Parameter 


Min 


Max 




Pinch-off Voltage 


-1.0V 


-5.0V 


tass 


Saturation Current 


-1.0mA 


-10.0mA 



For the above values, R, is calculated to be from to 6.6Kohm. A 
1 0Kohm trimpot is chosen for R, . 

Since the constant current is adjusted to 1 .0mA, R 2 is chosen to be 
5.1 K to obtain a Vout of 5.1 VDC. The value of C 2 is selected to 
supply the peak current required by the load on V 0UT over a period 
of time. C 2 can be calculated as follows: 

c 2 = louT( dt/dv ouT) where, 

'out - output current 

dt = required time duration of l OUT 

dV OUT = acceptable change in V OUT 

For example, a 10.0mA output peak current for a duration of 
1.0|isec with a maximum V OUT drop of 100mV will require a C 2 
value of 1 .0mA(1 .0usec/1 OOmV) = 0.1 u.F or greater. C 2 is chosen 
to be 1 .OuF. 



Figure 2 is an oscilloscope picture showing the actual voltage 
waveforms on the drain of the LND1 and V 0UT . 

Figure 3 is an output characteristic showing the regulation of the 
circuit over a wide range of input voltage. 

Alternative Applications 

For a 10V source, R 2 can be replaced with a 10K resistor. 
Applications requiring multiple voltage references can be gener- 
ated by using a string of resistors as shown in Figure 4. 

The constant current can easily be changed by readjusting R, for 
the desired current. However, the power dissipation on the LND1 
should be taken into consideration. P D for the LND1 in the TO-92 
package should not exceed I s( v in" v out) = 600 mW. 

Universality 

The universality of the linear regulator can benefit a variety of 
industrial or consumer applications as it can be used from a very 
wide range of input voltages, anywhere in the world. Input voltages 
can be up to 450V for linear regulation. Protection is afforded for 
line voltage transients up to 500V since the LND1 breakdown 
voltage is guaranteed to be greater than 500V. A simple, low cost, 
transient protection (e.g., MOV) will protect thecircuitfrom virtually 
anything, other than a direct lightning strike. 

Regulation can also be achieved with AC or DC voltages from 6.8V 
to 240V with no modifications of the circuit. This allows manufac- 
ture of one model of equipment for worldwide usage without any 
voltage setting tappings. 

Conclusion 

The Supertex LND1 can be configured as a simple, constant 
current source to create an economical compact off-line, low 
current regulated, voltage supply for powering CMOS ICs and 
other low current loads. The need for transformers can be elimi- 
nated. 




Figure 2. Input/Output Waveforms 

3-37 



LND1 Series Applications 




3-38 



_ m LND1 Series 




err 


w=7k inCm Application Note 

AN-D11 



±500 Volt Protection Circuit 



Introduction 

A ±500V protection circuit for low voltage high impedance 
measuring instruments is shown in Figure 1 . The protection is 
accomplished by limiting the amount of current going into the 
measuring instrument. The circuit will protect against destruc- 
tive high voltages inadvertently connected to the probes (V MEAS ) 
of up to 500VDC of positive and negative polarity. 



Circuit Description 

The circuit consists of two transistors, Q, and Q 2 , and one 
resistor, R. Both Q, and Q 2 are Supertex LND150N8, 500V N- 
channel depletion mode MOSFETs with gate-to-source ESD 
protection in a SOT-89 surface mount package. Q1 and Q2 are 
configured back-to-back as two constant current sources with 
a nominal value of 1.0mA. Resistor R sets the current limiting 
value. Figure 2 is a typical low voltage high impedance mea- 
surement instrument. Figure 3 is a simplified equivalent circuit 
showing the protection scheme. 



LND150N8 LND150N8 
1K 

Probe o-i^-j-Pvw 
Vmeas 




Probe o- 



2 



Vl 



Measuring 
Instrument 



Figurel. ±500V Protection Circuit 




V = 2(V 2 -V 1 ) 



■i 1/4 LM324 



I Low Voltage High 
Measurement 



Vsup 



+ 

Vsup 




T 



Vsup 




Vsup 



1 .0mA 1 .0mA 



j D 2 

Vsup 
"J Da 



Probe 



Vmeas 



1 b 



-o Probe 



i 1 

Internal ESD Protection 



Figure 3. Equivalent Circuit 



3-39 



Under normal operation, the absolute value of V 

meas less 

than the supply voltage of the circuit. Q, and Q 2 will be fully on 
with a maximum guaranteed R DS of LOKohms. Since the 
instrument's input impedance is typically very high, say above 
10Mohms, the additional 2.0Kohm series resistance from Q, 
and Q 2 will not affect measurement accuracy. 

Under the fault condition, the absolute value of V MEAS is greater 
than the supply voltage, Q, limits the current to 1 .OmA against 
large positive voltages and Q2 limits the current to -1 .OmA 
against large negative voltages across V MEAS . 

For example, if V MEAS is connected to ±500V, Q, and Q 2 will limit 
the input current to ±1 ,0mA causing the input voltage to the 
measurement instrument to clamp to 1.3V above its supply 
voltage (when R = 600£J) and 0.7V below ground. 

Typically the measuring instrument has ESD protection diodes 
connected from both probes to its power supply and ground. 
The ESD protection diodes can usually handle 1 .OmA continu- 
ously. In case there are no ESD diodes provided, external 
diodes D,, D 2 , D 3 , and D 4 can be added. 

Calculation for Resistor Value 

For a current limiting value of ±1 .OmA, R can be approximated 
by the following equation: 

where, l D = desired constant current value, 
V P = pinch-off voltage, and 
loss = saturation current at V GS = OV. 

V p and l DSS are device characteristics and will vary from lot to 
lot. Actual constant current values are not critical as long as the 
power dissipation of the LND1 is less than 600mW. 

p diss = 600mW = (constant current value)(max. input voltage) 

Figures 4A and 4B are pictures of current due to V MEAS vs. V MEAS 
voltage of the actual circuit. R was chosen to be 1 .OKohm. 



LND1 Series Applications 

Conclusion 

The high voltage protection circuit is ideal for both bench 
measurement and handheld measurement instruments. It is 
simple, reliable and cost effective. It eliminates the possibility of 
input damage to very sensitive and expensive high impedance 
devices within the measurement instrument. 




Figure 4B. 



3-40 



LND1 Series 
Application Note 

AN-D12 



High Voltage Ramp Generator 



Introduction 

A low cost 500V high voltage ramp generator is shown in Fig- 
ure 1 . High voltage ramps are ideal for applications requiring a 
linear relationship between output voltage and time, e.g., high 
voltage sweeping, automatic test equipment and piezo electric 
drivers. 



500V 



LND150N3 



13K 



1nF 



| Vqut 



C 3.3K > R 2 



VN0550N3 



-o V|N 



Figure 1. 

Circuit Description 

The high voltage ramp generator shown in Figure 1 utilizes 
two Supertex high voltage DMOS transistors, the LND150N3 
and the VN0550N3, two resistors, R., and Ft 2 , and a capacitor 
C. R, is a trimpot resistor. The LND150N3 is a 500V ESD pro- 
tected N-channel depletion-mode MOSFET and the VN0550N3 
is a 500V N-channel enhancement-mode MOSFET. Both tran- 
sistors are available in the TO-92 package. 

The LND1 is configured as a constant current source charging 
a capacitor C. R, introduces negative feedback to regulate and 
set the desired constant current value. When the constant cur- 
rent source begins charging capacitor C, a voltage ramp is gen- 
erated across the capacitor. The voltage ramp, V oux , is the 
voltage across the capacitor. 

The VN05 can be turned on with TTL or CMOS control signal 
to reset the ramp voltage V 0UT by discharging the capacitor to 
ground through R 2 . The VN05 has a typical On-Resistance of 
45 ohms at 10V gate drive and 50 ohms at 5V gate drive. Re- 
sistor R 2 is calculated to limit the discharge current for the VN05 
to operate within its SOA rating. 



Calculations for Component Values 

The ramp is designed to be 0.1 V/|xsec. Capacitor value C 
should be kept small to reduce charging and discharging a large 
amount of energy. The selection of C should be large enough 
so that output loads and stray capacitances will not introduce 
significant error. C is chosen to be 1 .0 nF. 

The charging characteristic for a capacitor is I = C (dv/dt). 

I = 1 .0 nF x 0.1 V/usec = 100 uA. 

Calculating R, for a 100 uA constant current source: 




| D = | DSS (1 - Y^)2, v GS = -l D Rl 
= IDSS(1 + ^) 2 



Solving for Ri : 
• VP. 



V P = pinch-off voltage. Measured value = -1 .6V. 

I DSS = saturation current at V GS = 0V. Measured value = 3.0 mA. 

Calculating for R, using the typical values: 



Rl= S(V 100 ^ A /3.0mA -1)=13-1KQ 



R, should therefore be adjusted to approximately 13.1Kohms. 

During power up and down, it is possible to have high transient 
voltages to the gate of the LND1 . The LND1 internal ESD gate- 
to-source protection will protect the device against such tran- 
sients. 

The VN05 performs the reset function by discharging capacitor 
C through resistor R 2 . The VN05's low output capacitance, 
(C oss ) of 10pF max, minimizes additional parallel capacitance 
across capacitor C. 

It is desirable to discharge V 0UT rapidly and as close to ground 
as possible. This can be accomplished with a low value R 2 . 
However, care should be taken not exceed the SOA rating of the 
VN0550N3. 



3-41 



Maximum peak power for VN05 in a TO-92 package is 3.0W. 
Calculating for a minimum R2: 

Pdiss = Id ' V DS , V DS = 500V - (l D « R 2 ) 

I d( on) min = 150mA, P DISS = 3.0W 

R 2 = (1/I D )(500V-P DISS /I D ) 

= (1/150mA)(500V - 3.0W/150mA) 

= 3.2K 

R 2 is set to a standard resistor value of 3.3K. 

Figures 2 and 3 show two different input signals with their corre- 
sponding output voltage ramps. The ramp can be adjusted by varying 



LND1 Series Applications 

Conclusion 

The LND1 is ideally suited for high voltage, low constant current 
source applications. High voltage ramp generators, high voltage 
triangular waveform generators, high voltage references, biasing 




















m 


m 






























































- 








/ 


r • • ■ 










- 






/ 














D7. ■ • - 




/ 
























\ 













Figure 2. 



Figure 3. 



HV91 Series 
Application Note 

AN-H13 



Designing High-Performance Flyback Converters 
with the HV9110 and HV9120 



by Ray Ruble, Applications Engineer 



Introduction 

Although the HV91XX family of PWM ICs can be used to control 
single-switch converters of any topology or size, their primary 
usage is in low-cost, low to medium power, discontinuous-mode 
flyback converters. Designing such converters is relatively simple 
and quick if one has a basic understanding of how a flyback 
converter functions. It is the purpose of this note to provide such 
an understanding, and to illustrate, with a couple of examples, 
one way in which such a converter design can proceed. It should 
be noted that this is an engineering approach, meant to allow the 
user to develop a working design quickly, not a textbook ap- 
proach meant to teach underlying theory. Safety margins are 
taken into account, and the path taken through the design is 
intended to make these margins work with each other in order to 
generate an economical and producible power supply. Many 
apparently arbitrary values are used. They are arbitrary, and 
different ones could have been used that would have resulted in 
different power supplies, that would have been, for whatever 
feature was optimized, just as valid as the examples chosen. 

On Flyback Function 

A flyback converter functions, as does almost every other 
switchmode converter, by storing energy in an inductor during a 
main switch ON period, then discharging the stored energy into 
a load during the switch's OFF period. The trickiness to this (if 
there is any) is that the inductor has two or more windings, (an 
input winding and one or more output windings) and that the 
current flow alternates between the input and output windings, 
with effectively no current (other than a little leakage) flowing in 
the nonconducting winding while its partner carries the current. 

The way a flyback converter works can lead to some confusion 
if the designer tries to approach the design of its magnetic as if 
it were a transformer, because, except for the case of multiple 
output windings, the magnetic in a flyback converter is NOT a 
transformer. Perhaps the easiest way to view the magnetic in a 
flyback converter is as an energy buc/cerwhich is alternately filled 
(when the main switch is ON) and dumped (when the switch is 
OFF). A flyback magnetic is NOT a transformer despite its super- 
ficial resemblance to one: A transformer functions as a voltage- 
in, voltage-out power transfer device, where input and output 
windings conduct simultaneously. A flyback magnetic is an en- 
ergy-in, energy-out power transfer device where the input and 
output windings do not conduct current simultaneously. Obvi- 
ously, voltages present on the active winding are reflected, by the 
turns ratio, to the inactive winding, but the old saw 'The voltage 



on the main switch is twice the input voltage" is incorrect, be- 
cause the voltage reflected from the output winding can be either 
higher or lower than the input voltage (generally it is lower) 
depending on the voltage at the output, and the time allotted for 
the output inductance to discharge into it. Discontinuous-mode 
operation merely means that all the energy (neglecting losses) 
put into the coupled inductor during one time period when the 
main switch is ON is then emptied out during the following period 
when the main switch is OFF. No energy is carried forward to a 
subsequent cycle. (See Figure 1.) 

For both converter and magnetic design, a flyback magnetic can 
be thought of as two independent inductors which share a com- 
mon core. Once the designer is accustomed to thinking of the 
flyback magnetic as a dual inductor, the rest of the design be- 
comes easier. 

What the designer needs to do is define the output side inductor 
so that it delivers enough energy to the load, while the switch is 
off, to produce the desired current at the desired voltage. Next, 
define the input side of the inductor so that it takes in enough 
energy when the switch is on to provide for both the output and 
system losses. To facilitate this, a conversion formula is neces- 
sary: 

be = U 'y m, N 



period 

This formula converts DC to peaks of noncontiguous triangle 
waves. 1 

If we deal with ON time as a percent of total clock period, (duty 
cycle) and define 

D= *9B_ ;1 . D = 

'period period 

the formula reduces to: 
D 



Inc = I, 



for the input side and 



In 



1-D 

'pk " V 3 ,or ,ne out P ut side 
Because the designer knows the length of time the switch will be 
ON and OFF (these are defined by the clock frequency and the 
PWM IC used) as well as the input and output voltages desired, 
the peak currents found from the formulae can be used with the 
defining formula for inductance 

E = L • (dl/dt) 

to determine the required inductances for the input and output 
sides of the coupled inductor. In the process, the rest of the 
design generally falls into place. 



3-43 



HV91 Applications 



Data Needed to Start the Design 

1 . Minimum and Maximum Input Voltage 

2. Nominal Output Voltage(s) and Tolerance(s) 

3. Maximum Output Wattage 

4. Minimum Output Wattage 

5. Maximum Allowable Output Ripple 

6. A defined clock frequency 

7. A list of mechanical and thermal i 

Operating Frequency 

Most designers approach converter design with the idea of oper- 
ating at the highest possible frequency that is convenient. This is 
generally a useful approach, because it minimizes the size and 
cost of output capacitors and the coupled inductor. However, it is 
not always the best way to choose a frequency. In the case of 
low-power converters, once the magnetics are reduced in size to 



a vendor-dependent minimum, further reductions in size will raise 
the cost of the magnetics. Very small cores and ultra-fine wire are 
hard to handle. 

There is another important consideration in the choice of fre- 
quency that is often overlooked: dynamic range. If the difference 
between the widest pulse a PWM IC can generate (which is a 
function of its operating frequency) and the narrowest pulse it can 
produce (a function of the PWM IC's speed and internal struc- 
ture) is small, the ratio between P out(max) at low line and P out ( mi „) 
at high line must also be small, or reducing the size of the 
inductor and output filters will be paid for by increasing the size 
and cost of the EMI filter. Further, if the PWM IC selected cannot 
handle the full range of pulse widths required, it will start cycle- 
skipping (failing to turn on at all for some cycles). 

While most PWM ICs, including the HV91XX family, can simply 
skip cycles by not turning on at all, if the differential between V in 
and P out becomes too great, skipping cycles reduces the effective 
clock frequency of the converter, and re-defines the minimum 
frequency for which the input EMI filter must be designed. For 
example, if the converter skips every other cycle at high line/light 



The "Energy Bucket 

Situation 1 




V, N varies, Load is fixed. 

r Slope of rise is dependent on 
[input Inductance (fixed) and _V|^(yarying) . 



The PWM IC holds (Llf N ) constant 
by shutting input switch OFF at the 
required current regardless of how 
long current took to rise to that level. 




T ON : Input side switch is ON, inductor charges up r Slope of fall is dependent on 

I output inductance (fixed) and V c 




T OFF : Energy stored 
on previous half-cycle 
discharges into load 



Situation 2: V, N is fixed, Load varies. 




The PWM IC varies (LI 2 ) by varying shutoff 
current to allow more energy for larger loads. 





Output slope is constant as long as output voltage is constant. 
Dead time exists in Output amplitude changes with output current, 
each cycle except ; ; j 

when Load = Max 
and V, 



Load = Min 




Clock starts each cycle. 



Figure 1 



Load = Max 



3-44 



HV91 Applications 



load, the size (and cost) of the EMI filter can be doubled. Cycle 
skipping also increases either the size of the output capacitors or 
the amount of ripple on the converter's output. 

Recently, dynamic range has been overlooked because most 
bipolar PWMs do not have a wide dynamic range. For example, 
a bipolar 1845 PWM operating at 50KHz has a dynamic range of 
only=17.6:1. ACMOS 9110, in contrast, has a dynamic range of 
> 120:1 at 50KHz. Proper use of dynamic range can have a 
significant effect on EMI filter cost. 

Another consideration in choosing an optimal frequency is switch- 
ing power loss, which increases linearly with frequency in non- 
resonant converters. 



Example 1 



A 48W converter patterned after an instrument power supply. 
This will be a simple generic example with no bells and whistles. 
First, we need the input parameters listed above: 

Maximum Input Voltage: 65VDC 

Minimum Input Voltage: 18VDC 

Outputs: A: 5.0V, ±1%, 0.25 to 8A, < 25mV ripple 

B: 12.0V, ±5%, 0.01 to 0.7A, < 0.5V ripple 

Maximum Output Wattage: 48.4W 

Minimum Output Wattage: 1 .37W 

Operating Frequency: 50KHz 

(See Figure 2.) 



An HV9110, which will accept input voltages of up to 120V is 
used. As previously noted, this chip will allow a dynamic range 
sufficient to handle the stated line/load variations at 50KHz. 
Setting the clock frequency requires selecting an appropriate 
timing resistor. From a graph on the data sheet, the appropriate 
resistor for 50KHz operation is =330Kn. This however does not 
account for the tolerance of either the resistor or the chip. To 
ensure that all device-resistor combinations operate at or above 
50KHz, 261 KQ is a better choice. The reason that the clock 
frequency should be set to a minimum rather than a nominal 
value, despite the reduction in dynamic range this causes, is to 
prevent the slowest converter from saturating its coupled induc- 
tor. While magnetic saturation does not cause damage in a 
current-mode converter as it would in a voltage-mode converter, 
it still causes additional dissipation and stress on the main switch. 
It can also limit power throughput. 



The Design 



First, translate the RMS current of the major output winding at 
maximum load to a peak current. From the data sheet for the 
HV9110 it can be seen that maximum ON time for a cycle is 50% 
minus approximately 150 nsec. At 50KHz, this amounts to a little 
over 49%. We can declare a maximum duty cycle (D) of .49 and 
allow a small safety margin. If D MAX is .49, then minimum 1-D is 
.51 . Using .50 as a value for 1 -D (thus allowing a 1 % overall dead 
band as safety margin) determine peak secondary current: 



.50 



19.59A 



L1 



+VIN 



+C8 : 



COM 



+C9 



:R2 

13 



: R1 



R3 



T1 



2 •) 



U1 



Ol— 
CO =3 
OO 



FDBK HV9110 

C0MP r „ ft en , 



OUT 



CJ o: S « w oi 

I > CD □ > O 



11 11 

1 2 

C5 = 



D2 

->4- 



D1 



C2 



R6 



C4 



Q1 



>R5 



C3 




R7 



Figure 2 



This value will also be used to determine the actual voltage 
required of the winding, which is the output voltage plus the drop 
in the output diode: 

^winding = V out p u , + Vpj djo( j e j 

Also, repeat this procedure for each auxiliary output winding as 
an aid in determining the real voltage required of these windings: 



pk(12V) 



: 0.7A 



.50 



= 1.715A 



Next calculate minimum t of) , which will be 50% of the maximum 
PWM oscillator frequency. Using a 261 K timing resistor, maxi- 
mum frequency should be < 67KHz, which gives a t period of >14.9 
usee, and a of 7.46 usee. 

Next, we need to generate an estimate of instantaneous forward 
drop of the diode on the main output. We cannot actually choose 
a diode until we know what its reverse voltage needs to be, which 
will not be known until input side inductance is calculated. 0.8V 
should be a reasonable estimate. This voltage is added to the 5V 
output voltage to determine the actual voltage on the main output 
winding (5.8V in this instance). 

Knowing the peak current and voltage of the output winding and 
the minimum t off , we can calculate the inductance of the output 
winding from the defining equation for inductance, E = L dl/dt. 



5.8V 



4, 



19.6A 



\7.46x 10 e 



: 2.21uH 



The same procedure is used to calculate primary inductance. 
First we need to calculate the total power into the magnetic. This 
is the power out of the magnetic, plus the losses in the magnetic 
itself. 

The power out of the magnetic is just the continuous output 
power of the converter, plus the losses in the output diodes. Use 
an average forward drop for the diodes for this step. 



out(5V) - 
3 0Ut(12V) 



. 5.6V • 8.0A = 44.8W 
= 12.7V • 0.7A = 8.89W 



P out(TOTAL) = ^-SW + 8.89W = 53.69W 

The losses in a well-designed magnetic assembly, for a fixed 
frequency and power output, interestingly enough, depend pri- 
marily on the physical size of the magnetic. Smaller magnetics 
will be less efficient and run hotter. Larger magnetics will have 
less loss and run cooler. The effect is logarithmic, and means that 
no one will ever build a magnetic less than » 90% efficient, 
because the insulation required would burn up under normal 
operating conditions, and that very few people could accept a 
magnetic that is over 99% efficient, because the size would be 
prohibitively large. For a switchmode converter of the type de- 
scribed 95% to 97% efficiency will result in a reasonable mag- 
netic size that is economical to build. Using an estimated mag- 
netic efficiency of 96%, calculate input power (which is just output 
power divided by magnetic efficiency): 

53.69W -t- .96 = 55.93W 

Next, determine the minimum voltage across the input winding. 
This is just the minimum input voltage to the converter, minus the 
drop across the switch and the current sensing resistor. 

The drop across the current sensing resistor is easy to determine 
from the data sheet for the 91 1 0. According to the data sheet, the 
minimum trip point for the current limiting section of the chip is 
1.0V. This means that our maximum normal operating peak 



HV91 Applications 

voltage across the resistor should be slightly below 1.0V. If we 
establish a maximum peak voltage that is much less than 1 V, we 
will increase the distance between maximum normal operating 
current and the maximum guaranteed overcurrent trip point, 
which is 1 .4V. Usually the best choice is to operate with a normal 
peak voltage across the current sense resistor very close to 1 V, 
so 0.99V is a reasonable value. Note that this voltage drop 
across the current sensing resistor only occurs during current 
limit. In normal operation at loads below maximum, the trip point 
for the switch moves down to limit the energy going to the output. 
That is how this form of converter regulates. 

The drop across the switch is more complicated, because first we 
have to choose a main switch. To do this we need an estimate of 
what the current will be. Generally a close enough estimate can 
be made using the wattage into the magnetic and an estimated 
minimum voltage across the winding. If we assume that the 
voltage across the switch will be no greater than 1 .5V peak, we 
can subtract this voltage, and the current sense voltage, from the 
minimum input voltage and estimate DC input current: 

18V- (1.5V + 1V) = 15.5V 

Dividing the previously determined input wattage to the inductor 
produces a DC input current: 

55.93W-H 15.5V = 3.61 A 

Dividing that by the DC to peak conversion factor (based on t 0N 
= 49%) gives us an estimated peak current. 



3.61 * 



.49 
3 



: 8.93A 



Dividing the previously assumed drop across the switch by the 
estimated peak current gives us a target R DS( on) f °r the main 
switch: 

1.5V H-8.93A = 0.1 68Q 

Estimating that 100V should be sufficient maximum drain voltage 
gives us a wide variety of devices from which to choose. The 
IRF530 at 0.16U and the MTP20N10 at 0.15H are closest. 



Aside 

Obviously, by altering the estimated value for drop across the 
switch up or down one could change which switch ended up 
satisfying the circuit requirements. The end result does not change 
the design process, only the efficiency of final converter, and how 
much one pays for the switch. It is also possible to start the 
design with a main switch already selected or a mandatory 
efficiency goal, and just fill in the appropriate value for R DS (on) 
when you get to that step of the process, but doing so may mean 
repeating that section of the calculations once or twice. 

Similarly, one can specify different transformer efficiencies, if 
efficiency or volume is more than ordinarily important. Readers 
are cautioned, however, that magnetic efficiencies below 92% or 
over 98% may not result in a practical design. 

By using the IRF530, our original estimate is close enough so 
there is no need to recalculate, and we can use the already 
calculated peak current to determine the value of current sensing 
resistor needed, which is simply 



peak 



v current sense' 



or 0.99V -s- 8.93A= 0.111 a 



The closest lower value is 0.110Q in 1%. A 0.11Q in 5% values 
could also be used with small risk of a worst-case combination 
causing current limiting at less than 100% of normal output. To 



3-46 



HV91 Applications 



determine wattage we can use the DC input current: 

3.61A 2 • 0.11£1 = 1.43W 
so a 1 .5W or 2W resistor would work. 

A Word on 

Current Sense Resistors 

Obtaining a good current sensing resistor is still a problem. Most 
common resistors are not fit for this service because they are too 
inductive. What answer there is probably lies in bulk metal resis- 
tors, or noninductive resistors, but be careful. Some "noninduc- 
tive" resistors are only "noninductive" at low frequencies, and can 
be the source of considerable error at high frequencies. Carbon 
film resistors and most metal film resistors are not recommended. 
Also, most of the low value resistors that look like carbon com- 
position resistors are actually film or wirewound resistors in molded 
cases. 4-terminal resistors specifically meant for current sensing 
are for the most part wirewound, and meant only for DC, not 
switched current measurements. Be sure to test the inductance 
of the resistor you intend to use before you install it in your circuit! 
Also, even a good noninductive resistor will not work properly if 
long leads or long printed circuit board traces are allowed to add 
inductance to the mechanical assembly. Good PCB layout prac- 
tice is mandatory. 

The Design (continued) 

We can also use the same procedure (I 2 • R) to determine the 
approximate power loss in the main switch. This is not the 
absolute loss, which will be a little higher due to the rise in R DS(on) 
with temperature in the MOSFET, but generally it will be close 
enough to start determination of heatsinking requirements. 

3.61 A 2 ' 0.16Q = 2.085W 

Note that because the DC input current is equivalent in this 
instance to the RMS current through the switch (or the current 
sense resistor), one does not need to account for duty cycle or 
time effects. 

Next, we need to determine the inductance required of the input 
winding. Now that we know the voltage across the winding and 
the peak current through the winding, all we need do is calculate 
the minimum t on and repeat the same procedure as for the output: 

t ON = .49 • 14.92usec = 7.31 usee 

then L = 15.5V +( 8 93A ) = 12.7uH 
V 7.31 usee / 

Now that we have the inductances of the output and input wind- 
ings we can determine the voltage stresses applies to the switch 
and diodes, and make a final determination of the appropriate 
devices. The trick here is that the inductance varies as the square 
of the number of turns, so the turns ratio varies as the square root 
of the ratio of the inductances. 

turns ratio = ij = 2.40 :1 or 1: .417 

Thus, when there is 65V present on the input winding, there will 
be 65V • .417 = 27.1V on the 5V output winding. Adding to this 
the +5V that will be present on the cathode end of the diode from 
the output gives 32.1V, and means that a 45V diode allows a 40% 
margin for noise spikes and should work well. Two good choices 



are the Motorola #MBR1045 and the #MBR1645, the difference 
between them being that the larger one would be a bit more 
efficient. 

Similarly, when the main switch is OFF, in addition to the 65V 
present from the input, there will be 

5.8V • 2.40 = 13.9V 

reflected from the output, for a total of 78.9V present on the drain 
of the main switch. This leaves a 26% margin for spikes. A 100V 
FET should work. 

A similar procedure based on turns ratio finds the voltage present 
on the diode on the 12V output. This output is ratiometrically 
linked to the 5V winding with its own turns ratio of 12.8 : 5.8, or 
2.20:1, so when there is 27.1V reflected from the input winding 
there will be 27.1 V • 2.2 = 59.6V, plus 12V from the output, for a 
total of 71 .6V across the 1 2V diode. A 1 00V, 1 A ultra high speed 
silicon diode, like a Motorola #MUR105 is a reasonable choice. 
Note that in the case of multiple outputs which conduct at the 
same time, the flyback magnetic does act like a transformer, but 
this is the only case in which it does. 

Next, we can complete the definition of the magnetic assembly. 
The inductances of the input and output side are known. What 
remains is to define the resistances of the windings. These can 
be calculated from the rule that for an optimum size/efficiency 
magnetic, 50% of the loss occurs as resistive loss in the wind- 
ings, and this loss is balanced among the windings based on the 
percentage of total power handled by each (the other 50% of the 
loss occurs in the core as hysteresis loss). Output power, as 
previously calculated, is 53.69W. Input power was calculated to 
be 55.93W. Thus power loss in the magnetic is 

55.93W - 53.69W = 2.24W. 

The copper loss should be close to 1.1 2W. Half of this, .56W, 
occurs in the input winding, which must supply all the outputs. 
The other half is split between the 5V and 12V windings in the 
ratio of their respective powers. For the 5V winding this is: 

(Hf)'- 56 = - 467W 
For the 12V winding it is: 

(H!).. 56 = . 093W 

Knowing a target wattage and DC current for each winding (in 
this case DC = RMS) we can calculate resistances from I 2 • R. 

input: .56W + (3.61 A) 2 = .043n 

5V output: .467W * (8A) 2 = .00730 

1 2V output: .093W ■* (0.7A) 2 = 0.1 90Q 

This completes the definition of the magnetic assembly. 

Actually, because it is difficult to balance power loss between 
windings, or between windings and core, easing the calculated 
values up somewhat (as much as 20%) may result in a magnetic 
that would be significantly smaller with no increase in total losses. 
This should be discussed with your magnetics vendor. Also, 
because modern high-performance ferrites tend to have very low 
losses at moderate frequencies like 50 to 1 0OKHz, you may wish 
to divide the total power loss differently, say 40% core, 60% 
copper. This can also reduce the cost of the inductor without 
increasing its size. This probably will not work if the clock fre- 
quency of the converter is 200KHz or more. 



3-47 



HV91 Applications 



Leakage Inductance 

The final thing you need to specify with regard to the magnetic is 
a maximum leakage inductance. Leakage inductance is a mea- 
sure of the amount of flux generated by one winding in a mag- 
netic assembly that is not coupled to the other winding(s) by the 
core and winding structure. For a flyback converter it is a mea- 
sure of how much of the energy taken into the input winding is 
incapable of being transferred to the output winding when the 
switch turns OFF. This energy appears as a voltage spike on the 
drain of the MOSFET each time it turns off and must be dissi- 
pated either by the MOSFET directly, or in a snubber circuit. A 
reasonable value for leakage inductance is 1% to 2% of nominal 
inductance, but this is highly variable and depends on the in- 
tended operating frequency, size, and efficiency of the magnetic 
being developed. An actual maximum value should be discussed 
with your magnetics vendor before it is cast in concrete, and that 
maximum value should be used later for the development of a 
snubber, if a snubber appears to be worthwhile. (See Figure 3.) 

Next, we select the output capacitors. Two criteria need to be 
met. First, the minimum capacitance must satisfy the standard 
capacitance definition I = C dV/dt where I is in Amperes, C in 
Farads, delta t = t ON and delta V = 25% of the allowable output 
ripple. Second, and almost inevitably harder, the Equivalent Series 
Resistance (ESFt) of the capacitor(s) must provide no more than 
the part of the ripple (75% in this case) not provided from the first 
criteria, in accordance with 

^ripple - 'peak * ESR 

where l peak is the peak current from the output inductance during 
discharge. (This is because when the main switch turns OFF, the 

Coupled Inductor Specification 

(Preliminary) 
5 




(outputs) 



Nominal Operating Frequency: 50 to 60 KHz 

WDG 1-2: L = 12.7(iH ± 5% with 8.9 A DC Flowing 
DCR < 0.045 Ohm 

Leakage Inductance 1-2 with 3-4 shorted: < 200nH 

WDG 3-4: L = 2.2jiH ± 5% with 19.6 A DC Flowing 
DCR < 0.0075 Ohm 

WDG 3-5: Voltage ratio of 3-5 to 3-4 12.8: 5.8 ± 2% 
DCR < 0.19 Ohm 

Polarization: Starts must be as shown on schematic 
(pins 1, 4, 5) 

Insulation: Vacuum impregnate in class A 
thermosetting varnish 

Interwinding Insulation: Not applicable 

Expected Thermal Rise: <45°C in 40°C ambient 

Mounting: Through-hole PCB Figure 3 



current in the filter capacitor switches, effectively instantaneously, 
from an outbound current l ou ,, to an inbound current, (l peak - l oul ). 
The reason for splitting the allowable ripple between the two 
criteria is that in the final converter they will tend to add. The 
reason for the asymmetrical split of the allowable ripple is that the 
ESR-caused ripple limit is the more difficult criteria to meet. In 
some instances a more drastic partitioning (5 or more to 1 in favor 
of the ESR ripple) may be better. 

For the 5V output these criteria calculate out as follows: 

C = 8A -h ((.25 • .025V)/10u.sec) = 12,800uF 

and 

ESR = (.75 • ,025V) + 19.59A = 957uI2 

Based on Mallory type THF capacitor (330uF, 6 WVDC, ESR < 
0.04£2) (a typical good output filter capacitor). This works out to 
42 pieces in parallel to satisfy ripple from an ESR standpoint, and 
39 pieces to satisfy ripple from a capacitance standpoint. Close 
enough. Note that the capacitor chosen is a tantalum capacitor, 
If you wish to use aluminum capacitors to perform the same 
service you can ignore ripple from capacitive droop an-1 assign 
1 00% of the ripple to ESR. Sizing an aluminum capacitor strictly 
from ESR will generally provide one with 40 to 100 times more 
capacitance than is needed. This will slow down the transient 
response of the converter, but it means that you will rarely, if ever, 
encounter stability problems. 

Aside 

Based on the price of Mallory THFs, the stated stolution may not 
be an optimum solution to the problem. A better solution might be 
to change the effective ripple specification from <0.025V to 
S0.250V and add an additional stage of LC filtering from the 
nominal output to the "real" output seen by the load. This means 
that instead of 42 capacitors we can use 4, but these must be 
followed by an LC filter with 10:1 attenuation (20dB) at 50KHz. 
This implies a corner frequency, f c , of 5KHz, which means it won't 
be a small filter, but there is no necessity of using a high perfor- 
mance capacitor on this second filter stage. The other difficulty 
with a second-stage filter is that the DC resistance of the inductor 
is not cancelled by the feedback loop, and consequently the 
variation in output voltage with load current can exceed the 
specifications for the power supply. To hold the + 1% regulation 
specification on the 5V line we would need an inductor with = 
.0030 resistance. 

A second alternative would be to use a combination of electrolytic 
and film capacitors in parallel with the electrolytics sized solely to 
the load current ripple criterion and the film capacitors sized 
solely to the ESR ripple criterion. In this instance, ESR and 
capacitive droop should divide the ripple about 50-50. (See 
Figure 4.) 

Next we define the filter capacitors for the 12V output in the same 
way: 

C > OVA - 25 '- 5V \ therefore C > 56uF 
\ 10usec / 

ESR < (.75 • .5) * 1.715A, therefore ESR < 0.21 9H 

This is a much easier capacitor to find. A Sprague type 676, 
900nF 12WVDC, aluminum electrolytic (the smallest 12V capaci- 
tor in this series) will work well. A 56uF, 1 5V, Mallory type THF will 
also work. 

Next we define the divider resistors which will be used to feed 
back a sample of the 5V output to the error amplifier in the PWM. 



3-48 



HV91 Applications 



Output Filters for Equivalent Ripple 



C = 42 pes. Mallory #THF337M006P1G 
Total 13,860uF 



Cost: 
Respc 
Volume: 



Highest 
Fastest 
Smallest 



3 



■* — rm 1 + 1 + j* 1 + 



T T T T 



TTTT 



Feedback 



1jiF Mylar 



C1 = 4 pes. Mallory #THF337M006P1G 

C2 = 1 United Chemi-Con #RZA 22,000|iF 6.3v 

L = 1 .5mH; .0025 Ohm 

Total C = 23,320nF 



Cost: Intermediate 

Response: Intermediate (Reduced Load Regulation) 
Volume: Largest 



3 

3 



B 



-t — r 



1.55mH, .0025 Ohm 



22,000uF 



1(iF Mylar 



Feedback should be taken 
from before second filter to 
avoid stability problems. 



C = 4 pes. Sprague #676D159M6R3JT5C 
Total C = 60,000uF 

Cost: Least 
Response: Slowest 
Volume: Intermediate 



— mr 

TTTT 



Feedback 



1(iF Mylar 



Figure 4 



Because the error amp in the HV9110 is CMOS, its input bias 
current is negligible, and the divider string can carry a very small 
current; 100uA is plenty. The feedback terminal of the HV9110 
(the inverting terminal of the error amplifier) is satisfied by 4.00V 
±1%. If we use a 100uA divider, the lower resistor should be 

4.00V .0001 A = 40kH 

The closest real value is 40.2KJ2. To produce exactly 4.00V with 
40.2KH we need an actual divider string current of 

4.00V * 40200Q = 99.50uA 

Dividing the 1V remaining between 4V and our intended output 
of 5V by our actual divider string current, gives a value of 

1.00 .00009950 = 10,0500 

The closest value is 10.0K. 

Normally, the next and final step in the design process would be 
stability analysis. However, it turns out that one of the advantages 
of discontinuous-mode, current-mode flyback converters with a 
maximum duty cycle of < 50%, with output capacitors (especially 
if they are aluminum electrolytics) sized to ripple requirements, is 
that they are usually stable "as is." As a matter of prudence, 
checking the loop response of a new power supply on a network 
analyzer or Venable machine is always a good idea, but for 
supplies of this nature this writer no longer considers full analysis 
mandatory. For this reason, and because including stability analy- 
sis in this application note would probably double its length, 
analysis is omitted. For those desirous of performing a full math- 
ematical analysis of every loop, the following texts 5 on the subject 
are recommended: 

DC to DC Switching Regulator Analysis 

Dan Mitchell, McGraw-Hill, ISBN 0-07-042597-3 

Switch Mode Power Conversion 

K. Kit Sum, Marcel Dekker, ISBN 0-8247-7234-2 



Modeling, Analysis and Design of PWM Converters, vol. 2 
VPEC staff, VPEC 2 , ISBN (none) 3 

Advances in Switched-Mode Power Conversion, vol. I and II 
R. D. Middlebrook and S. Cuk, Teslaco, ISBN (none) 4 

Dynamic Analysis of Switching-Mode DC to DC Converters 
Nathan Sokal, Andre Kislovski, and Richard Redl, Van Nostrand 
Reinhold, ISBN 0-442-21396-4 

Modern DC to DC Switchmode Power Converter Circuits 
R. Severns and G.E. Bloom, Van Nostrand Reinhold, 
ISBN 0-442-21396-4 



Accessory Circuits 



1. The snubber circuit for the MOSFET drain switching spike 
should be sized to absorb the energy taken into the magnetic that 
is not coupled to the output. The available energy is 1/2 L • I 2 
where L is the leakage inductance of the primary and I is the peak 
input side current. Using a reasonable estimate of 2% for leakage 
inductance gives a value of 250nH. Spike energy then is: 

1/2 (250nH • 8.93A 2 ) = 10.1uJ 

Multiplying this by the maximum repetitions per second (which 
occurs at maximum frequency) gives 

10.1uJ • 67,000Hz = .679W, 

which is the amount of power to be dissipated either in the 
MOSFET or the snubber. 

To dissipate it in the snubber it must be captured in the snubber 
capacitor without exceeding the drain breakdown of the FET. 

Minimum FET breakdown: 100V 

Maximum circuit-supplied voltage on FET drain: 78.9V 

Maximum voltage for snubber cap: 21 .1 V 



3-49 



HV91 Applications 



High Switched Current Paths 



+VIN 



COM 



14 
13 



2 8 



7 6 



FDBK °~ 00 =• 

OUT 

ffl S < to ,53 M 

CC > CO £3 ^ 



IT n 

1 2 



> 4 

4 Its 



5 




1:5V Output Loop: 19.5A delta I 

2: Input Loop: 8.9A delta I 

3: 12V Output Loop: 1 .7A delta I 

4: MOSFET drive ON Loop: 0.6A delta I 

5: MOSFET drive OFF Loop: 0.6A delta I 



Figure 5 



To calculate the size of the snubber capacitor we convert the 
1/2 L • I 2 energy previously calculated to 1/2 C • V 2 energy, and 
divide by the maximum voltage we desire on the capacitor: 

(2* 10.1uJ)-*- 21.1V 2 = 0.045uF 

Using the next larger real capacitor (.047 in this case) assures us 
that the voltage spike will not be large enough to break down the 
MOSFET. The resistor in series with the snubber capacitor must 
have a low enough value to allow the capacitor to discharge in 
the minimum on-time of the switch, which for a HV9110 will be 
about 200nsec. Because the discharge distance (62.5V max) is 
much greater than the charge distance (21 .1 V) declaring 400nsec 
= RC will work. Thus 

400nsec + 47nF = 8.51 Q 

The catch here is that, except when the switch is on for the 
minimum time, the capacitor will reverse charge to 



■(V F et+V, 



) or 62.5V. 



current sense. 

It is this energy which must be dissipated in the resistor: 

1/2 (62.5V 2 • 47nF) • 67KHz = 6.15W 

So a 1 0W resistor will be necessary. To save 679mW in the FET, 
this hardly seems worthwhile, but it can be done if desired. 

2. If a snubber is used, an RC filter network should be added 
between the current sense resistor and the current sense termi- 
nal of the HV91 1 to prevent the higher-than-usual leading edge 
spike on the current waveform from shutting the switch off prema- 



turely. The RC time constant of this filter should be approximately 
20% of the snubber time constant, but never more than =100 
nsec. (Otherwise authentic fault current spikes may be slowed 
down too much.) The R for the current spike filter can be a lot 
larger, and the C much smaller, because the load presented by 
the HV9110 is quite small (on the order of 3pF). Using a 1K£2 
resistor and a 75pF capacitor should be sufficient for the snubber 
above. 

3. Two small capacitors are shown in Fig. 2, connected directly 
at the converter outputs. These are 1 jaF stacked film capacitors 
with very good AC characteristics, intended for general noise 
suppression. They may not be necessary, but they are reason- 
able insurance. 

4. An Input EMI filter will also be required under most circum- 
stances. For conducted emissions, generally an asymmetrical pi- 
type filter is sufficient. The converter-side capacitor should be 
sized to convert the delta I caused by switching to a reasonably 
low delta voltage over t otf . The inductor and input side capacitor 
should be designed to have a corner frequency that comple- 
ments the corner frequency of the regulator loop, to minimize 
susceptibility to outside noise coming in to the regulator. 

In this case, from previous calculations, input switching current is 
known to be a maximum of 8.9A. Similarly, minimum t off is 
7.46usec, and a reasonably low value for delta V is 250mV. Thus, 
from I = C dV/dt, the converter side capacitor calculates out to: 

8.9A + (.25V * 7.6 x 10" 6 sec) = 271 uF 



3-50 



HV91 Applications 



A good choice is 330uF. This capacitor can also serve to insure 
a minimum holdup time for short input dropouts. 

The values of the inductor and the input side capacitor can be 
calculated from 



fr = 



2tiVlC 



once the corner frequency of the regulator loop is known. In this 
case the regulator loop is rather slow, due to the large output 
capacitors required by the ripple specifications, and an appropri- 
ate frequency to use is only 750Hz. This gives us a VLC = 212 
x 1 0' 6 . This means that any combination of inductor and capacitor 
values whose product is 4.5 x 1 8 will provide an adequate filter. 
Generally, it is best to use a larger value of capacitor and a 
smaller value of inductor because inductors usually cost more. In 
this case using a 1 0OOuF capacitor results in a 45uH inductor, 47 
or 50u.H is easily obtainable, small and inexpensive. The DCR 
should be low enough so that our previous calculations based on 
V, N remain valid. Based on 3.6A maximum DC input current, a 
0.5U DCR will give a 0.14V drop, which is well within allowable 
safety margins, and results in a cheap, small inductor. 

On Layout and Noise 
(Radiated EMI) 

Anyone using the HV9100, HV9110, or other parts in the same 
family, will end up switching current flow on and off. Sometimes, 
quite large currents are switched in short periods of time. In the 



current example, the dl/dt on the 5V secondary will be over 300 
amps per microsecond! This is sufficient to cause significant 
radiated EMI if it is improperly handled. 

Controlling EMI from a switchmode converter is neither difficult 
nor costly, provided attention is paid to the subject early enough 
in the design cycle. 

There are no "tricks" to EMI control, only one basic rule: Minimize 
the area of the loops around which switched currents circulate. 

This is purely a mechanical constraint, and should be dealt with 
during PCB layout. Generally, unless you have a PCB layout 
person with prior experience with switching converters, the circuit 
designer will have to lead the board designer through the first few 
layouts, and even thereafter, will have to show the board de- 
signer where the switched current loops are in the circuit. (See 
Figure 5.) 

Obviously, there are other constraints to a switchmode converter 
PCB as well, and these also affect system performance. Most 
converters should be laid out single-sided, with the second side 
of the PCB reserved for a ground plane. Also, high currents 
require wide lands, just to keep DC resistances low. First and 
foremost though, should be the effort to keep switched current 
loop area minimized. Loop length is also important, as long runs 
can have enough inductance to disrupt circuit operation. On the 
9110/9120 this is only likely around the gate drive loops, which 
have relatively low delta I's, and the current sense resistor, where 
stray inductance can cause the overcurrent sensing to shut the 
main switch off prematurely, thereby limiting power output. 



Effect of a Local V DD -V ss Capacitance 
on Area of MOSFET On-Drive Loop 



+VIN o- 



Current loop with no local capacitor ■ 
Area deleted with local capacitor 
Resultant smaller loop 



14 
13 



FDBK ° 
C0MP„ 



COM 





Figure 6 



HV91 Applications 



Board layout should proceed by taking the switched current loops 
in order of delta I, and laying the DC portions of the circuit out last. 
Using the first circuit as an example, this means starting with the 
5V loop, (which includes only the coupled inductor, 5V diode, and 
output capacitors) taking the input loop next (coupled inductor, 
power MOSFET, current sense resistor, and input filter cap) and 
following those with the 12V output loop, and the MOSFET drive 
loops. In each instance, it is the entire loop that matters, including 
the return path. Assuming that the return path is good, even on 
boards with ground planes, is risky. Look at each loop carefully 
to see that its area is minimized. After the switched current loops 
are laid out, the DC sections can be fitted where they are conve- 
nient. They do not contribute noise, but they can convey it if it is 
generated elsewhere. The feedback loop is a special case. By 
itself, this is a DC loop, but it is susceptible to noise generated on 
other loops, and because it is, for the most part, a high-imped- 
ance path, not much energy is required to disrupt it. The feed- 
back loop should also be laid out for minimum area, but it is more 
important that the path of its circuitry lies well away from, and 
where possible perpendicular to, the switched current loops. 
Generally, layout grows outward from the transformer, and care- 
ful choosing of which pins on the transformer connect to which 
windings can do a lot to make layout convenient. 

There are a few things that can be done in designs with the 
HV91 XX family that may make a specific layout more convenient: 
First, it should be remembered that the high current paths asso- 



ciated with the current sense resistor do not include the line from 
the junction of the resistor and the MOSFET to the current sense 
terminal of the IC. The sense lead to the IC is a very low current 
path, and can be comparatively long providing that the path from 
MOSFET to resistor to ground is short. The output lead from 
HV9110s and HV9120s however should be kept short, because 
it services both the charge and discharge paths from the MOS- 
FET gate. Also, when a 10V or 12V winding on the transformer 
is used to power the HV91XX, it may help to split the filter 
capacitor into two pieces, one near the transformer and diode (to 
keep that current loop short) and a second near the HV91XX to 
keep the ON-drive current loop short. The V DD and V ss terminals 
of the HV91XX are adjacent to each other specifically to allow 
this. (See Figure 6.) 

Inevitably, there will be some residual radiated EMI, and some of 
this will be picked up by the DC circuits and seen on the input and 
outputs as conducted EMI. The 1uF film capacitor previously 
noted should suffice to remove this from the outputs, and a small 
commercial line filter should suffice for the input. Most commer- 
cial EMI filter suppliers offer EMI lab services (sometimes free!) 
to assure that the end converter + filter meets whatever require- 
ments are in force for your particular circumstances. Using these 
services as a final check is generally worthwhile. 

There is only one additional noise control measure necessary. 
The reference pin of the HV91 XX is a high impedance node, and 
is designed to work with a 0.01 uF to 0.1 uF capacitor between 



The Final Design 



L1 47u.H, 0.5 Ohm 



+VIN 

+C8' 
1 ,000uF 
100V 



COM 



+C9 

330u.F 

100V 



R2 

10.0K 1% 



14 
13 



R3 
261 K 1% 



T1 



U1 



FDBK 



°HV9110 out 

COMP^ Sin m 

d 23 i < 2 » w 

to a: > ta o >• o 



IT n 

1 2 



1 



C5-L 
0.1 jiF 

R1 

40.2K 1% 



D2 

mIjf 



D1 MUR105 



MBR1045 

5 C2 



R6 
1K 

C4 
75pF 



Q1 

IRF530 



R5 

0.111 1% 
Noninductive 



4 pes 
15,000uF 
6.3\T 



+12V 



C3 
^56uF 



15 




R7 
390K 



Figure 7 



3-52 



HV91 Applications 



+VIN 

O 

90 to 
390VDC 



Option A 



ISOIBi 




R9; 



R1 



Input o_ 
return 



Figure 8 



15 



14 



Example 2 

1 T1 



R6 



1 9 



=fc C7 



> tog cn=> C2 
FDBK ° Hv g^20 > 0UT 

t/3 cc > ra o > o 



:R2 



h h 

2 3 



C9 



R3 



C6 



D3 

-4* 



R4 



7 .3 



Q1 



>R5 



M 51 



C1 



fr.4 



f /» 



f.5 



C2^ 




VOUT 



D2 



Output 
return 



-5V OUT 



If the converter's outputs do not exit the enclosure 
C3 and C4 generally are not used, or are replaced 
with bypass caps at the loads they supply. 




Option B 



itself and V ss . This capacitor should not be omitted. On the other 
hand, a capacitor between the bias pin and V ss should not be 
required. If a capacitor from the bias pin to V ss improves opera- 
tion, the capacitor should be placed from V DD to V ss . As usual for 
any switching circuit, all noise filtration capacitors should be 
types with good high frequency performance: Stacked Mylar and 
ceramic multi-layer caps generally are best. (See Figure 7.) 



Example 2 



A 3W converter for a DPM. Size is to be as small as is consistent 
with low cost, input range is 65VAC to 240VAC, load is fairly 
constant. 

As before, the first thing we need is specifications to design to: 

Maximum Input Voltage: 390VDC {[(240 + 1 5%) • Vl]-1 .4} 

Minimum Input Voltage: 90VDC [(65 • VI)-1 .4] 

Outputs: A: +5V ± 5%, 0.4 to 0.55A, < 100mV ripple 

B: -5V ± 5%, 30mA, < 100 mV ripple 

C: +10V ± 10%, 14mA, < 100mV ripple 

Maximum Output Wattage: 3.04W 

Minimum Output Wattage: 2.29W 

Operating Frequency: 500KHz (min) 

An HV9120, which accepts input voltages up to 450VDC will be 
required. This time, even with the high operating frequency, 
sufficient dynamic range exists (13.2:1) so that the end supply 
should not exhibit cycle skipping. This minimizes the size of 
output filters. (See Figure 8.) 



ated with the PCB layout can have a serious effect on clock 
oscillator performance at high frequencies (the timing capaci- 
tance in the 9120 totals less than 10pF), the value of the timing 
resistor should be confirmed in the final assembly to assure 
desired performance. 

Next, calculate minimum t off and t on . If minimum frequency is 
500KHz, worst case maximum can be up to 600KHz, and at 
600KHz, maximum duty cycle will be no greater than 46.5%. 
Thus, minimum t on will be: 

1 667 nsec • .465 = 775 nsec 

and minimum t 0(f will be: 

1 667 - 775 = 892 nsec 

or 53.5% of total period. For peak current calculations (to follow) 
it will be sufficient to declare D (duty cycle) = 46.5%, and 1-D = 
51 .5%, leaving a 2% deadband to assure discontinuous-mode 
operation. 

Next, translate the DC current of the output with the greatest 
percentage of the load (+5V this time) to a peak current using the 
same formula as in the previous example: 



.55A 



.515 



1 .328A I 



peak 



The Design 



First, select a timing resistor. To assure that all units operate at 
500KHz or above despite tolerance effects, a 16.5K£2 resistor 
should be sufficient. But, because parasitic capacitances associ- 



This allows us to calculate the inductance of the secondary using 
E = L dl/dt. Remember that the voltage seen by the inductor 
includes the forward drop of the output diode, so the actual 
calculation works out to: 

5.75V h- ( 1 .328A * 858nsec) = 3.72uH 

The -5V winding will be equal in turns (thus also in voltage and 
inductance) to the +5V winding. The 1 0V winding, (which powers 
the HV91 20) conducts at the same time as the main +5V winding, 
and thus has a turns ratio equal to its voltage ratio, (10.7 : 5.7) 
and no inductance calculation for it is necessary. 

SIDE NOTE: The load stated above for the 10V winding (14mA) 
is considerably larger than the 1 mA specification for the HV91 20. 



3-53 



HV91 Applications 



The remaining 13mA are what is required to provide the charge 
to the gate of the power MOSFET the HV9120 will be driving at 
500KHz. This current was determined by dividing the total gate 
charge of the MOSFET (Q g ) at V g = 1 0V (from the MOSFET data 
sheet) by 1 0V (V g ) to determine the effective gate capacitance, 
then using that capacitance value in I = CV 2 f (converting charge 
to current) to determine the current required to charge the gate 
500,000 times per second. While this calculation is a good check 
of real supply current for the HV9120 in operation, it is seldom 
necessary unless the converter is operating at over 100KHz. 

Next, using the same system, calculate the required inductance 
of the input winding. To start, we need the power into the mag- 
netic, which is just the power out of the magnetic divided by its 
efficiency. Power out of the magnetic includes not only output 
power, but the voltage drop through the output diodes. At the 
currents needed, 0.75V is a safe estimate for diode drop. So 
maximum power out of the magnetic will be: 

[5.75V • (.55A+.03A)] + (10.75V • .014A) = 3.485W 

Because it is more difficult to design small magnetics (and size 
was one of our original constraints) to high efficiency, and be- 
cause higher frequency magnetics tend to be less efficient, this 
time I will adopt an efficiency estimate of only 94%. Now, power 
into the magnetic calculates out as: 

3.485W + 0.94 = 3.707W 

To obtain a DC input current, this wattage is divided by the 
minimum DC voltage across the input winding, which is just the 
minimum DC input voltage less the drop in the current sensing 
resistor and the power MOSFET. The maximum drop across the 
current sensing resistor again should be set to just under 1 .0V 
(from the HV9120 spec.) and a reasonable estimate for drop in 
the MOSFET is 2. 1 V, (based on the use of a Supertex #VN0660N3, 
600V, 20n MOSFET). So minimum input side voltage will be: 

90 -(1 + 2.1) = 86.9V 

and DC input current will be: 

3.707W h- 86.9V = 42.7mA 

Knowing DC input current and duty cycle we can now calculate 
peak input current, which will be: 



0.0427A 



■V 1 



465 



= 0.1 08A 



Knowing peak input current, minimum input voltage and smallest 
maximum t on , we can now calculate input side inductance from 
E = L dl/dt. This works out to: 



86.9V 



( J08A \ 
\775nsec/ 



= 624uH 



Next, we need to determine the DC resistances of the various 
windings of the magnetic. In this case, because of the operating 
frequency, copper losses and core losses probably will be 
approximately equal. Again, power loss in the magnetic is just 
P in - P oul or 222mW. Assuming half of this is copper loss gives 
a copper loss of 111 mW. This should be divided among the 
various windings in proportion to their proportion of the total 
wattage. 

Input winding: 50%, or 55.5 mW 
+5V output: 45.4% or 50.4 mW 
-5V output: 2.5% or 2.75 mW 
+1 0V output: 2.2% or 2.40 mW 



Coupled Inductor Specification 

(Preliminary) 



7», 



Schematic 

Nominal Operating Frequency: 500 to 600 KHz 

WDG 1-2: L = 625jiH ± 5% with 0.10 A DC Flowing 
DCR = 30 Ohms MAX 
Leakage Inductance 1-2 with 3-4 shorted 
10nH MAX 

WDG 3^1: 3.7uH ± 5% with 1 .3 A DC Flowing 
DCR = 0.16 Ohms MAX 

WDG 5^1: Voltage ratio WDG 5-4 to WDG 3-4 
1.00:1.00 ±2% 
DCR = 3.0 Ohms MAX 

WDG 6-7: Voltage ratio WDG 6-7 to WDG 3^t 
10.7 : 5.7 ±2% 
DCR = 12.5 Ohms MAX 

Polarization: Starts must be as shown on schematic 
(pins 1 , 4, 5, 7) 

Insulation: Vacuum impregnate with class H 
thermosetting varnish 

Interwinding Insulation: WDG 3^-5 to WDG 1-2 and 6-7 
min 1.5KVAC 

WDG 1-2 to WDG 6-7 min 500VAC 
Expected Thermal Rise: <60°C in 50°C ambient 
Mounting: Through-hole PCB Figure 9 



Actually, this shortchanges the input winding somewhat, as it 
carries slightly more power than all outputs combined, but this is 
usually trivial. As before, DC current (NOT peak) is used to 
determine resistance knowing dissipation: 

For the input winding: .0555W + .0427A 2 = 30£2 

For the +5V winding: .0504W + .55A 2 = .166£i 

For the -5V winding: .00275W + .030A 2 = 3.06£J 

For the 10V winding: .0024W + .01 4A 2 = 12.24ft 

This gives us enough information to complete a specification for 
the coupled magnetic. (See Figure 9.) 

The value of the current sensing resistor can be determined once 
the peak input current is known. The sensing voltage levels for 
the HV9120 are the same as they were for the HV9110 in 
example 1 . Thus 

0.99V-H0.108A = 9.16Q 



3-54 



HV91 Applications 



The next lower resistor is 9.09Q in 1% or 9.1 Q in 5%. As the last 
time, using a 5% resistor will probably result in very few (if any) 
units that do not allow full output power at low line. Wattage of the 
current sense resistor is calculated as l 2 R using DC input current 
(42.7 mA). This calculates out to 16.6 mW based on a 9.1H 
resistor, so a 1/10 watt resistor (if you can find a noninductive 
one) can be used. 

The drop across the main switch and its power loss should be 
calculated next. In this case we already selected a main switch 
(a Supertex VN0660N3) based solely on its being the smallest 
(and least expensive) 600V MOSFET available. The on-resis- 
tance of the VN0660N3 is 20n, which implies a peak-current 
voltage drop of 2.16V, and a power dissipation of 36mW, which 
is easily handled by the TO-92 version. 

Using the "square root of inductances ratio" we can now deter- 
mine the approximate voltages reflected across the coupled 
inductor to determine the actual voltages present on the main 
switch when it is off and the diodes when they are blocking. This 
time that works out to: 



V 



625 x 10" 6 



3.7 X 10" 6 

or almost exactly 13:1, Thus when the main switch is off, it will 

see: 

5.7V x 13 = 74V 

added to the 390V present from the input, a total of 464V. The 
diodes, when blocking, can see a maximum of 

390 + 13 = 30V 

added to the 5V present on the output capacitors. So 1A 40V 
Schottky diodes, such as the 1N5819, should work well for 5V 
output diodes. 

If increased efficiency were required, 1 N5822 three-amp Schottky 
diodes, and/or a 500V, 16a, VN0650N3 main switch could be 
substituted. 

As with the first example, the next thing to do is to calculate the 



requirements for the output filter capacitors. This time the ripple 
specification is easier to meet (100mV vs 25) and the loads are 
smaller. The technique remains the same, and a 25%/75% divi- 
sion of ripple between capacitance and ESR should still hold. 
Thus, for the +5V output 

C = 0.55A + (.025V + 930 x 10 9 sec) = 20.5uF 

Remember that for capacitor holdup, maximum rather than mini- 
mum t,,,, is used, as the time for which the capacitor must hold up 
is the maximum time the switch could possibly be on. ESR ripple 
is also done exactly as before: 

ESR = .075V * 1 .328A = .5650 

This is a much easier capacitor to find. A Nichicon SF type 1 50uF, 
6.3V would work fine. So would a Sprague 672D227H6R3CG3C 
(220uF, 6.3V aluminum) or a Sprague 199D336X96R3DA1 (33uF, 
6.3V dipped tantalum). 

The -5V secondary works the same way, except the current is 
only 30mA: 

C = 0.030A + (.025V -*- 930 x 10' 9 sec) = 1 .1uF 

ESR = .075V + .073A = 1 .0£2 

In this case, because the load current (and thus the capacitor) 
are so small, it is probably better to use a 1uF stacked film 
capacitor and ignore the ESR which will be orders of magnitude 
below requirements. A 1uF 50V Wima #MKS-2 (ESR » .02£2) 
would be fine. The same capacitor could also be used on the 1 0V 
output that feeds the HV9120 (14mA). This particular capacitor is 
also an excellent choice for the final noise filters on the regulator's 
outputs (as in example 1). But in this case the regulator's outputs 
will not go outside the enclosure and extra noise filters are 
probably unnecessary. 

Feedback for this circuit is shown two ways: First, as just a 
resistive divider off the secondary that feeds the HV9120, and 
second as optical feedback, which requires additional circuitry. 
(See Figure 10.) For the regulation specifications given, (±5%) a 
resistive divider on a separate winding is sufficient over the 



The Final Design 



+VIN 

O 

90 to 
390VDC 



Option A 




i R10< 
!100K^ 



C9 
4700pF' 



R6 16.5K 
1 9 



U1 



220pF~inT 
Note 1 2 3 

C5 . 
0.1uF" 

R2 
100K 1% 
Note 1 



HV9120 



n > m □ 



:C6 
33Pf 



R3 
390K 



D3 

K- 

1N4148 

: C7 
1|XF 



_QlJ£ 



VN0660N3 



R5 



+5V OUT 




9.09 1% 
Noninductive 



Note 1 : Delete with Option A 



Output 
return 



1N5819 



-5V OUT 

If the converter's outputs do not exit the enclosure 
C3 and C4 generally are not used, or are replaced 
with bypass caps at the loads they supply. 



+5V o- 



R7 
6.19K 
1% 

R8 . 
6.19K< 
1% 
Return o- 



ISOIA 



V -K4N 



4N26 

3 

^ U2 
2 TL431 CLP 



Option B 



Figure 10 



3-55 



HV91 Applications 



industrial temperature range (-40°C to +85°C). Such a "divider on 
a separate output" relies on the magnetic coupling between 
windings on a common core to regulate the isolated windings. 
Within limits (accuracy, mostly) it works very well, but it would 
require an excellent transformer builder to be able to meet ±5% 
regulation of magnetically coupled outputs over a full -55°C to 
+125°C military temperature range. 

The resistive divider, as in the previous example, can draw very 
little current, because the CMOS error amp in the HV9120 does 
not draw significant bias current. Because the last example used 
100uA divider current this one will use 40uA. (Using much less 
than 20uA requires using high value precision resistors that are 
expensive.) Again, the feedback point of the HV9120 is internally 
trimmed to expect 4.00V at design output voltage. This time the 
design voltage of the winding directly coupled to the divider is 
10V, so using a 40uA divider current, the lower resistor becomes 
100Kfl, and the upper resistor becomes 150KQ. 



Accessory Circuits 



1 . No snubber circuit is shown on this converter, and none should 
be necessary. Maximum energy available to be snubbed, like last 
time, is just L, eakage x l peak 2 , or 117nJ per switch-off. At 600KHz 
that works out to 70mW, which is easy to ignore. Also, the main 
switch chosen has 20pF of reverse transfer capacitance, which 
can absorb this much energy while only rising an additional 76V. 
This still leaves V drain of the MOSFET below 90% of breakdown 
and should be safe. 

2. Leading-edge spike suppression on the current sense resistor 
can be handled as it was in the first example, with a 1 K£l resistor 
between the top of the current sense resistor and the current 
sense pin on the HV9120, plus a capacitor between the current 
sense terminal and ground. For this regulator, leading edge spike 
suppression is probably more important than it was for the last 
one, because the peak gate drive current to the power MOSFET 
is actually greater than the load current! Because the gate ca- 
pacitance of the FET is much smaller though, the capacitor's size 
should be reduced. 33pF is a good starting value. 

3. Optical feedback is usually only used on isolated outputs that 
must be regulated to a tighter tolerance than ±5% over industrial 
temperature range or ±7.5% over the military temperature range. 
Optically isolated feedback has been developed over the past 
few years so that it is straightforward and relatively inexpensive, 
consisting of a T.I. #TL431, an optocoupler and two to four 
resistors. Because of the high gain of the TL431 (80dB), virtually 
any level of accuracy desired is achievable. 

The TL431 requires 2.5V at its third terminal to achieve regula- 
tion. As we require a 5V output, the divider resistors will be equal. 
The TL431 requires a maximum of 4uA into the reference termi- 
nal. To hold reference current to a maximum of 1% divider error, 
divider current must be >400uA. Thus the divider resistors should 
be <6250n each. A reasonable value is 6.19K. The original 
feedback divider at the HV9120 is replaced by a divider com- 
posed of the phototransistor and its emitter load. Precision resis- 
tors for this divider are no longer required because the regulation 
loop will compensate for any errors here. The current used earlier 
on this path (40uA) can be kept, or adjusted as convenient. We 
will stay with the original value. 

The choice of optocoupler will depend on the loop response 
speed required. Optocouplers tend to be slow, and unless care 
is taken in optocoupler selection, the optocoupler ends up being 
the controlling element in regulation loop response speed. For 



this example, I used a 4N26 because it was on hand. A 6N135 
or similar high speed optocoupler would have given loop re- 
sponse more appropriate for a 500KHz converter. The resistor 
shown between the base of the optoisolator transistor and ground 
is a noise/leakage eliminator and should have a value between 
1MQ and 10M£1, depending on the optocoupler used. For a 
4N26, 4.7M works well. 

Because there are now two op amps in the regulation loop, loop 
gain will be far more than necessary, and some of it must be 
done away with. Otherwise stabilization will be a problem. There 
are two simple ways to eliminate gain. Either convert the error 
amp in the HV9120 to a gain of -1 configuration with two equal 
resistors, or add a resistor between the anode of the TL431 and 
output return to reduce its gain to approximately 1 . Both meth- 
ods work equally well. The error amp in the HV9120 has a 
minimum guaranteed output sink current of 120uA, so any feed- 
back resistor greater than 50K will allow full opposite swing. 
150K gives plenty of margin, and reduces power a little. 

Alternatively, a resistor between the anode of the TL431 and 
output return can be used as a gain-destroyer to reduce the gain 
of the TL431 (plus the optoisolator) to approximately 1. The 
value of the gain-destroyer resistor is dependent on the coupling 
"gain" of the optoisolator and the current required from the 
phototransistor. Using a 4N26, the current required from the 
phototransistor is approximately 40uA, and the LED current 
required to achieve it will be approximately 1 OOuA. To adequately 
reduce the gain of the TL431 will require a delta V on its anode 
of about 50mV, so a 470O resistor should work. 

Conclusion 

To demonstrate functionality, both examples were assembled 
and tested by a technician at our facility. A few suggestions to 
avoid difficulties are as follows: 

First, wire-wrap construction methods are, and always will be, 
completely incompatible with power supply construction. The 
light gauge wire will not carry the current, and the stray induc- 
tance caused by longer-than-necessary paths will disrupt the 
circuit and cause additional EMI. Seriously, the requirement for 
short, low-inductance, low-resistance paths and good mechani- 
cal layout throughout the design is mandatory. Every unneces- 
sary tenth of an inch of lead should be eliminated. This may not 
appear to save space in a completed design, but in fact it will 
save both space and trouble. 

Second, flyback power supplies should never be operated with- 
out a load! Once the main switch turns off, the energy stored in 
the coupled inductor inevitably goes into the output and charges 
the output filter capacitors. If no load is present to remove the 
charge, the capacitors or the output diodes will break down. 

Third, output voltage ratios for the multiple output windings may 
need to be adjusted slightly, to get all output voltages into 
tolerance. This happened in the small converter where the 10V 
output winding, because it was closer to the input winding than 
the other output windings, put out more voltage than planned. 
The solution was to reduce the number of turns on that winding 
by about 10%. 

Last, my choice of the optoisolator (a 4N26) was not appropriate. 
The result was that the regulation loop crossover frequency was 
only 9KHz, when it should have been over 1 0OKHz. A transistor 
with a 10usec storage time, like the phototransistor in the 4N26, 
just isn't capable of the response speed desired from a 500KHz 
switcher. 



In summation, two different circuits have been developed to show 
the flexibility of flyback converters built with the HV91XX family 
PWM ICs, and the simplicity of their design and construction. 
Both circuits met their original design goals. The field of use for 
the HV91XX family is a lot broader than can be illustrated in a 
single application note. Many other forms of converters, which 
may be best suited for their particular purposes can also be built 
using the HV91XX PWM ICs. Contact Supertex for additional 
application notes. 



1 . Reference Data for Radio Engineers, 6th ed. 
Howard Sams & Co., chapter 44, table 4. 

2. Virginia Power Electronics Center, 

Bradley Department of Electrical Engineering, 
Virginia Polytechnic Institute and State University, 
Blacksburg VA 24061 . 

3. Available from publisher or see footnote 5. 

4. Only available from publisher: TESLAco, 

10 Mauchly, Irvine CA 92718 (714) 727-1960. 

5. Books with ISBN numbers can be ordered from any book- 
store. All the books in this list except the TESLAco book can 
also be acquired from: 

E.J. Bloom Assoc. Educational Division, 

115 Duran Dr., San Rafael CA 94903-2317 

(415) 492-1239. They generally have them in stock. 

6. Magnetic assemblies for the converters were supplied by: 
GFS Manufacturing, Inc. 

140 Crosby Rd., Dover NH 03820-1409 (603) 742-4375. 



LP07 Series 
Application Note 

AN-D14 



Low Dropout 3.0 Volt Linear Regulator 

by Jimes Lei, Applications Engineer 



Introduction 

Low dropout regulators are becoming increasingly important as 
more and more equipment utilizes 3 volt and 5 volt analog and 
digital circuits. 

The main advantage of low dropout 3.0V linear regulators is full 
utilization of battery life which makes them desirable for battery- 
powered applications. The low dropout feature will allow for output 
regulation even when the input battery voltage is discharged close 
to its output regulated voltage. This will extend the operating input 
voltage range and allow circuits to operate at a lower battery 
voltage. 

This application note discusses the advantages of using Supertex 
part number LP0701 N3, which is a very low gate threshold voltage 
P-Channel MOSFET.This part has a guaranteed maximum thresh- 
old of -1 .0V and a maximum R ds(0 n) of 2.0 ohms at -3.0V drive. 
This performance is essential for designing an ultralow dropout, 
low voltage linear regulator. 



Circuit Description 



The low dropout 3.0V linear regulator shown on Figure 1 utilizes an 
LP07, an LM 1 0, 4 resistors, and 3 capacitors. The LP07 is a 1 6.5V, 
2.0 ohm, P-Channel MOSFET with a maximum threshold of -1 .0V. 
The LM10 is a dual op-amp with a 0.2V reference. R1 is a 
potentiometer. R2, R3, and R4 are 5%, 1 / 4 watt resistors. C1 , C2, 
and C3 can be either ceramic or electrolytic capacitors. 



A1 is configured as a unity gain buffer for the 0.2V reference. The 
output of A1 is attenuated by R1 and R2 and is connected to the 
inverting input of A2. A2 is configured as a noninverting amplifier 
with a closed-loop gain of (R4 / R3 + 1 ). The LP07 is configured as 
a common source amplifier, which functions as a series pass 
transistor while contributing additional gain to the open-loop gain 
of A2. The output of A2 regulates the gate of the LP07 for a V 0UT 
of 0.2V x [R1 / (R1 + R2) x (R4 / R3 + 1 )]. The resistor values are 
chosen (explained in detail in the design considerations section of 
this application note) and R 1 adjusted for an output voltage of 3.0V. 
C3 is in parallel with R4 to reject external noise. C1 and C2 are 
bypass capacitors. 

Any small decrease in Vqjjj due to a load applied to the output is 
sensed by R3 and R4 which is fed back to the noninverting input 
of A2. The output of A2 will drive the gate of the LP07 to a lower 
potential thereby increasing the gate drive adequately to source 
current to the output load and maintain a constant output voltage. 



Design Considerations 

The objective is to implement a 3.0V linear regulator with the 
lowest possible voltage drop from input to output. The output 
transistor for a linear regulator can be designed with N-Channel or 
P-Channel MOSFETs or bipolar NPN or PNP transistors. Figures 
2a to 2d (see page 2) show the four possibilities. 

In figure 2a, the dropout voltage using an N-Channel MOSFET is 
too large since it cannot be better than the threshold voltage of the 




V2LM10 



V REF T 0-2V 




Figure 1 : Low Dropout 3.0V Linear Regulator 




C1 =1= 1 .OuF 
1 LP0701 N3 X 



< » 'W\/ 1 > 

R4 TSOK^ 

C3 



0.01uF C2= L 10(lF 
R3 < 500Q 



-oV OUT = 3.0V 



3-58 



LP07 Series Applications 



I)— 




Vbatt 

N-Channel 



II— + 



AW 

R4 



_o Vqut = 3.0V 




Vbatt 
NPN 



Figure 2a: N-Channel MOSFET 



* o Vout = 3.0V 

R4 



Figure 2b: NPN Transistor 




o Vqut = 3.0V 



Vbatt 

P-Channel 



— Figure 2c: PNP Transistor 



R3 



-AAA* * o v out = 3.0V 

R4 



Figure 2d: P-Channel MOSFET 



MOSFET, which is 1 .0V to 4.0V, depending on the type of device 
used. In figure 2b, the dropout voltage using an NPN is lower but 
still fairly large. The dropout voltage is typically 0.7V, which is the 
V BE rating of the transistor. 

In figure 2c, the dropout voltage using a PNP transistor is limited 
by the V CE(sat) rating of the transistor, which is typically -200mV at 
low collector current. This approach also requires the output of the 
op-amp to operate 0.7V below its most positive rail at all times. 

In figure 2d, the dropout voltage for the P-Channel MOSFET 
approach is determined by the on-resistance of the device times 
the load current. The device is driven by the battery voltage minus 
the minimum output voltage of the op-amp. Similar to the PNP 
approach, the op-amp is required to operate one threshold below 
the battery voltage during the no load condition. When the battery 
voltage is discharged close to 3.0V, the MOSFET chosen should 
have a very low threshold and a very low on-resistance at low V GS 
ratings to achieve low dropout. 

Conventional P-Channel MOSFETs have guaranteed maximum 
thresholds of -4.0V, which would require the supply voltage to be 
greater than 4.0V for adequate turn on. A low threshold, low on- 
resistance P-Channel MOSFET is ideal for this approach. 

The Supertex LP07 has a guaranteed maximum threshold of -1 .0V 
and guaranteed on-resistance at -2.0V, -3.0V, and -5.0V drives. 
The specifications are shown on the following table. 



At -3.0V, the on-resistance is 1.7 ohms typical and 2.0 ohms 
maximum, which helps achieve a low drain-to-source voltage 
drop. Since the LM1 can swing very close to ground i.e., 0V, the 
dropout voltage can be estimated to be 2.0 ohms x (I LO ad)- For a 
50mA load, the dropout voltage is 0.1 V which means the battery 
voltage can be 3.1 V with the output still regulated at 3.0V. 

Preventing Unwanted Oscillation 

The LP07 acts as an additional gain stage to the open-loop gain of 
A2. The increase in open-loop gain causes the loop gain to be 
greater than 1 at low closed-loop gain conditions, which causes 
oscillation. Oscillation can be eliminated by setting the loop-gain to 
be less than 1. This can be achieved by setting R(negative 
feedback) < 1 / gain contributed by the LP07. 

The gain contributed by the LP07 is a function of the load and the 
transconductance, G FS , of the LP07. Figure 3 shows an equivalent 
circuit of the open-loop gain of the LP07. 



Parameter 


Min 


Typ 


Max 


Units 


Conditions 




-0.5 


-0.7 


-1.0 


volts 


V G s = V D s. Id = "10mA 


Rds(on) 




2.0 


4.0 


ohms 


V GS = -2V, l D = -50mA 






1.7 


2.0 


ohms 


V GS = -3V, l D = -150mA 






1.3 


1.5 


ohms 


V GS = -5V, l D = -300mA 



V g o-| S-P07 



-oVqut 



Gfs 



Vout = 



R3< 



PiLOAD 



v out = G FS 



= | I(R3 + R4)(R LOAD ) l 
[R3 + R4 + RloadJ 

(R3 + R4)(R L0AD ) 1 
R3 + R4 + RloadJ 



Figure 3: LP07 Open-Loop Gain 



3-59 



LP07 Series Applications 



Figure 4a: G FS vs. I at Low Currents 


Figure 4b: vs. I D at High Currents 




1.20 
1.00 
-g 0.80 

E 

to 0.60 
0.40 
0.20 


c 


















300 

250 

«•» 200 
p 

E. 

U) 150 
100 
50 





















































































































































































































10 20 30 40 50 60 70 

Id (HA) 


20 40 60 80 100 120 140 

Id (mA) 





The G FS of the LP07 varies with l D , which is also the load current. 
Typical G FS versus l D for low and high currents of the LP07 is shown 
on figure 4a and 4b respectively. 

For the no load condition, l D = 3.0V / (R3 + R4). It is desirable have 
R3 + R4 large to minimize the amount of biasing current. The sum 
of R3 + R4 is chosen to be approximately 150K. From figure 4a, 
G FS is 0.62m U for an l D of 20uamps. V OUT / V G is calculated as 
(0.62mU)(150K) = 93. 

For a load current of 100mA, R LOAD = 3.0V/ 100mA. Using figure 
4b, V OUT / V G is calculated as (310mU)(30ohms) = 9.3. The open- 
loop gain varies with load and is at its maximum during the no load 
condition. The negative feedback, 3, is R3 / (R3 + R4) and should 
be set less than or equal to 1 / (V OUT / V G ). 

It is desirable to set 13 «1 / 93 since 1 / 93 is a typical value. R3 and 
R4 are chosen to be 500 ohms and 150K respectively for a 13 of 
1 / 301 , providing an adequate safety margin. 

Calculations 

The offset voltage, V os , input biasing current, l B + and l B -, and 
tolerancesof the external resistors will affect the output voltage. R1 
is used to adjust V 0UT to 3.0V. Figure 5 is an equivalent circuit 
showing V os , l B + , and l B -. 



To determine the range of R1, the range of V, needs to be 
determined under the worst case conditions. Using superposition, 
V OUT is calculated as: 

Vout = (Vos + V,)( f & +1 ) + l B *R4 + | B -( +1 ) 

The LM10 guarantees V os = 4.0mV max and l B = 30nA max. 
R1 X R2 / (R1 + R2) is set at 2K. 

For minimum Vi: 

3.0V = (V, + 4.0mV)( 1 ^| K +1 ) + 30nA (1 57.5K) + 

3.0V = 3332.6Vi + 1 .330V + 4.725mV + 1 9.95mV 
Vi(min) = 4.947mV 
For maximum Vi: 

3.0V = (V, - 4.0mV)( 1 5|| K + 1 ) - 30nA (142.5K) - 

30nA(2K)( l ^| !l + 1) 

3.0V = 272.4Vi-1.090V-4.275mV-16.35mV 
Vi(max) = 15.09mV 



R2 



Figure 5: Offset Voltage and 
Input Biasing Current 



?R1 

4 




o- 

Vos 




i 


i 



Vbatt 
-Ih?lP07 



R4 



Vout 




3-60 



LP07 Series Applications 



Figure 6: Dropout Voltage 



> 

E. 

> 
I 

H 
Z> 

> 



250 



200 



150 



100 



50 



































v OUT = 


= 3.0V j 



























25 



50 75 

II (mA) 



100 



Figure 7: V 0UT vsV |N 



3.0 



O 

& 2.0 



3 
O 
> 



























Rlc 


)AD = 


50£i 












/ 


r— 
















/ 

1 
















/ 


















/ 





















































1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 

V, N (Volts) 



The range for R1 



(20 0mV) = Vi 

ri - R 2 » n R 2 
m - 39.40 10 12.25 

Choosing R1 to be a 2K potentiometer, R2 = (2K)(12.25) = 24.5K. 
R2 should be less than 24.5K so under the worst case conditions, 
R1 would not operate at its maximum value of 2K. R2 is chosen to 
be 22K. The range of R1 is calculated as: 

R1 = 22K(0.95) / 39.4 to 22K(1 .05) / 1 2.25 

R1 =531 ohms to 1.89K ohms 



Measurements 



Actual measurements were recorded and are shown on figures 6 
and 7. Figure 6 shows the dropout voltage at different load 
currents. Figure 7 shows the output voltage regulation versus the 
decrease in battery voltage with a fixed load. 



5V Regulators 



The low dropout 3.0V regulator in figure 1 can be easily modified 
to a 5.0V or adjustable low dropout regulator by changing R1 to a 
5K potentiometer. Using a voltage controlled resistor for R1 will 
allow for a programmable low dropout regulator. 

Conclusion 

Low dropout 3.0V linear voltage regulators are ideal for portable 
battery operated applications to help extend battery life. The low 
dropout voltage allows the battery powered equipment to operate 
at a lower battery voltage. 

In addition to the otheradvantages discussed, MOSFETs increase 
the efficiency of the circuit because of the current required to drive 
the gate is virtually zero as it is usually in the sub nanoampere area. 
Bipolars need base current and this is undesirable especially when 
battery energy is at a budget. LP07 is ideal for linear applications 
requiring high efficiency because of its low threshold voltage and 
low guaranteed on-resistances at 2V, 3V and 5V drives. 



3-61 



©DMOS 
Supertax inC. Application Note 



AN-D15 



Understanding MOSFET Data 



The following outline explains how to read and use Supertex 
MOSFET data sheets. The approach is simple and care has been 
taken to avoid getting lost in a maze of technical jargon. 



The VN01 A data sheet was chosen as an example because this 
is one of the most popular devices and has the largest choice of 
packages. The product nomenclature shown applies only to 
Supertex proprietary products. 



0} Supertex inc. 



Device Structure 

V: Vertical DMOS (discretes & quads) 
D: Vertical Depletion-Mode DMOS 



T: Low threshold vertical 
discretes 

A: Lateral DMOS arrays 

L: Lateral DMOS discretes 



Type of Channel 

• N-Channel, or 

• P-Channel 



Design 

Supertex Family number 



Advanced DMOS Technology 

These enhancement-mode (normally-off) DMOS FET transistors 
utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and negative temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 



VN01A 



Voltage Range 

Suffix Min BV DSS volts 

U: 18 
L: 20, 40 

A: 40, 60, 90, 

C: 160, 200, 240 
D: 350, 400 
E: 450, 500 
F: 550, 600 

• Some A range devices not 
available in 40, 90 & 100V 

• Some C range devices not 
available in 240V 



100 



structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range of 
switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speed are desired. 



This section outlines main features of the product 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV 0SS / 
BVpos 


Rds(on) 
(max) 


(min) 


Order Number / Package 


T0-39 


TO-92 


T0-52 


TO-220 


Quad P-DIP 


Quad C-DIP 


DICE 


40V 


30 


2.0A 


VN0104N2 


VN0104N3 


VN0104N9 


VN0104N5 


VN0104N6 


VN0104N7 


VN0104ND 


60V 


3£2 


2.0A 


VN0106N2 


VN0106N3 


VN0106N9 


VN0106N5 


VN0106N6 


VN0106N7 


VN0106ND 


90V 


3Si 


2.0A 


VN0109N2 


VN0109N3 


VN0109N9 


VNI0109N5 






VN0109ND 



Drain to source breakdown voltage 
& drain to gate breakdown voltage 



Maximum resistance from drain to 
source when device is fully turned on 



Minimum drain current when device 
is fully turned on 



3-62 



Package Options 



Understanding MOSFET Data 



Hermetic metal can 

• Moderate power 
dissipation 

• Industrial/Military 
applications 



Plastic 

• Low power 

• Mainly commerical 
applications 

• Cost effective 



Hermetic metal can 
• Low power Industrial/ 
Military applications 



Plastic 

• High power 

• Commerical/lndustrial 
applications 



Ordering Information 



BV DSS / 
BV MS 


^DS(ON) 

(max) 


'd(ON) 

(min) 


Order Number / Package 


TO-39 


TO-92 


TO-52 


TO-220 


Ouad P-DIP 


Quad C-OIP 


□ICE 


40V 


3£J 


2.0A 


VN0104N2 


VN0104N3 


VN0104N9 


VN0104N5 


VN0104N6 


VN0104N7 


VN0104ND 


60V 


3fl 


2.0A 


VNI0106N2 


VN0106N3 


VN0106N9 


VN0106N5 


VNI0106N6 


VN0106N7 


VN0106ND 


90V 


3d 


2.0A 


VN0109N2 


VNI0109N3 


VN0109N9 


VN0109N5 






VN0109ND 



14-Lead DIP 


14-Lead DIP 




ND: Die in waffle pack 


Dual in line plastic 


Dual in line ceramic 


NW: Die in wafer form 


Die can be visually 


• 4 dice in one package 


• 4 dice in one package for 


• 4 inch diameter wafers 


inspected to commercial 


• Commerical/lndustrial 


Industrial/Military 


• Reject die are inked 


(standard) or military 


applications 


requirements 


visual criteria (specify 
while ordering) 



Extreme conditions a device can be subjected to electrically 
and thermally. Stress in excess of these ratings will usually 
cause permanent damage. 



Ratings given in product summary. 



• Most Supertex FETs are rated for ±20V 

• ± voltage handling capability allows quick turn off by 
reversing bias. 

• External protection should be used when there is a 
possibility of exceeding this rating. Stress exceeding 
±20V will result in gate insulation degradation and even- 
tual failure. 



Absolute Maximum Ratings 



Drain-to Source Voltage 


BV DSS 


Drain-to-Gate 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature 


300°C 




Maximum allowable temperature at lead 


3 while soldering, 


1 .6mm away from case for 10 seconds. 





• All Supertex devices can be stored and operated satisfactorily within these junction 
temperature (T,) limits. 

• Appropriate derating factors from curves and change in parameters due to reduced/ 
elevated temperatures have to be considered when temperature is not 25°C. 

• Operation at T d below maximum limit can enhance operating life. 



3-63 



Understanding MOSFET Data 



Thermal Characteristics 

Device characteristics affecting limits of heat produced and 
removed from device. Die size, R DS( on) and packaging type are 
the main factors determining these thermal limitations. 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 
@ T c = 25°C 


°c/w 


°c/w 


'dr 


'□RM 


TO-39 


0.8A 


2.5A 


3.5W 


125 


35 


0.8A 


2.5A 


TO-92 


0.5A 


2.0A 


LOW 


170 


125 


0.5A 


2.0A 


TO-52 


0.5A 


2.0A 


LOW 


170 


125 


0.5A 


2.0A 


TO-220 


1.5A 


2.5A 


15.0W 


70 


8 


1.5A 


2.5A 


Plastic DIP 
Ceramic DIP 


See DMOS Arrays & Special Functions section 



l D (continuous) 

Maximum continuous current carrying 
capability of device. 

• Depends mainly on: 

A. R DS(0N) - on state resistance 

B. P D - maximum power dissipation for 
package 

C. Die size 

D. Maximum junction temperature 



l D (pulsed) 

Maximum non-continuous pulse current 
carrying capability for a 300 uS 2% duty 
cycle pulsed. 

• Depends mainly on : 

A' R DS(ON) 

B. P D max 

C. Diameter of bonding wire 

D. Die size 

E. Maximum junction temperature 



Power Dissipation 

• Maximum power package can dissipate 
when case temperature is 25°C. 

• When case temperature is higher than 
25°C, use P D vs. T c curve to determine 
dissipation permissible. 



Thermal resistance from junction to air. 

• Depends mainly on package and die size 



Thermal resistance from junction to case. 

• Depends mainly on package and die size 

• To determine T, use equation 
Tj=P D xe, c + T A 



Continuous current handling capability of 
drain to source diode. 

• Factors affecting value same as l D 
(continuous) 



'drm 

300 uS, 2% duty cycle pulsed. Current 
handling capability of drain source diode. 

• Factors affecting this parameter same 
as l D (pulsed) 



3-64 



Electrical Characteristics 



Understanding MOSFET Data 



The following DC parameters are 100% tested with 300nS, 2% duty cycle pulsed at 

25°C, BV DSS , V GS(TH) , l DSS , Id(on) & Rds(ON)- 

• AV GS(TH) and AR DS(ON) are guaranteed by design ie., when device is functional for 
other DC parameters, these two parameters will not deviate from published values. 

• Since a representative sample is adequate to assure consistency of specs, A.C. 
parameters are sample tested on a lot/batch basis. 

• High temperature testing on sample basis when requested with hi-rel processing. 

• Refer to section 3 "power MOS structures" for test circuits used for measurement. 



BV DSS 

• Please see product summary (part I) 

• Positive temperature coefficient. See 
curve BV DSS vs. T,. 



•GSfTH) 

• Voltage required from gate to source to 
turn on device to certain l D current value 
given in "condition" column. 

• l D measurement condition is low for 
small die and higher for larger die. 



AV G srrH) 

• Threshold voltage reduces when 
temperature increases and vice versa. 

• Value at temperature other than 25 °C 
can be determined by V GS(TH) (normal- 
ized) vs. Tj curve. 



• Since the gate is insulated from the rest 
of device by a silicon dioxide insulating 
layer, this parameter depends on thick- 
ness/integrity of layer and size of device. 

■ Measured at maximum permissible 
voltage from gate to source: ±20V. 

1 Values of this parameter are often tens/ 
hundreds of times less than published 
maximum value. Electrical screening is 
done at 100nA since test equipment 
functions slowly at lower values, which is 
not practical for mass production. Con- 
sult factory for screening lower values. 



In 



• This is the leakage current from drain to 
source when device is fully turned off. 

• Measured by applying maximum 
permissible voltage between drain and 
source (BV DSS ) and gate shorted to 
source (V GS = 0) 

■ Special electrical screening possible at 
lower values since max. published 
values are higher to achieve practical 
testing s 



Electrical Characteristics (@ 25?c unless otherwise specified) 



Syn*ol 


Panneer 


u, 


Typ 




IM 




BV W 


Drain- to- Sou roe 
B reak down Vdtage 


VM0109 


90 






V 


V «-°. 'o = ,mA 


VNDI06 


60 


VN0104 


+0 


V «M 


Gate Threshdd Vdege 


OB 




2.4 


V 


V«.= V„, l„= (mA 




Changein V 3#p ^witi Temperature 




-38 


-5.S 




V«.=V„, l = imA 


U 


Gate Body Leakage 






100 


nA 


v a .= ±aov.v ( ,.=o 




ZeoGae VdagePrainCurrent 










V„=0 1 V D .= MaxRa*n9 


fOO 


V a .=0,V e ,= 0.8Max Rating 

T, = t2S"C 




ON-Stae Dam Current 


0.S 


10 




A 


V«=5V,V„=25V 


SO 


2.6 




V <S ,= 10V,V C ,.= 25V 




State Dairy to- Source 
ON-State Fteistance 




30 


s 


A 


V„=SV, l„=250mA 


2.S 


3 


V m= ioV, l D = 1 A 




Change in F^^witi Temperatu e 




07 






V a »= (OV, l„= tA 


Gr- 


Fb wa id T ranscorductance 


3X1 


450 




mtT 


V„ = 25V, t = o.SA 


CW 


Input Capaciwnce 




45 


60 


PF 






Co omen Source OuputCapacitsrce 




ao 


2S 




Reverse Transfer Capacitance 




5 






TurvON Delay Time 




3 


5 




V DO =2SV 
l B =IA 
R ow = 2Sfl 


<■ 


R_-.~ Tirrit- 




S 


6 


V") 


Tun-OFF Delay Time 




6 


9 


\ 


Fal Time 




S 


8 




□ode FswardVdtage Drop 




12 


1£ 


V 


v"«=0, i„ = iO* 




Reverse Recovery Time 




400 






V„ = 0, l^ = tOA 



'd(on) 

• Defined as the minimum drain current when device is turned on. 

• Supertex measures l D(0N) min. at two test conditions: 

V GS = 5V and V GS = 10V, to give the designer a look at both logic 
level turn on and full turn on 

Although Supertex specifies a typical value of 

'd(on)' designer 

should use minimum value as the worst case. 



™DS(0N) 

• Drain to source resistance measured when device is partially 
turned on at V GS = 5V, and fully turned on at V GS = 1 0V. 

• Designers should use maximum values for worst case condition. 

• When better turn on characteristics (ie., low R DS (ON)) is required for 
logic level inputs, Supertax's low threshold TN & TP devices may 
be used. 

• Typical value of R DS (on) can be calculated at various V GS conditions 
by using output characteristics or saturation characteristics family 
of curves (l D vs. V DS ). 

• r dsion) increases with higher drain currents. R ds(0 n) curve has a 
slight slope for low values of l D , but rises rapidly for high values. 



ARds<on) 

• Positive temperature coefficient. 

• Enhances stability due to current sharing during parallel operation. 



Understanding MOSFET Data 



Switching Characteristics 



Extremely fast switching compared to 
bipolar transistors, due to absence of 
minority carrier storage time during 
turn off. 

Switching times depend almost totally 
on interelectrode capacitance, R s 
(source impedance) and R L (load 
impedance) as shown on test circuit. 



Electrical Characteristics (@ 25*c unless otherwise speeded) 



Represents gain of the device and 
can be compared to H FE of a bipolar 
transistor. 

Value is the ratio of change in l D for a 
change in V GS 

G FS = 4^ 
FS AV GS 

Rises rapidly with increasing l D , and 
then becomes constant in the satur- 
ation region. See G FS vs. I D curve. 





PawtiHfer 


Un 




■fax 


Unit 


Cmtttat 


BV D „ 


Drain- tr> Source 
Breakdown Voltage 


VN0IQ9 


30 






V 


V a ,=0, l e = fmA 


VNoios 


GO 


VN0104 


■40 




Gate Threshold Voltage 






2.4 




V .= V„, l D = 1mA 




Cfriangein V a ^, fc) witi Temperature 




■38 


-5.S 






I» 


Gate Body Leakage 






100 


nA 


V„=S20V,Vo. = 


Lm 


Zeo Ga« Vdtage Drain Cu Bent 








M» 


V a ,= 0,V D ,= Max RaUr^ 


100 


V„= 0, V„= o.e Max Ra*ng 
T»= )2S-C 




ON- SO* DainCunent 


0.S 


i a 




A 




20 


2$ 




V o .= 10V,V M =25V 


V, 


State Darv to- Source 
ON-Stae Resistance 




30 


s 




V a .= 5V, l o =2S0mA 


2.S 


3 


V a .= 10V, l D = tA 




Changem Ro^witi Ternperatue 




07 


i 




V„= iOV, l B = (A 


G„ 


fowaidTransconductaixe 


300 


■4 SO 




iy,t_? 


V e . = 25V,t = 0.SA 


<W 


Input Capaci Bre e 




45 


60 


pF 




0„ 


Oommcn Source Output Capaci Urce 




20 


2S 


Ch« 


Reverse Transfer Capacitarte 




5 


8 




Tun-ON Delay Time 




3 






v DD =asv 

H wtH = ZSQ. 


\ 


HseTime 




S 


8 




Tgn-OFF Delay Time 




6 


9 


\ 


Fal Time 






S 


%m 


HcdeFo ward voltage Prep 






15 


V 


^♦=0,^=1 OA 


\. 


Reverse Recovery Time 




400 




ns 


V„= 0,1^=4 OA 



C|SS> Crss> Coss 

• Please see section 3 in Databook "Power MOSFET 
Electrical Performance" for interelectrode capaci- 
tances and equivalent circuit. 

• Supertex interdigitated structures have lowest C lss in 
the industry for comparable die sizes and exhibit 
excellent switching characteristics. 

• Values of these capacitances are high at low voltages 
across them. Please see capacitance vs V DS curves 
for details. 

• Negligible effect of temperature on capacitances. 

• The following equation may be used for calculating 
effective value of C, ss with "Miller Effect." 

Ciss = ^gs + O+Gfs Rl) *-"GD 



1 d(ON) 

During this period, the drive circuit charges C, ss up to 
V GS(TH) . Since no drain current flows prior to turn on, V DS 
and consequently C ]ss remain constant. Region I on the 
V GS vs. Q G curve shows linear change in voltage with 
increasing Q G . 



Gate Drive Dynamic Characteristics 





DRAIN 
C GD 1 










— C DS 


GATE 












SOURCE 


Ciss = 


Cgd + C GS 






Coss = 








Crss = 


c GD 







I 























vp 


S = 


























v DS 


= 4C 


V - 
















1 


— 


— 


-III 



















































































































0.2 0.4 0.6 0.8 1.0 

Q G (nanocoulombs) 



Switching Characteristics (continued) 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 




Un 




■fat 


Unit 


Conditions 


BV D<W 


Drairv to- Source 


VKXCS 


90 












Brea kdoun Vdta ge 










v 


« 


— 1 




VN01O4 


40 










a * fK> , 


GateThieshddVdsge 


08 




2 4 


v 


V«= V^,!,, = imA 


^ 


Oi»ngein V^^witi Temperaure 




38 


-55 


mW*C 


V„=V„, l D =tmA 


La 


■Sale Body Lsiksge 






too 


nA 


V„= = 20V,V M =0 


u. 


ZeoGae v/dtage DramCuirer* 






— 




V„=D,V D ,= Max Baling 










(00 


uA 


v ol =0,V [1( =0? M a >: Rating 
T A = 12S-0 


Id(CM| 


OK-Sta«0ain Current 




0.S 


to 






V a ,= SV,V„, = 2SV 








20 


a.5 




A 


v„= iov,v D8 =a5V 




State Deavto-Souioe 






30 


s 




V w = 5V, [p = 250mA 




CN-Stae Resistance 






2 £ 


3 


A 


icv. I D = iA 




Changein F^cqwiti Temperate 




C 7 


* 




V«= lOV.ts iA 




FowardT ranstcrtluctance 


300 


490 




mv 


V [> .= 2SV,t = 0SA 


CU 


Input Capacifince 




■45 


6D 








Commm S:.'jri:-i=;-:'ijifi'j"I'-sp5i;iBnce 




ao 


as 


PF 




cw 


Reverse Transfer Capaeiiarce 




s 


e 








Tun-ON Delay Time 




3 


s 






t. 


Hse Tims 




S 


3 




V PC> =2SV 

I B =IA 




Tui>OFF May Time 




6 


3 




\ 


Fal Time 




5 


8 




v. 


DJOdeFowardVdtageDicp 




12 


fS 


V 


v„=o, l„=10A 




Reverse Recovery Time 




400 




ns 


V„=0, l„=iOA 



• When C 1SS is driven to a voltage exceeding V GS(TH) , conduction 
from drain source begins. G FS increases causing increase in C, ss 
due to "Miller Effect" Charge requirements to Region II increase 
considerably. Gain stabilizes in Region III and "Miller Effect" is 
nullified, resulting in a linear change in V GS for increase in Q G . 



td(OFF) 

• The sequence of events now begins to reverse. C, ss discharges 
through R GEN . The rise of V DS is initially slowed by increase of 
output capacitance. 



tf 






• V DS ris 


3S as the load resistor 


charges the output capacitance. 



V SD 

• This is the forward voltage drop of the parasitic diode between 
drain and source. 

• Diode my be used as a commutator in H bridge configurations 
or in a synchronous rectifier mode. Excessive fly back voltages 
may be clamped by this diode in a totem pole configuration. 









• The reverse recovery time is the time needed for the carrier 




gradient, formed during forward biasing, to be depleted when the 




biasing is reversed. 




• An external fast recovery diode may be connected from drain to 




source to improve recovery time. 



3-67 



jfy Super tex inc. 



LND1 Series 
Application Note 

AN-D16 



Constant Current Sources 

Depletion-mode MOSFETs can be used either as "normally closed" 
switches or current sources. This note shows circuits, utilizing 
depletion mode devices, that will benefit many applications. The 
main performance features of the circuits and examples of 



and Depletion-Mode FETs 

applications are listed. For more applications information on 
depletion mode MOSFETs, refer to other LND1 and DN25 series 
application notes. 



High Voltage Protected 



o-tx- 



LND150N3 



tl 



RX5RA30AX = 



-oV 0UT = 3.0V 



□ ±500V transient protection 

□ +5 to +500V operation 

□ Typically 800nA quiescent current 

□ See application note AN-D17 for details 

Telecommunication, automotive, fax machines, off-line control 
circuits 



Zero Bias Amplifier 




+500V 




OUT 

i LND150N3 



r 



V OUT- V DD" 



G FS R D w 

1+G FS R S * 



□ Very high input impedance 

□ Large output swing 

Instrumentation amplifier for sensors/transducers 



Switchable Bleed Resistor 



High Voltage 
Regulator 



-10Vo- 



100K< 



T " v OUT 

=j= C 500VDC 



LND150N3 



□ 500V operation 

□ Saves power 

High voltage power supply, lab equipment 



Off-Line Trickle Charger 




□ Suitable for single or multiple cells 

□ High compliance voltage 

Hard-wired smoke alarms, burglar alarms, security systems 



Off-Line Voltage Reference 




o 3.0V 



□ Universal input 

□ Resistor values determine voltage references 

□ See application note AN-D1 for details 
Instrumentation, VCRs, televisions, ATEs 



LND1 Series Applications 

High Voltage Ramp Generator 



500V 

_h 



LND150N3 



_U T oV OUT 




3.3K 



; VN0550N3 



□ High linearity 

□ Adjustable slope 

□ See application note AN-D12 for details 

Piezo transducer drivers, measuring instruments, soft start 
controls 



High Voltage Protection 



Probe 




LND150N8 



— 1 $ LND150N8 



Probe 



Measuring 
Instrument 



□ ±500V protection 

□ Stack for ±1 000V or higher 

□ Current limiter 

□ See application note AN-D1 1 for details 

Handheld meters, lab instruments, data communication lines, 
resettable fuses 



High Voltage High Gain Amplifier 




—i A LND150N3 



^V n 



VN0550N3 



□ High input impedance 

□ Up to 500 V operation 

□ Over 60dB gain 

High voltage linear regulators, instrumentation amplifiers, piezo 
transducer drivers 



3-69 



High Voltage Off-Line Linear Regulator 



by Jimes Lei, Applications Engineer 



Introduction 

There are many applications for small, linear voltage regulators 
that operate from high input voltages. They are ideally suited for 
powering CMOS ICs, small analog circuits, and other loads 
requiring low current. These circuits can be used in several 
applications requiring power directly from the utility line. They can 
also be used for applications which either have very wide input 
voltage variations or environments with high voltage spikes; for 
example, telecommunications, automotive, and avionics. This 
application note discusses several circuits which will benefit these 
applications. 

Direct off-line applications require operation at 1 20VAC to 240VAC 
which corresponds to maximum peak voltages of ±340V. Applica- 
tions in telecommunications, automotive, and avionics require 
immunity against very fast, high voltage transients. In telecommu- 
nications, the high voltage transients are caused by lightning or 
spurious radiations. I n automotive and avionics they are caused by 
inductive loads such as ignition coils and electrical motors. Inter- 
national Standards Organization specification ISO/TR7637, for 
electrical interference by conduction and coupling in automobiles, 
shows that transients up to -300V and +120V can be generated 
due to various inductive loads 

In addition to the ability to withstand high voltages, many circuits 
used for the above mentioned applications also require low 
quiescent current. The low quiescent current is required to mini- 
mize power dissipation in these linear regulators. Many telecom- 
munication applications require very low quiescent current be- 
cause there are limitations to the allowable current that can be 
drawn from the telephone lines. Automotive and avionics applica- 
tions require low quiescent current to minimize the loading on 
batteries, especially when the vehicles are not in use for long 
periods of time. Forexample, only afew microamperes are needed 
for powering memory ICs. In such situations the quiescent current 
of the regulator should be within a few microamperes. 

The high voltage protected, 5.0V linear regulator shown in Figure 
1 meets all of the above requirements. It is very simple, compact 



IN4005 

HV IN(>t>H ^ 

D =LC 



LND150N8 




RH5RA50AA 



:5.0V 



C 2 =J=0.01nF C-, =j=0.01uF 



Figure 1 : High Voltage Universal 
Off-Line Linear Regulator 



and inexpensive. The high operating voltage and high transient 
voltage protection are achieved by using Supertex part #LND1 50N8 
inconjunction witha5.0V linear regulator, Ricoh part#RH5RA50AA. 



Circuit Description 



The LND150N8 is a 500V, N-channel, depletion-mode MOSFET. 
It has a maximum R DSlONI of 1 .OKohm, V GS(OFF) of -1 .0V to -3.0V, and 
an l DSS of 1 .0mA to 3.0mA. The RH5RA50AA is a 5.0V ±2.5% 
voltage regulator with a maximum quiescent current of 1 .Onamp. 
Both these parts are available in the SOT-89 (TO-243AA) surface 
mount package. 

The high voltage input, HV IN , is connected to the anode of diode D. 
The cathode of the diode is connected to the drain of the LND 1 . The 
diode is used as protection against negative transient voltages and 
as a half-wave rectifier for off-line application. The LND1 is 
connected in the source follower configuration, with its gate 
connected to the output, V OUT , and its source to the input of the 5.0V 
regulator, V !N . Capacitors C,, C 2 and C 3 are bypass capacitors. C 3 
is required when HV IN is negative, such as during the negative half 
cycle of an AC line, or negative transients. The proper value of C 3 
is chosen based on the worst case duration and duty cycle of the 
negative pulses on HV IN . 

HV (N , V IN and V OUT are at 0V before a voltage is applied to HV IN . The 
LND1 is turned on when its gate-to-source voltage, V GS = 0V. Once 
a voltage is applied to HV ]N , current will flow through the diode and 
the "normally on" channel of the LND1 charging capacitor C 2 . The 
voltage across C 2 is connected to V IN . As V IN starts to increase, V 0UT 
will also continue to increase until it reaches its regulated voltage 
of 5.0V. 

The LND1 is configured as a source follower with its gate con- 
nected to a fixed 5.0V value (nominal). The voltage on the source, 
V 1N , will follow the voltage on its gate, minus V GS . V, N = V^ -V GS 
where V Gs is the voltage required to supply the input current l IN . If 
500VDC is applied on HV IN , V OUT will remain at 5.0V and V IN should 
be between 6V to 8V, since V GsfOFF1 of LND1 50N8 is guaranteed to 
be -1 V to -3V volts. The actual observed value was 6.26V. 

The dropout voltage, (V IN -V 0UT ), for the 5.0V regulator with a 
1.0mA load is rated as 30mV. To maintain regulation, V IN must be 
equal to or greater than 5.03V. As l IN increases, V IN decreases and 
thereby increases the gate-to-source voltage on the LND1 to meet 
the l IN requirement. The transfer characteristics of the LND1 gives 
a good indication of V GS vs. I IN . 



Advantages of the LND1 

The important parameters of the LND1 are its 500V breakdown 
voltage, 1 .5pF output capacitance and 1 .OMohm dynamic output 



3-70 



LND1 Series Applications 



impedance. Supertex utilizes a proprietary design and fabrication 
process to achieve very flat output characteristics which gives this 
device its very high dynamic impedance, r D . The RH5RA50AA has 
an absolute maximum input voltage rating of 13.5V. The high 
breakdown voltage of the LND1 extends the maximum input 
operating voltage range from 13.5V to 500V. The low output 
capacitance and high dynamic impedance prevent the input 
voltage of the RH5RA50AA from exceeding its absolute maximum 
value of 1 3.5V when very fast high voltage transients are present. 
The ripple rejection ratio is also improved by several orders of 
magnitude. 

LND1 improves the performance of the 5.0V linear regulator in the 
areas listed below. Observations and measurements were taken 
under three different loading conditions: no load, 10Kohm, and 
5.0Kohm. 

a) DC operation extended from 13.5V to 500V 

b) High voltage transient protection 

c) Greatly improved ripple rejection ratio 

d) Eliminates power-up transients 



DC Operation 



The LND1 increases the maximum operating voltage range from 
1 3.5VDC to 500VDC. In orderforthe output to maintain regulation, 
the voltage difference (V, N -V 0UT ), must be greater than the regulator's 
specified dropout voltage of 30mV at 1 ,0mA load current. The 
measurements are shown below. 



HV |N 




v IN 


V 

OUT 


Conditions 


10V to 500V 


770nA 


6.26V 


5.02V 


No load 


10V to 500V 


503uA 


5.56V 


5.02V 


10Kohm 


10V to 500V 


1.0mA 


5.30V 


5.02V 


5.0Kohm 



Since the LND1 50N8 is connected in a source follower configura- 
tion, the value of V, N can be estimated as shown in Figure 2. 



High Voltage Transient Protection 

Positive and negative transient voltages were applied on HV, N . The 
positive transient voltages are blocked by the LND1 and the 




\ V GS(OFF) / 



Id = bss 

VgS = V OUT - V IN 



- V|n v, N = v OUT -v GS(OFF) (i-^ g ) 



Figure 2: V IN Calculation 



negative transient voltages are blocked by the 1 N4005 diode, 
which has a 600V PIV rating. 

Figure 3 shows the test conditions used for simulating transient 
voltages. Positive 300V pulses with a pulse width of 500nsec, a 
rise time of 1 0nsec, and a duty cycle of 1 .0% are superimposed on 
the 1 0VDC line of HV IN . Figures 4a and 4b are waveforms showing 
HV 1N ,V IN andV ou1 . 

The low drain-to-source capacitance, C os = C^ - C^ = 1 .5pF, 
and high dynamic output impedance, r D = 1 .OMohm, of the LND1 
inherently give the LND1 excellentfrequency response. The LND1 
configured as a source follower will effectively protect high voltage 



HV INl 



LND1 



H v IN 






V OUT 


REG 










J0.01u.f|o.01u.F = 


L° 1 1 



>5K£2 



310V 
HV IN 
10V 



500nsec 



-50usec- 



-ii- 



t B = 1 0nsec 
Figure 3: Positive Transient Test Condition 




Figure 4a: HV IN and V lK 



HV IN = 
31 0V 




Figure 4b: HV IN and V 



3-71 



LND1 Series Applications 



HV IN 



'oi C DS 4= 15 P F 



C 2 =L 0.01 uF 



r Q = AC resistance, typically 1 .0M£2 
(almost no effect on V, N ) 

/ 300V \ 



«d = C, 



AV lN = 



=1-5Pf(i 



10nsec J 
I'dt (45mA) (10nsec) 



45mA 



C 2 _ 0.01 hF 
AV| N = 45mV PEAK 

Figure 5: Estimate V IN Increase due to Transients 



transients on HV IN from affecting V lN . The only paths for transient 
voltages to get into V IN are through the 1 .5pF C DS or 1 .OMohm r . 
Any transient voltages that pass through will be further attenuated 
by C 2 . The increase in V IN caused by the transient voltage can be 
estimated with the equivalent circuit shown in Figure 5. 

Negative 300V pulses with a pulse width of 500nsec, a rise time of 
1 0nsec, and a duty cycle of 1 .0% are superimposed on the 1 0VDC 
line of HV IN . The 1 N4005 diode is reverse biased and blocks the 
negative voltage. Figures 6a and 6b are waveforms showing HV IN , 
V, N , and V OUT . 

The LND1 with the 1 N4005 effectively protects the input of the 5.0V 
regulator from positive and negative transient voltages. Theoreti- 
cal and measured values indicated V 1N will never exceed its 
maximum rating of 13.5V. 



Ripple Rejection Ratio 

The ripple rejection ratio, RR, demonstrates the LND150N8's 
capability of filtering AC ripple on the input of HV IN . A 4.0V P . P , 
1 .0MHz sinusoidal signal was applied to the 5.0V regulator with 
and without the LND1 . Figure 7 shows the test conditions. 




V IN = HV| N = 9.0VDC + 2.0SIN27tftV 
f = 1.0MHz 



C 2 ^0.01nF^| d 



VQUT 



0.01U.F 



Vreg 


VOUT 


1 

; Jo.oiuf: 




C 



Figure 7: Ripple Rejection Test Conditions 



Measured results are as follows: 

Peak-to-peak output AC voltage, RR = 20log 



OUT 

4.0V I 



V OUT with LND1 


V OUT without LND1 


Conditions 


1 .3mV, RR = -70dB 


2.90V, RR = -2.8dB 


No load 


1.3mV, RR = -70dB 


2.90V, RR = -2.8dB 


10Kohm 


1.3mV, RR = -70dB 


2.90V, RR = -2.8dB 


5.0Kohm 



The amount of AC attenuation due to the LND1 can be estimated 
by the equivalent circuit and equations shown in Figure 8. 

The ripple rejection ratio was improved by a factor of 1 000. Such 
a high ripple rejection ratio is particularly useful for off-line applica- 
tions. A typical 240VAC off-line application is shown in Figure 9a. 



HV IK 



-tx- 



C DsT 1.5pF 

V, N K) 2SIN2rcftv 

-Vf=1-0MHz c =1 001rF 



-o V, N 



HV,k 



Figure 8: Ripple 

Rejection 

Calculation 



V 'N-C DS + C 2 

1.5pF 
V|N_ 1.5pF + 0.01uF 

V IN = 600uV P .p 



(4.0Vp. P ) 



HV, 



10V 



V IN = 
5.4V 



■ 




mm 


2 




■ 








IWHS 








i 


s 














■ 
u 


- 






■ ■ 














L 














IV 
















Figure 6a: HV IN and V IN 



-300V 

■ 

Figure 6b: HV IN and V 0UT 



LND1 Series Applications 



IN4005 

r-W 



0.04u.F=j=C 3 



HV IN (^O 240 VAC 



T 



Vreg 



0.01 uF jC 2 



0.01uF 

Figure 9a: 240VAC Off-Line 5.0V Regulator 



R L <5K 



Figure 9b shows the voltage waveforms at the drain, V DRAIN , of the 
LN D1 and the AC voltage at V our There were 290 Volts of AC ripple 
observed on V DnA1N with less than 2.0millivolts of ripples on V 0UT . 

C 3 is a high voltage holding capacitor. In order to minimize size and 
cost, more often than not it is desirable to select C 3 to be as small 
as possible. The high ripple rejection ratio helps in achieving a 
small size of C 3 because it allows for large AC input voltage with 
negligible AC output voltage. 



Power-Up Transient Suppression 

The circuits shown in Figures 1 0a and 1 0b are powered up from 0V 
to 1 0V in 1 0Onsec. This test demonstrates the stability of the circuit, 
the amount of overshoot voltage on V OUT , and the amount of time 
required for the output to settle. Large overshoot voltages on V OUT 
may damage sensitive loads, such as CMOS circuits. 

The test results were: 




IS Hw 



Figure 9b: V DRAIN and 



With LND1 


Without LND1 


Conditions 


V t 

PEAK \ 


V t 

PEAK r 


0.0V 50|isec 


7.6V 1 .Onsec 


No load 


0.0V 60|jsec 


7.0V 1 .0nsec 


10Kohm 


0.0V 80|isec 


6.9V 1 .0|jsec 


5.0Kohm 



While there was a large overshoot voltage without the LND1 , no 
overshoots were observed in the circuit employing the LND1. 
Loads prone to damage by overshoots can be effectively protected 
by using the LND1. 



Conclusion 

The high voltage protected, low power, 5.0V linear regulator in 
Figure 1 is a robust, compact, cost effective regulator. It can 
operate up to 500VDC, protect against ±500V transients, and has 
a maximum quiescent current of 1 .Onamp. The electrical charac- 
teristics of the LND1 allow for the 500V operation and protection. 
Some examples are proximity controlled light switches, street 
lamp control, fax machines, modems, and power supplies for 
CMOS ICs in automotive, avionics and a variety of applications. 



Other Application Ideas 

The circuit in Figure 1 can be easily modified for higher current 
capability. The LND1 can be replaced by the Supertex DN2540N5, 
which is a 400V, 150mA depletion-mode MOSFET in a TO-220 
package. In case the current is low and the worst case power 
dissipation for the DN25 is below 1 Watt, the TO-92 version (part 
#DN2540N3) can be used to save space and cost. Figure 11 
utilizes an op-amp and an enhancement-mode MOSFET for a 
much higher output current capability. Figure 1 2 is an off-line street 
lamp control where V SENSE is the input voltage from a light sensing 
device. 




REG 



-2J_ 



0.01|iF^[ 



0.01uF 



REG | j ,oul i 

I C 4°-°^ F |r l 



10V 



HV| N ov / - t r = IQOnsec 



10V 



5V- 
Vout 0V 



tr 

Figure 10a: Power Up Response with LND1 



V IN ov / - tr = IQOnsec 



V>EAK 

5V 

Voirr 0V 



Figure 10b: Power Up Response without LND1 



3-73 



LND1 Series Applications 



HV, 



'N— W- 



3 ,4 LND150N3 



RH5RA50AA 



~" 2 I 



I 4 



5.0V 



Max 
406 



. VN0340N5 

-O V OUT =VsET 



Figure 11: High Output Current Linear Regulator 



-4 J 



i 

1 120VAC 



->2 V 



3 4 LND150 



RH5RA50AA 



C 2 j 



5.0V 



V SENSE 
O 



VN0640N5 
Max406 



Ri R2 



Figure 12: Off-Line Street Lamp Controller 



C 4 ± 



Lamp 



3-74 



DN25 Series 
Application Note 

AN-D18 



Constant Current Sources and Depletion-Mode FETs 



Depletion-mode MOSFETs can be used either as "normally closed" 
switches or current sources. This note shows circuits, utilizing 
depletion mode devices, that will benefit many applications. The 
main performance features of the circuits and examples of 



applications are listed. For more applications information on 
depletion mode MOSFETs, refer to other LND1 and DN25 series 
application notes. 



Current Surge Protection 




□ Current limit up to 1 50mA 

□ Back-to-back pair for bi-directional limiting 

Inrush limiting for lamps/motors/capacitive loads, instrumen- 
tation, telecommunication 



High Voltage Protected Regulator 



o-W- 



DN2540N8 2i - 



RX5RA30AX 



kjV out = 3.0V 



□ ±400V transient protection 

□ +5V to +400V operation 

□ Typically 800nA quiescent current 

Telecommunication, automotive, fax machines, off-line control 
circuits 



Solid State Relay 




n Normally on 

□ ±400V blocking 

□ Low C, N for fast switching 

Telecommunication, instrumentation, fax machines, modems, 
data line diagnostics 



SMPS Start-Up 




DC -DC 
Converter 



-Kr- 



□ Off-line capability 

□ Switchable to save power 

□ Improves efficiency 
Switchmode power supply 



312V 



3-75 



HT01 

inCm Application Note 

AN-D19 



Translator for 

by Jimes Lei, Applications Engineer 



Introduction 

The Supertex HT0130 is a 300V 8-channel high voltage level 
translator designed to drive and control the gates of eight indepen- 
dent high voltage P-channel MOSFETs via low voltage CMOS logic 
control signals. A logic low on one of the inputs of the HT01 will 
cause the corresponding outputto drop typically 1 4V below the high 
voltage rail, which is used to safely turn on an external P-channel 
MOSFET with -1 4V gate-to-source voltage. A typical application 
of the HT01 being used in a full H-bridge high voltage DC motor 
controller for tape drives, utilizing several DC motors, is shown in 
Figure 1 . The major advantages of the HT01 over existing level 
translation approaches are the ease in design, the reduction of 
discrete components and the ability to operate at DC levels. 

The advantage of high voltage DC motors over lower voltage DC 
motors is that they require less current for the same mechanical 
output. Although their operating voltage is higher, the total input 
power is approximately the same. The lower current operation is 
advantageous to minimize the power dissipated across the driver 



transistor due to reduced l 2 R 



DS(ON) 



losses. The output drivers 



therefore need not have low on-resistance. 

Circuit Description 

The DC motor shown in Figure 1 is used for industrial tape drives. 
A full H-bridge configuration is required for bi-directional capability 
used fortape rewinding and forwarding. The full H-bridge consists 
of the Supertex TQ3001 N6 low threshold complementary quad (vi- 
and P-channel MOSFETs operating from a 35V line. The N-channel 
transistors are low threshold MOSFETs and can be driven directly 
from 5.0V logic. 

A logic low signal at the input of the HT01 will turn on the P-channel 
transistors by driving the gate to the positive rail minus the 



guaranteed clamp voltage of the device, V PP -V 2 . The N-channel 
transistors are driven directly from the CMOS logic. 

To forward wind the tape, P1 and N2 are on and P2 and N1 are off. 
To rewind, P2 and N1 are on and P1 and N2 are off. To brake, N1 
and N2 are on and P1 and P2 are off. The logic truth table showing 
the different states is as follows: 

Truth Table 



Logic 


MOSFETs 


Motor 
Status 


A 


B 


c 


D 


P1 


N1 


P2 


N2 








1 


1 


On 


Off 


Off 


On 


Forward 


1 


1 








Off 


On 


On 


Off 


Rewind 


1 


1 


1 


1 


Off 


On 


Off 


On 


Brake 


1 





1 





Off 


Off 


Off 


Off 


Coast 



It is desirable to brake the motor during transitions between 
forwarding and rewinding. This will avoid stretching and possibly 
breaking the tape. Braking between transitions will also eliminate 
the possibility of having both transistors on the same leg "on," 
thereby shorting the V PP line to ground creating high crossover 
current. 



Advantages in Using the HT01 

The designer can choose from many different techniques for high 
voltage high side P-channel drivers. They all, however, require a 
fair amount of external components per driver. Bootstrapping, 
charge pumps, optocouplers, floating power supplies and pulse 



5.0V 
A O 



1 



35V 



/a HT01 | 1 



— 



T P1 P2 J 

— 00X1— 



B O- 



h |m N2T 



| 1 V 8 HT01 



-O C 



VOUT2 



-O D 



Figure 1 : H-Bridge Motor Driver 



3-76 



HT01 Applications 



V DD = 5.0V 



5.0V 

ov 



' DD = =■< 



Input 
Logic 



V NN = GND 



V PP = 35V 



200uA i 



Vout 

— o 



'SINK 



300uA 



35V 

5.0V 



1/8 HT01 



Vout 



Figure 2: 1 of 8 HT01 Output 



transformers are a few examples. The HT01 , which is available in 
a single 20 pin DIP will drive eight independent P-channel MOSFETs 
with no external components required. Applications for this device 
include motor drivers, solenoid drivers, and high side DC switches. 
The HT01 will also operate with a DC input to keep the P-channel 
MOSFET continuously "on" as required in this application. Other 
techniques such as the use of bootstrapping capacitors and pulsed 
transformers cannot operate at DC because these schemes 
require periodic charging. 

The HT01 is guaranteed to operate at logic levels from 4.75V to 
15.0V, making it compatible with both TTL and CMOS logic. The 
outputs are designed with constant current sources that can sink 
and source 100|xamps and 200namps, respectively. The outputs 
can be easily paralleled for higher current capability. Output 
voltages will swing from V PP to V PP -V Z where V z is guaranteed to 
be between 11V min and 17V max when V PP is between 12V to 
275V. 



HT01 Output 



The HT01 outputs are designed to drive capacitive loads. A 
simplified internal schematic of 1 of 8 HT01 output is shown in 
Figure 2. 1, and l 2 are constant current sources. A logic low on V, N 
will close switch S. I 2 will sink 300namps to V NN and is equal to 
i i +i z +i sink- v out is therefore discharged by l slNK to V PP -V Z . A logic 



high on V, N will open switch S. I 2 will have no current path to V NN 
and therefore will appear effectively as a series resistor with the 
opened switch S.I, will charge V 0UT to V PP with a constant current 
of 200namps. As V 0UT charges close to V PP , I, will effectively 
appear as a resistor between V 0UT and V PP 

HT01 Switching Speed 

The switching speed will depend on the input capacitance of the 
MOSFETs driving the motor. The following explains various factors 
to be considered in orderto understand the charging and discharg- 
ing requirements of the input capacitance. The calculated values 
are based on a single channel driving the P-channel MOSFET of 
the TQ3001N6. Faster switching speeds can be obtained by 
connecting multiple HT01 outputs in parallel. 

During the forward mode, the HT01 will try to discharge the gate 
of P1 to V PP -V Z = 22V through a constant current sink of 1 OOnamps. 
The gate-to-drain, C GD , and gate-to-source, C GS , capacitances will 
start to discharge to 22V. As the voltage on the gate reaches the 
threshold of the device, the device will start to turn on and the 
voltage on the drain will increase to V PP This will cause the voltage 
on the gate V g to increase due to the capacitive coupling of C GD . 
This results in a plateau on the gate of P1 . 

This additional discharging of C GD is often referred to as Miller 
effect. Once V OUT1 reaches 35V, the gate will continue to discharge 



100ua ©, 

J_ISINK 



35V 



OFF , 



ON 




VOUTI 



35V 

Vg 
22V 

35VX 
Vout 
0V 



in 



Figure 3: Gate Voltage Waveform 



t, t 2 t 3 



3-77 



Region I: The output of the HT01 discharges the C| SS of the 
P-channel MOSFET to its threshold voltage. This estimates the 
delay time of V 0Lrr . 

I = C^-; C ISS = C GS + C SD at V DS = -35V 



dVos = -km = -JQMl = .! 05V/usec 

dt Ciss 95pF 
, _ Vcstth) _ -2.0V 

1 dV GS /dt -1.05V /usee' 



: 1 .9usec 



Region II: The output of the HT02 discharges the C RSS of the 
P-channel MOSFET by 35V. This estimates the rise time of V 0UT . 

I = ; C RSS = C G0 at V DS = -35V to 0V 

dl = C R ss-dV = (60pF)(-35V) = 2 
-Isink -100uA 

t 2 = t, + dt = 22.9usec 



35V 



0V 





■J 




■ 






■ 
















■ 




















— 










— 






— 


— 








































_ 



















i = u-^-; u = C ISS at V DS = 0V 



dV, 



dt 



_gs = -'sink = -100"A 
dt C| SS 310pF 

Vz - VGs('h) -13V -(-2V) 
-0.32usec 



dV GS /dt 
t 3 = t 2 + dt = 57.3usec 



-0.32V/usec 

= 34.4u.sec 



Figure 4 is an oscilloscope picture showing the voltage waveforms 
of the gate of P1 and V 0UT 1 to the motor during startup. Figure 5 
shows the amount of inrush current, 1 .2A into the motor during 
startup. The RPM of the motor will start to increase until it reaches 
6000 RPM at no load. The DC current drawn by the motor is only 
11.0mA. 

The continuous total power dissipation on the TQ3001 N6 for a no 
load condition is (11 .0mA) 2 • (1 .5 + 2.0) = 424uW. The total peak 
power dissipation is (1 .2A) 2 • (1 .5 + 2.0) = 5.04W. The 1 .2A peak 
is below the pulsed current rating of the TQ3001 N6 which is 3. OA 
for both the N- and P-channels. 

Figure 6 shows the gate of P1 and V 0UT1 during turn-off. Because 
the back EMF holds V 0UT1 to 35V, there is very little Miller effect on 




Figure 4: Output Voltage During Startup 



Figure 5: Peak Current During Startup 











: 








SuS 










35V — 


JtC • - 


.... 






















_J 


/ 




















22V — 
35V — 


-/ 














-t-H-t- 
















: 






mmm 






VoUT 




















































10V 






: 














uv 



Figure 6: Output Voltage During Coasting 




Figure 7: Output Current During Braking 



3-78 



the gate. The gate voltage plateaus for only 2 to 3usec. Figure 7 
shows the gates of P1 and N1 and the current through the motor 
when it is braking. Both N1 and N2 are on for 300ms discharging 
the energy stored in the motor to ground. The peak current 
measured was 1 ,2A. 



Other Applications 



The HT01 can also be used for solenoid drivers and high side 
switches for power management. Figure 8 is an example to show 
the ease of using the HT01 for multiple loads. It is being used as 
four separate high side switches and four separate solenoid 
drivers controlled by 5.0V logic signals. 

Depending on the number of loads to be driven, one could use 
either an eight-channel array (e.g., Supertex part #AP0130NA or 
AP0132WG) or discrete MOSFETs (e.g., VP05, VP06, or VP03 
products) available in various packages. 

Conclusion 

The HT01 simplifies gate driver designs on high voltage P-channel 
MOSFETs. Eight independent channels are available in a single 20 
pin package. A considerable amount of board space can be saved 
as compared to discrete approaches. Its wide operating high 
voltage and logic voltage operating ranges allow for easy logic 
interfacing with high voltage P-channel driver applications up to 
275V. 

The outputs can be connected in parallel for faster switching 
speeds for the output MOSFET. 

The HT01 can operate even when the control signal is held 
constant at a DC level, i.e., a static condition. It does not have the 
disadvantage of other capacitively or inductively coupled schemes, 
where the control signal has to vary with time. 



HT01 Applications 



20, 



f ^ 
2 . 6 



p 



JO 



HT01 



'1 

'3 o 6 
U 

Is °> 
'7 



v NN ° f 



IX" 



19 



13 



17 



16 



15 



14 



12 



11 



4S? 



nr } n 

J~ Q 1 ^ R LOAD1 



JQ 2 ]» 



j4 



LOAD2 



JQ 3 ^ 



LOAD3 



"TUT > „ 

_r° 4 I l 




L 4 



Figure 8: High Side Switches and Solenoid Drivers 



3-79 



Non-Impact Printing 
Application Note 

AN-H20 



HVCMOS Drivers for Non-Impact Printing 

by Frank Yang, Applications Engineer 



This article discusses the use of monolithic high voltage ICs for 
non-impact printing and plotting applications. Supertex's HVCMOS® 
process technology allows combining low voltage logic as well as 
high voltage DMOS outputs up to 400V on one monolithic IC. The 
principle of operation for inkjet and electrostatic printing/plotting is 
also described briefly. 



expulsion of droplets from the nozzle is controlled by an internal 
change in pressure caused by a piezoelectric transducer. 



Inkjet Printing 



The inkjet printing industry has grown dramatically in recent years 
because of the low cost and improved quality. There are two basic 
types of inkjet printing technologies: Continuous and Drop-on- 
Demand, though there are several variations. Both systems, under 
electronic digital control, "paint" the images on a substrate using 
carefully formulated and controlled jet droplets. 

The continuous method in Figure 1 directs the flight of charged ink 
droplets to the receptor substrate, e.g., paper. 

In the drop-on-demand method, however, ink droplets are ejected 
from the nozzle only as required; no circulation system is needed. 
Figure 2 shows a drop-on-demand inkjet printing method. The 



Ink 
Supply 



Depletion 
Plate 

Charge 

, ,Pum P Pla,e 
Filter 



Ink Reservoir 




Figure 1 : Continuous Method 



Ink 
Supply 

Ink Reservoir 




Piezoelectric 
Transducers 



Figure 2: Drop-on-Demand 



POL o- 
BL o- 



Latch Enable o- 



J \OA < 



Clock 



DIR 



64 bit 
Static Shift 
Register 



64 Latches 




to 



HV 0UT 1 



HV 0U t2 



60 Additional 
Outputs 




-O D IOB 



Figure 3: HV34 Functional Block Diagram 



3-80 



Non-Impact Printing Applications 



High Voltage Drivers 
for Inkjet Printers 

Supertex HV34, which was designed for driving the deflection 
plates to control the path of charged ink particles, can help optimize 
performance and cost. 

The HV34 is a low voltage serial input to high voltage parallel 
output converter with 64 push-pull outputs at up to 1 80V. Figure 3 
shows a functional block diagram of the HV34. This device 
consists of a 64-bit shift register, 64 latches, and control logic to 
perform the polarity select and blanking of the outputs. A DIR pin 
controls the direction of the data shift through the device. Data 
output buffers are provided for cascading multiple devices. The low 
voltage logic section of the H V34 can be operated either at a 5V or 
1 2V logic supply voltage. The corresponding maximum data shift 
frequency possible with these logic supply voltages is 6Mhz or 
1 2MHz respectively. The user can therefore choose the appropri- 
ate V DD voltage to suit the application requirements. 

Normally, the load on the outputs of the drivers is capacitive. Since 
the output has a true complementary MOS configuration, either the 
P-channel or N-channel MOSFET can be turned on at a time. 
When the output P-channel FET is turned on, the capacitive load 
starts to charge and its voltage increases until it reaches V pp . 

One can calculate how fast a certain value of the capacitive load 
can be charged up, as explained in the following example. Assum- 
ing the voltage on the load is at zero volt and a DC voltage of 1 00V 
is applied to the V pp terminal of the IC. As soon as the P-channel 
transistor turns on, the load starts to charge up. Initially, the drain- 
to-source voltage is at maximum value, because V OUT = 0V and 
Vpg = Vpp - Vjhj,.. This P-channel transistor operates in saturation 
and delivers maximum possible current to charge the capacitor. 
The dV/dt is calculated as 

dV/dt = l/C 

where I is the source current of the P-channel transistor and C is 
the load capacitance. Assuming a capacitive load of 1nF, the 
output source current of the HV34 is 5mA, so the dV/dt is 



dV/dt=l/C = 5x10- 3 /1x10-» 
= 5V/us 



Since the V pp is at 1 00V, the time required to charge the load to 90% 
of the V pp is 90%V PP / (dV/dt) = 1 8ns. The dV/dt to charge the load 
for the remaining 10% of the V pp will be slower. This is due to 
decrease in the V DS voltage of the P-channel transistor as the 
voltage on the load increases. The transistor finally gets out of 
saturation and operates in the linear region, thereby causing a 
reduction in the output current. 

In the above example, the output of the IC was "hot switched." The 
term "hot switch" means that a high voltage DC supply is applied 
to device V pp at all times even when the high voltage outputs are 
being switched. On the other hand, "cold switch" means that the 
high voltage supply is brought to a much lower voltage, sometimes 
to zero volt depending on the application, while the high voltage 
outputs are being switched. After switching the outputs, the high 
voltage supply is brought up to the desired voltage level. 

Cold switching may be necessary on some ICs as this prevents 
possible damage to the device due to large crossover current 
during transition from the high-side transistor to the low-side 
transistor and vice versa. In a hot switching system, only a DC high 
voltage power supply is needed; this is simplerthan the cold switch 
system where an extra high voltage switch or a high voltage ramp 
circuit is necessary. 



'R * 



IN5245 
15Vz 




IN5245 
5.1Vz 



MOO 



150 
f2N3906 



IN5245 
S 15Vz 



[2N3906 
150 





IN5245 
5.1Vz 



Figure 4: Ramp Generator 



When the load connected to the output of the IC is very large, the 
risk of damage to the output transistors is not only from the 
crossover current but also because the safe operating area of the 
device may be exceeded. This risk is eliminated by ramping the V pp 
which minimizes the drain-to-source voltage drop across the 
device by controlling the slew rate of the ramping voltage. Ramped 
high voltage supplies are not only less strenuous to the output of 
the ICs, but have the following additional advantages: 

a. Lower power dissipation in the high voltage IC. 

b. Reduced switching noise, which has several disadvantages, 
e.g., malfunction of logic, latch-up, etc. 

The rise and fall time of the output voltage is determined by the 
output sink and source current of the device and the size of the 
load. The slew rate of ramp voltage can be designed to closely 
follow the rising load voltage to minimize the drain-to-source 
voltage drop. Figure 4 shows a typical ramp generator circuit. 

The above circuit utilizes Supertex high voltage DMOS transistors 
VP0635N5 and VN0635N5. The TO-220 package was chosen to 
handle a large power dissipation. If the output current required is 
low, theTO-92 version of these parts, the VN0635N3 and VP0635N3, 
may be used to save component cost and board space. The 15V 
zener diodes provide extra protection for the gate of the DMOS 
transistors. The value of the R and C is chosen in such a way that 
the time constant of this RC is much greater than the output pulse 
width of the ramp generator. V NN and V pp are fixed voltages 
available from the system's main power supply. If a negative 
voltage is not needed, the V NN can be kept at zero volt. 

The input A and B are connected to 5V or 12V logic IC outputs. 
Care must be taken to ensure that either VP0635N5 or VN0635N5 
is on at a time to avoid large crossover currents flowing through 
both transistors at the same time, which may cause catastrophic 
failure. 

In applications where different V pp voltages are required to be 
applied to the deflection plates, a Supertex HV1 01 6P can be used 
to connect the V pp pin of the IC to the appropriate high voltage. 
Figure 5 shows the block diagram of HV1016P , which is used to 
supply 4 different voltages to the V pp of the HV34 by controlling the 
SW0, SW1, SW2 and SW3 turned-on time. 

Piezoelectric transducers can also be driven by Supertex high 
voltage push-puil drivers. The high voltage output of the driver 
forces the interspace of the piezoelectric transducer to expand, 



3-81 



C, o- 



C 2 o- 



c, o- 



CLo- 
LE o- 



I 

+95V 
V DD V nn V pp 



SW1 
120V 



SW2 
80V 



TV T 

0V +140V 80V 



SW3 
60V 



thereby sucking liquid ink into the nozzle. Then, when a high 
voltage of reverse polarity is applied to the transducer while the 
nozzle is filled with ink, the ink will be expelled and deposited on 
the paper. 



Electrostatic Printing/Plotting 

The electrostatic method of printing/plotting is relatively new. 
Electrostatic printers and plotters produce images by converting 
vector data into raster data and applying dots to the medium. This 



: — >v ss 




V DD = 



Figure 6: 

Electrostatic Printing/Plotting 
Open Drain Configuration 

+375V 



NIB (Stylus) 

Paper 
^JTsHOE 



Logic 
In 



Logic 



VbD^ss-SV) 1 — p 
Vdd=(Vss + 5vT^_ 



a 



Logic. Logic 
In 



P-Channel 
(HV49) 



B 



N-Channel 
(HV31) 







NIB 



Figure 7: -375V 
Electrostatic Printing/Plotting 
Push-Pull Configuration 



° Vss 



: Paper 
1PSHOE 



HV34 



GND 



T 



SW1 



SW2 



SW3 



140V 



Non-Impact Printing Applications 



rr 0V 

Figure 5: HV1016 for Selecting V pp Voltages 



allows them to lay down the image across the entire width of the 
media simultaneously and thus increase printing speed. 

The electrostatic printing/plotting process typically uses a toner 
and a paper that will hold charge. The paper is passed over the 
print head which contains a stylus array (NIB) that lays down 
negative charges on the paper. The higher the charge voltage 
across the paper (i.e., between the print head NIB and the SHOE), 
the better the image definition. 

To implement electrostatic printing technology requires very high- 
voltage driver circuits for the stylus arrays either in an open drain 
configuration as shown in Figure 6 or, preferably in a push-pull 
configuration for better efficiency as shown in Figure 7. The current 
required, however, is relatively low, typically below 1 mA. 



High Voltage Drivers for 
Electrostatic Printer/Plotter 
HV31 and HV49 

Supertex HV31 and HV49 are ideally suited for electrostatic 
printer/plotter applications. 

The HV31 is a low voltage serial input to high voltage parallel 
output converter with 64 N-channel open-drain outputs with a 
375V rating. Figure 8 shows a functional block diagram of the 
HV31 . This device consists of a 64 bit shift register, 64 latches and 
logic control to perform the output enable function. A direction 
(DIR) pin controls the data shift through the device, which can be 
clockwise or counter-clockwise as desired. Since many devices 
are often used in one system, data output buffers are provided for 
cascading purposes. 

The HV31 allows up to 6Mhz data shift frequency with logic supply 
voltage of 5 volts, which is convenient to interface with microcom- 
puters directly without the need for voltage shifting circuits. 

The HV49 is a high voltage open-drain P-channel device that can 
be operated up to -375V. The functional block diagram of the HV49 
is the same as for HV31 except that the output section consists of 
open drain P-channel MOSFETs. Being a P-channel device, the 
polarity of all the voltages are reversed. 

For high performance systems, a 375V push-pull configuration 
can be formed using the combination of the HV31 and HV49 
(Figure 7). In this configuration, level shifting of the logic signal is 
required because the input logic voltages for both the HV31 and 



Non-Impact Printing Applications 



Output Enable o- 



LE o- 



Data Input o- 



Clock c- 



DIR o- 



64-bit 
Static 
Shift 
Register 



64 
Latches 



O 



to 



-o Data Out 



-o HV 0UT 1 



-o HV 0UT 2 



60 Additional 
Outputs 



-o HV OUT 63 



-o HV OUT 64 
► 



Figure 8: HV31 Functional Block Diagram 



HV49 are referenced to V ss . The circuit shown in Figure 9, utilizing 
opto-couplers, may be used to achieve the desired level shifting 
and isolation. 

Assume that the logic input signals coming from the TTL logic to 
the opto-couplers are to 5V. The power needed to run the opto- 
couplers is taken from the two floating power supplies. The logic 
signals coming out of the opto-couplers are referenced to the 
floating power supplies. The V ss voltage normally is ramped, as 
discussed earlier, to minimize the voltage drop across the output 
transistor of the device. The two floating power supplies are formed 
by using a transformer, the primary winding of which is connected 
to the 120V AC utility power line. There are two secondary 
windings on the transformer; the outputs will be rectified by the 
bridge rectifiers and stabilized by LM340 linear regulators. 

Since a very high voltage is used for electrostatic printers and 
plotters, arcing can occur between the NIB or stylus and the SHOE 
due to pin holes or cracks in the paper. High current during this 
arcing will be destructive to the driver IC, and adding circuitry for 
protection becomes necessary. Some protection for a short dura- 
tion is afforded by the saturation current of the HV31 and HV49 , 
which typically is around 2 to 4mA . However this is really not 
adequate because considerable heat may be generated for dura- 
tions longer than a few milliseconds. Current limiting resistors are 
required to lower the current further. 

HV46 and HV55 

In some applications such as electrostatic plotters where much 
higher current is desired, Supertex HV46 and HV55 can be used. 

The HV46 offers 32 P-channel open drain outputs similar to the 
HV49. The output voltage and current of the HV46 is -300V and 
60mA respectively. The HV55 is an 32 output, N-channel open 
drain device similar to the HV31 , and has a 300V, 1 00mA rating. 

These devices can be used in either an open drain (Figure 6) or, 
preferably, in a push-pull configuration (Figure 7). Short circuit 



protection by limiting the current will be necessary. The driving 
scheme for the HV49 and HV31 can also be used to drive these 
devices. 



HV32 

The HV32 offers 64 channel push-pull outputs with 250V rating. 
The uniqueness of this device is that the output current can be 
programmed by a resistor network and a reference voltage. 

Figure 1 shows a functional block diagram and Figure 1 1 shows 
the bias circuit for programming the output sink and source current. 
R IMT is an internal resistor of 20Kohms, the Vx is an internal 
reference voltage of 1 .3V. I, and l 2 are the source and sink current 
respectively. For example, if the V pp is 200V, V REF = V pp - 12V= 
188V; and the current to be programmed is 100nA, R, will be 
calculated as 

R, = [(V REF -1.3V)/100x10*]-R lNT 

= [(188-1 3)/1 00x1 0- 6 ] - 20x1 3 

= 1.8 Mohm 

The similar calculation can be done for the sink current. For 
example, if a 100|iA sink current is desired, R 2 is calculated as, 

R 2 = [(V REF -1.3V)/100x10^]-R INT 

= [(12V - 1 .3VJ/100 x 10- 6 ] - 20 X 10 3 

= 87 Kohm 

The range for the programmed output currents is from 25nA to 
250nA. Since the P 0TU and N CTL are all common for 64 outputs, the 
sink and source current of each individual output cannot be 
programmed independently. 

The output current programmability gives users the flexibility to 
drive different sizes of print heads. Only one resistor network is 
needed for programming the current for the whole integrated 
circuit. 



3-83 



Non-Impact Printing Applications 



=120VAC 



470 



LE<H> 
OE o-D> 



470 



CLKo-|> 
Data In o-f> 



LEM> 
OE o-[> 



=120 VAC 




IN5819 



IN4002 

W 

LM340 



In Out 



47uF 



GND - 



0.01 



? V CC = 5V or 12V 



470 < 
74ALS 1004 ' 
CLK<>-t> 
Data In o-£> 



>470 



HCPL 
2231 




HCPL 
2231 



Dir 

HV49 

CLK 
Data In 
LE 
OE 




HCPL 
2231 



HCPL 
2231 



IN4002 




0.01 uF 



CLK 
Data In 
LE 
OE 



HV31 



Dir 



IN5819 



^>V SS 



Figure 9: Level Translation using Opto-couplers 



3-84 



Non-Impact Printing Applications 



BLANK o_ 
Data In/Out o- 



CLKo- 



DIRo- 



64-bit 
Shift 
Register 



Latch 



-o 

Data Out / In 



Figure 10: HV32 Functional Block Diagram 



PctlcHRI'i 



Output, 



N-ctlO— |@JI 2 



64 outputs total 



PctlcH9|Ii 




Output^ 



fVpp 




P-Channel 




Current Control 
(Pctl) 


V REFp = V P p-12V 


N-Channel 
Current Control 


R 2 


(Nctl) 


Vref n = 12V 


i 


Rl + R|NT = 


Vr EFp -Vxi 


h 


R 2 + R)NT = 


Vref n -V X2 


k 


V x « 1 .3V (Nominal) 


R, NT * 20K (Nominal) 


Figure 11: Typical Current Programming Circuitry 



Conclusion 



Multichannel high voltage ICs provide practical solutions for driv- 
ing printer/plotter heads utilizing inkjet and electrostatic technolo- 
gies. High density solutions, which require a low unit area per 
output channel, save printed circuit board space and costs. The 
high voltage devices mentioned in this application note are also 
available in die form suitable for mounting the chips on circuit 
boards or "flip chip" on suitable substrates. 



3™85 



Alphanumeric Index and Ordering Information Iii 

Corporate Profile VI 
Applications Notes |cj 
Quality Assurance and Handling Procedures Ell 

Process Flow H 
Selector Guides and Cross Reference K«j 
N- and P-Channel Low Threshold MOSFETs Wi 
DMOS N-Channel Discretes |:j 
DMOS P-Channel Discretes i!] 
DMOS Arrays and Special Functions iUM 
High Voltage Driver/Interface ICs fif ■ 
High Voltage Analog Switches and Multiplexers \YM 
High Voltage Power Supply ICs iKfl 
CMOS Consumer/Industrial Products i£B 
Surface Mount Packages and Lead Bend Options |M 

Package Outlines i[*Ji 
Die Specifications \fM 
Representatives/Distributors i[:M 



Static 



Techniques 



For MOS Devices 



CAUTION MUST BE USED WHEN HANDLING AND TESTING 
MOS DEVICES. STANDARD PROCEDURESSHOULD INCLUDE 
THE FOLLOWING TECHNIQUES IN ORDER TO AVOID POS- 
SIBLE STATIC DAMAGE: 

1. MOS devices must be stored in containers such as bags or 
tubes made of conductive and/or static dissipative material 
(DOD-HDBK-263). 

2. The person handling the device should wear a wrist-strap 
grounded through a resistor of 1 Ma ±1 0% 

3. Workstations should have grounded conductive mats over 
non-conducting surfaces. 

4. All conductive surfaces and equipment must be connected to 
earth ground. 



5. Rubber gloves, finger cots and clothing that are recommended 
to be worn by any person handling parts must be the type which 
does not generate electrostatic charges. 

6. All parts should be handled by their packages and not by the 
leads. 

7. Relative room humidity should be kept between 45 to 60% 
since static generation increases exponentially as humidity 
decreases. 

8. Work, testing and storage areas should be mopped monthly 
with staticide solution or equivalent. 

9. For further details refer to DOD Handbook 263 and DOD 
Standard 1686. 



FOR YOUR CONVENIENCE, THE FOLLOWING IS A PARTIAL 
LISTOFCOMPANIESTHATSUPPLY ANTISTATIC PRODUCTS: 



3M Nuclear Products 

3M Center 

St. Paul, MN 55101 

Wescorp/DAL Industries, Inc. 
11 55 Terra Bella Ave. 
Mountain View, CA 94043 

Biggam Enterprises, Inc. 
2124 Bering Dr. 
San Jose, CA 95131 

Free-Flow Packaging Corp. 
2500 Middlefield Rd. 
Redwood City, CA 94063 

SpectraScan 

1110AEIkton Dr. 

Colorado Springs, CO 80907 



Conductive Bags, Grounding 
Mats, Tote Bins and Other 
Material 

Wrist Straps 



Wrist Straps, Staticide and 
Other Antistatic/Conductive 
Material 

Anti-Static Packaging 
Material 

Static Control Monitors 



4-1 



Quality Assurance 



The Management of Supertex, Inc. is committed to the continued 
enhancement of product excellence and service through the 
dynamics of its Reliability and Quality Assurance System, through 
the integrity of its people, and through the many professional 
disciplines engaged in new product development and process 
innovation. 

It is the chartered responsibility of the Reliability and Quality 
Assurance Manager to oversee and ensure enforcement of 
Supertex's Quality System. A formal yearly review is undertaken 
to ensure continued development of a Quality System that main- 
tains a competitive stance with the marketplace and meets cus- 
tomer requirements. 

Primary Job Charter of the 
R & QA Departments 

In-Process QC - The primary responsibilities of the Quality 
Control Department are to establish and maintain effective con- 
trols for monitoring manufacturing processes and equipment; to 
provide real time feedback of information concerning the state-of- 
control; and to initiate statistically valid techniques to further 
improve quality and reliability levels. This concept is used exten- 
sively in, but not limited to, the following major Quality Control 
functions: 

• Incoming Raw Materials 

• In-process Wafer Fabrication 

• In-process Assembly 

Quality Assurance (Standard and Hi-Reliability) -The primary 
responsibilities of the Quality Assurance Department are to assure 
that the delivered product meets workmanship standards imposed 
for standard or hi-reliability products and/or special customer 
requirements. This is accomplished through a program of process 
controls and gate inspections designed so that all devices are 
properly tested and sampled prior to shipment. Real time feed- 
back, concerning control/inspection data, keeps all relevant per- 
sonnel fully informed on the quality level of product going through 
final test operations. Major Quality Assurance functions include: 

• Incoming Contract Subassemblies 

• Outgoing Wafer Electrical and Visual Inspection 

• Product Assurance Electrical Test 

• Plant Clearance 

Reliability -The primary responsibility of the Reliability function is 
to assure that a high and consistent level of product reliability is 
continually being produced. The Reliability Department estab- 
lishes, defines and maintains evaluation programs to determine 
process/product reliability. Major Reliability activities include: 

• Failure Analysis 

• Hi-Reliability Program 

• Process/Product Qualification 



• New Product Design Evaluations 

• Reliability Assurance Monitors 

Document Control - The primary responsibilities of the Docu- 
ment Control department are to translate and format internal 
operating procedures and customer requirements into a system of 
regulatory written instructions. Document Control functions to 
ensure documentation integrity by establishing and maintaining 
procedures for: 

• Initiating, revising, approving, distributing, recalling, and archiv- 
ing documents. 

Organization 

The Manager of Quality Assurance/Quality Control reports directly 
to executive staff level of Management. 

Reliability Assurance Management maintains a dual level of 
reporting; with direct report to the R & QA Manager for R & QA 
program coordination and by dotted line to the Product Vice 
President respective of product service for Reliability Assurance 
support. 

It is the responsibility of the R & QA Manager to administer the 
planning, organization, execution, surveillance, appraisal, correc- 
tive action and documentation of Quality Programs. The character, 
responsibility and authority vested with the R & QA Manager will 
establish the means to attain the necessary quality and reliability 
objectives in all aspects of manufacturing within the accorded 
guidelines of this manual. 

Quality programs administered by the R & QA Department support 
the following functions: 

Operator Training - Supertex maintains a System of Operator 
Training and Qualification specific to the nature and complexity of 
each manufacturing operation, inspection, or test requirement. 
The basic training approach used by Supertex is supervised on- 
the-job training assisted by experienced/qualified personnel to 
provide a "buddy system" of training. 

Training is typically performed with the same equipment and tools 
used in the normal manufacturing environment. The use of training 
aids, such as films, photographs and demonstrations of equipment 
and tools, is typical. 

Each department manager is responsible for the training and 
evaluation of the workmanship performance to manufacturing 
norms. 

The R & QA department maintains a system of audits/monitors for 
evaluating operator's adherence to specification and quality of 
workmanship. 

Raw Material Procurement and Qualification - Supertex main- 
tains a system that ensures economical control and conformance 
to detailed technical and quality requirements of purchased mate- 
rials (direct and critical indirect). Material procurement is per- 



4-2 



formed through regulated specifications and drawings. R & QA 
functions within this system by providing the following services: 

• Documented instructions for material evaluation, procedures, 
flow, workmanship standards, test methods and statistical 
sampling. 

• Incoming inspection of raw materials. 

• Identification and segregation of qualified and nonconforming 
material. 

• Vendor qualification and ongoing vendor performance 
appraisal. 

• Feedback of inspection results and informing suppliers of new 
design changes on raw materials. 

• Formal review for disposition of nonconforming materials. 

Equipment Calibration - Supertex maintains a Calibration Sys- 
tem that ensures measurement accuracy of equipment used to 
determine product workmanship and acceptability. 

The Calibration System conforms to MIL-STD-45662. Major pro- 
visions of the R & QA program are described as follows: 

• Qualification of external calibration services. 

• Traceability of references to National Institution of Standards 
and Technology. Identifications of measurement and test 
equipment (electrical, mechanical, and optical) for type and 
frequency of calibration. 

• Document file certifying equipment calibration and recall 
history. 

• Management report on recall status. 

• R & QA audits of equipment calibration (date stickers and 
recall designation). 

Manufacturing Flow, Inspection, and Test Points - Supertex 
maintains Flow Charts that describe the sequential steps of 
semiconductor processing and associated documentation for 
Wafer Fabrication, Assembly, and PostAssembly Finishing through 
Final Outgoing Plant Clearance. Flow charts are prepared for each 
product family and associated manufacturing technology. 

Flow charts that delineate Fabrication processing are regarded as 
proprietary and are not available for external dissemination with- 
out prior approvals from the R & QA Manager and respective 
Product/Operations Vice President. Applicable Assembly Packag- 
ing Flow Charts are available upon request. 

Flow charts for Customer Hi-Reliability Products are documented 
by a detailed lot traveler which defines all sequential operations, 
manufacturing inspection points, Customer Source Inspection 
points, and Quality Assurance product sample acceptance points. 

In-Process Quality Control — Quality Control is a system of 
measurement and surveillance. The System is comprised of 
visual, dimensional, structural, and electrical characterization of 
material from incoming receipt of raw goods to outgoing finished 
product. Information obtained provides management with an 
overview on the state-of-the-process by specifically quantifying 
position of product yield, quality, and reliability. 

Major elements found in Supertax's Quality Control Program are 
summarized by, but not limited to, the following: 

• Environmental monitors (Airborne Particle counts, % RH and 
temperature). 

• Routine Scanning Electron Micrography (SEM) of semicon- 
ductor devices. 

• Specification compliance audits. 

• Random monitor of wafers in-process. 

• Electrostatic discharge prevention/monitor. 



• Product lot sample qualification at critical manufacturing 
points. 

• Wafer/die electrical sort monitor. 

• Quality performance/trend data reporting. 

• Return material analysis reporting. 

• Monitoring of storage, handling, packaging, and identification 
of raw materials, of work-in-process, and of finished product. 

Product Assurance Inspection - Supertex maintains a system 
of Product Qualification through inspection and test of finished 
product prior to customer shipment. 

The Quality Assurance department provides inspection based on 
statistical sampling to ensure that outgoing product quality meets 
internal workmanship standards and customer procurement 
requirements. 

The following process controls, inspections, tests, and documen- 
tation requirements are assured prior to submission of product to 
Customer Source Inspection and final Outgoing Plant Clearance: 

• Test equipment correlation and qualification. 

• Monitor manufacturing test operations. 

• Ensure conformance of product lots to detailed customer test 
requirements (electrical, external visual, mechanical). 

• Assure proper and complete documentation for each product 
lot, both in-process and at-plant clearance. 

Reliability Assurance - At Supertex the Reliability Concept is 
introduced at the design phase of all new products. The factors that 
may affect product reliability are: compatibility of fabrication pro- 
cess, circuit layout and characteristics, assembly process, pack- 
age materials, and application. Hence, Reliability Engineering is 
involved in evaluating all critical factors of reliability, starting with 
the design and first prototype functional circuit. From analysis, 
modification of design, wafer fabrication, and assembly, process 
changes can be implemented to enhance the reliability of the 
product. Approval is given for the release of new product to 
manufacturing only after the reliability of the product is established 
as acceptable within standard norms. 

The Reliability Department provides the Product Group with a 
number of programs to define product reliability levels. Among 
these programs are: 1) Qualification, 2) Reliability, 3) Failure 
Analysis, and 4) Data Collection and Presentation. 

Qualification Program of New Products and Processes 

• Procedures for qualification of new product designs require 
Reliability participation and approval in design reviews, doc- 
umentation, characterization, and reliability stress studies. 

• New package qualification is approved and released for 
production by Reliability after prescribed environmental tests 
have been successfully completed. 

• Qualification of a new product is granted only after Quality and 
Reliability have completed evaluation of process control 
studies. Significant modifications to existing processes are 
treated as new processes for the purpose of qualification. 

• Proper documentation of all changes to process steps and 
procedure, and of any new or improved designs or material, 
is assured by Reliability's approval. 

Reliability Monitor Programs 

• Device and Package Reliability Monitor Programs are effec- 
ted for all packages using a variety of device types to maxi- 
mize data usefulness and to evaluate cost effectiveness of 
equipment. 



4-3 



Dut are not limited to, the following general tests, using the 
appropriate conditions specified in MIL-STD-883, Class B, 
Method 5005: 



Condition 


Method 


Operating Life (HTRB) 


1005 


Steam Pressure (Molded packages) 


N/A 


Temperature Cycling 


1010 


Package Hermeticity 


1014 


Intermittent Opens (Molded package) 


N/A 


Salt Atmosphere (Initial Qual, only) 


1009 


Constant Acceleration 


2001 


Mechanical Shock (Initial Qual, only) 


2002 


Solderability 


2003 


Lead Integrity 


2004 


Vibration (Initial Qual, only) 


2007 


Biased Temperature Humidity 
(Molded packages) 


N/A 



— 



• Accelerated Stress Monitor Programs are conducted to ob- 
tain timely feedback for process evaluations, as well as for 
ultimate device capability studies. 

Failure Analysis 

• It is the policy of Supertex to perform analysis of defective 
product and utilize the resulting findings to improve product 
yield and integrity. 

• Reliability Engineering also performs failure analysis in mode 
and the mechanism of all failures (both from routine reliability 
tests and customer returns). 

Failure Analysis Support Activities include: 

• Qualification of existing products for new applications. 

• Customer Qualifications. Reliability is responsible for review 
and acceptance of all customer requirements. When qualifi- 
cation programs or special testing is required, Reliability 
designs and implements appropriate test plans and coordi- 
nates with customer. 

• Failure analysis, in support of In-Process Quality Control 
monitors, is handled by Reliability through Failure Report 
Requests. This support includes such services as visual 
inspection, metalography, thickness measurements, selec- 
tive etching, and die probing. 

• Customer's requests for failure analysis are filled by Reliabil- 
ity, which coordinates all replies to customers and approves 
all correspondence outside the Company. 

• Where Reliability has determined that corrective action is 
necessary prior to the release of product for shipment, or to 
proceed further in production processing, a Corrective Action 
Request is generated by Reliability. No shipment may occur 
if the integrity of product reliability would be jeopardized. 

Reporting and Publication of Data 

Qualification test reports are prepared and distributed by Reliabil- 
ity for all certified products and processes which have been 
formally qualified and released for manufacturing. 



mented by testing done at outside Test Laboratories that have 
been approved by DESC for performing MIL-STD testing. 



In addition, Reliability Assurance maintains a routine monitor of 
commercial grade finished product to evaluate reliability attributes 
against internally published norms. Products and packages are 
deliberately selected to represent typical characteristics and con- 
ditions of manufacturing - with the following considerations given: 

• Design complexity and fabrication processing technology. 

• Package type/assembly construction and materials. 

• Assembly plant location. 

Supertex reliability data for standard product is published for 
internal use. Specific reliability information is made available to 
customers upon request. 

Plant Clearance Inspection - Supertex maintains a Final Out- 
going Inspection on Finished assembled/tested product to ensure 
that all conditions of processing have been satisfied and that 
support documentation, as specified by contract, is maintained for 
each shipped lot. 

Provisions for the control of shipped product during the Outgoing 
Plant Clearance Final Acceptance Program are structured to 
ensure product workmanship guarantees are met. 



Summary 



Supertex maintains R & QA Programs at critical operations to 
assure that products are manufactured under a documented and 
controlled system for consistency in workmanship standards (fit, 
form, function, and reliability). 

The following Standards and Specifications have been integrated 
into Supertax's manufacturing operations and process control 
programs: 

• FED-STD-209 Clean Room and Work Station Require 

ments, Controlled Environments. 

• DOD-HDBK-263 Electrostatic Discharge Control Hand- 

book for Protection of Electrical and 
Electronic Parts, Assemblies and 
Equipment 

• DOD-STD-1 686 Electrostatic Discharge Control Program 

for Protection of Electrical and Electronic 
Parts, Assemblies and Equipment. 

• MIL-M-38510 Microcircuits, General Specification For. 

• MIL-Q-9858 Quality Program Requirements. 

• MIL-l-45208 Inspection Systems. 

• MIL-S-19500 Semiconductor Devices, General 

Specification For. 

• MIL-STD-1 05 Sampling Procedures and Tables for 

Inspection by Attributes. 

• MIL-STD-750 TestMethodsforSemiconductorDevices. 

• MIL-STD-883 Test Method and Procedures for 

Microelectronics. 

• MIL-STD-202 Test Methods for Electronic and Electri- 

cal Component Parts. 

• MIL-STD-45662 Calibration System Requirements. 

• Special Customer Specifications 



Alphanumeric Index arid Ordering Information Mi 

Corporate Profile WA 
Applications Notes iCj 
Quality Assurance and Handling Procedures 

Process Flow m 
Selector Guides and Cross Reference !*■ 
N- and P-Channei Low Threshold MOSFETs Hi 
DMOS N-Channel Discretes WM 
DMOS P-Channel Discretes §!■ 
DMOS Arrays and Special Functions 

High Voltage Driver/Interface ICs iiB 
High Voltage Analog Switches and Multiplexers WM 
High Voltage Power Supply ICs 1KB 
CMOS Consumer/Industrial Products \JiM 
Surface Mount Packages and Lead Bend Options if 

Package Outlines |[*J 
Die Specifications ffl£ 
Representatives/Distributors til] 



Supertex inc. 



DMOS /HVCMOS 
Standard Product 
Flow 



Wafer Fab 

r °' c ^ 

I Photomasks and I 
\^ Substrates y 



Wafer Fabrication 



QC 

Finished Wafer 
Inspection 



Wafer 
Backside Process 



100% Wafer 
Electrical Test 
(Sort) 



QA 

Visual Inspection 
I 

To Assembly or 
QA Plant Clearance 
(Wafers Only) 



Assembly 



Saw and Visual 



V Visual Inspection J 



Die Attach 










Wire Bond 






1 





QA Plant Clearance 
(Dice orders only) 



s 5c X 

{ Die Attach ) 
V Monitor J 



QC 



QC 
Wire Bond 
Monitor 



Visual Inspection J 



Seal 
(Hermetic Only) 



Mold 
(Plastic Only) 



Stabilization 
Bake 



Post Mold Cure 



Gross and Fine 
Leak 



Marking 



Marking 

ZJIZ 



Trim and Form 



Temperature 
Cycle (option) 



QC 

Visual Inspection 



To Test 
(See page 5-2) 



5-1 



DMOS /HVCMOS Standard Product Flow 



Test 



I 

(QA Visual 
Inspection J 



100% Electrical Test 



Optional Burn-in 



100% Electrical Test 



Reliability 
Monitor 



Mark 




QA Plant 
Clearance Inspection 



HVCMOS IC 
Process Option Flows 



RB PRODUCT FLOW 

(SIMILAR TO MIL-STD-883 
CLASS B) 



Preseal Visual 

Method 2010, Condition B 



Stabilization Bake 
Method 1008, Condition C, 
24 Hrs. 9 150°C 



zz 



Temperature Cycle (2) 
Method 1010, Condition C, 
10 Cycles, -65°C to + 150°C 
10 min. Minimum @ 
Temperature Extremes 



Constant Acceleration (2) 
Method 2001 , Condition DIE, 
Y Axis Only 

20,000 G for 24-40 LD PKGS 
30,000 G (or 8-20 LD PKGS 



Fine Leak (2) 
Method 1014, Condition A 
orB, 

5 x 10" 8 atm cc/sec 

I 



Gross Leak (2) 
Method 1014, Condition C1 



Trim and Mark 



External Visual 



ZC 



Electrical Test (4) 
100% Go/No-Go, 
Static and Functional 
Tests e Max Rated 
Temperature 



3 



Dynamic/HTRB Burn-in 
Method 1015. Condition C, 
160 Hrs. ® 125°C 



Electrical Test 
100% Go/No-Go 
Static Dynamic and 
Functional Tests ® 25°C 



Electrical Test 
100% Go/No-Go 
Static and Functional 
Tests <S Max. Rated 
Temperature 



Group A 




25°C Tests 


LTPD2 


Max. Rated Temp 


LTPD2 


Min. Rated Temp 


LTPD2 



Group B Sample (3) 
Per MIL-STD-883 



RC PRODUCT FLOW 



COMMERICAL PRODUCT FLOW 



Preseal Visual 

Method 2010, Condition B 



Stabilization Bake 
Method 1 008, Condition C, 
24 Hrs. 9 150°C 



Temperature Cycle (2) 
Method 1010, Condition C. 
10 Cycles, -65»C to + 150°C 
10 min. Minimum © 
Temperature Extremes 



Constant Acceleration (2) 
Method 2001 , Condition DIE. 
Y Axis Only 

20,000 G for 24-40 LD PKGS 
30,000 G for 8-20 LD PKGS 



Fine Leak (2) 
Method 1014, Condition A 
or B, 

5 x 10~ 8 atm cc/sec 
I 



Gross Leak (2) 
Method 1014, Condition C1 



Trim and Mark 



External Visual 



Electrical Test (4) 
100% Go/No-Go, 
Static and Functional 
Tests @ Max Rated 
Temperature 



Group A 
25°C Tests 
Max. Rated T 
Min. Rated Te 


LTPD2 
amp LTPD2 
mp LTPD2 






Group B Sample (5) 
Per MIL-STD-883 



Preseal Visual 
Supertex Standard 



ZL 



Stabilization Bake 
Method 1008. Condition C, 
24 Hrs. 18 150 C 



Fine Leak 1%AQL (2) 
Method 1014. Condition A 
orB, 

5 x 1 0" e atm cc/sec 

I 



Gross Leak 1%AQL (2) 
Method 1014, Condition C1 



Trim and Mark 



External Visual 



^Optional Electrical Test 
. 100% Go/No-Go, 
| Static and Functional 
Tests @ Max. Rated 
| Temperature 



["optional HTRB or 
. Dynamic Burn-in 
| Method 1015, Condition A | 
, orC, 

|_18 Hrs._@_125°C 



Electrical Test 
100% Go/No-Go 
Static and Functional 
Tests @ Max. Rated 
Temperature 



Group A 

25°C Tests 0.65% AQL 



Note 1: Processing consists of 100% screening and Group A. 

Generic group B, C and D data available on request. 
Note 2: Hermetic packages only. 

Note 3: Group C & D periodic lot sampling per MIL-STD-883. 
Note 4: As required. 
Note 5: No group C & D 

All test methods are per MIL-STD-883 unless specified otherwise. 

5-3 



DMOS Process 
Option Flow Chart 



DMOS ARRAY 
RB FLOW< 1 > 

(SIMILAR TO MIL-STD-883 
CLASS B) 



Preseal Visual 

Method 2010, Condition B 



Stabilization Bake 
Method 1008, Condition C, 
24Hrs. @ 150°C 



Temperature Cycle 
Method 1010, Condition C, 
10 Cycles, -65°C to +150°C 
10 minutes minimum @ 
each temperature extreme 



Constant Acceleration (2) 
Method 2001, Condition E, 
Y, Axis Only -20,000 G 



Fine Leak (2) 
Method 1014, Condition A 
orB, 

5 x 10~ 8 atm cc/sec 



Gross Leak (2 
Method 1014, Condition C, 



Electrical Test 
100% Go/No-Go, 
25°C D C. Parameters 



fHTRGB Bum-in (5)1 

Method 1015, Condition A, 
|_48Hrs. e_150°C 

["Electrical Test (5)~| 

. 100% Go/No-Go 

I 25°C D.C. Parameters 



HTRB Bum-in 

Method 1015, Condition A, 

80 Hrs. « 150°C 



Electrical Test (Post burn-in) 
100% Go/No-Go 
25°C D.C. Parameters 



Group A 

Subgroup 1 VIS/MEC, 
LTPD 5, 

Subgroup 2 D.C. ® 25°C 
LTPD 2, 

Subgroup 3 D.C. MinVMax. 

Temperature, 

LTPD 2, 

Subgroup 4 A C. 
LTPD 2 



SX FLOW 

(SIMILAR TO JAN TX) 
SXV FLOW<» 

(SIMILAR TO JAN TXV) 
MIL-STD-750 



Preseal Visual 


(6) 


Method 2072 





Stabilization Bake 
Method 1032, 
24 Hrs. 9 150°C 



I 



Temperature Cycle 
Method 1051 

20 Cycles, -65°C to + 1 50°C 
1 5 minutes minimum @ 
each temperature extreme 



Constant Acceleration (2) 
Method 2006 
Y 1 Axis only. 
TO-3- 10,000 G, 
Others - 20,000 G 



JZ 



Fine Leak (2) 
Method 1071, Condition G 
orH. 

Maximum Leak Rate 
TO-3 - 5 x 1 0" 7 atm cc/sec 
Others - 5 x 10" e atm cc/sec 



Gross Leak (2) 
Method 1071, Condition C 



Electrical Test 
100% Go/No-Go, 
25°C D.C. Parameters 



14) 



HTRGB Burn-in (3) 
Method 1042, Condition B, 
48 Hrs. 8 150°C 



Electrical Test 
100% Go/No-Go, 
25°C D.C. Parameters 



(*) 



HTRB Bum-in 

Method 1042, Condition A, 

160 ±8 Hrs. © 150°C 



Electrical Test 
1 00% Go/No-Go, 
25°C D.C. Parameters 
I 



(4) 



Electrical Test 
100% Go/No-Go, 
Group A, Subgroup 2 



Group A 

Subgroup 1 VIS/MEC, 
LTPD 5, 

Subgroup 2 D.C. « 25°C 
LTPD2, 

Subgroup 3 D.C. Min./Max. 

Temperature, 

LTPD 2, 

Subgroup 4 A.C. 
LTPD2 



SJ FLOW 

(SIMILAR TO JAN) 
MIL-STD-750 



Stabilization Bake 
Method 1032, 
24 Hrs. 9 150"C 



Fine Leak 1%AQL (2) 
Method 1071. Condition G 
orH, 

Maximum Leak Rate 
TO-3 = 

Cond. G 5 x 1 0" 7 atm cc/sec 
Cond. H 1 x 10" 7 atm cc/sec 
Others = 5 x 10" 8 atm cc/sec 



Gross Leak (2) 
Method 1071. Condition C 



Electrical Test 
100% Go/No-Go, 
25°C D.C. Parameters 



Group A 

Subgroup 1 VIS/MEC, 
LTPD 5 

Subgroup 2 D.C. <8 25°C, 
LTPD 2, 

Subgroup 3 D.C. Min./Max. 

Temperature, 

LTPD 2, 

Subgroup 4 A.C. LTPD 
2 



COMMERICAL BURN-IN 
SC FLOW 

MIL-STD-750 



Stabilization Bake 
Method 1032, 
24 Hrs. @ 150°C 



Fine Leak 1%AQL (2) 
Method 1071, Condition G 
orH. 

Maximum Leak Rate 
TO-3 = 

Cond. G 5 x 10" 7 atm cc/sec 
Cond. H 1 x 1 0" 7 atm cc/sec 
Others = 5 x 10" 8 atm cc/sec 



Gross Leak (2) 
Method 1 071 , Condition C 



Electrical Test 
100% Go/No-Go, 
25»C D.C. Parameters 



HTRB Bum-in 

Method 1042, Condition A, 

96 Hrs. <8 150°C 



Electrical Test 
100% Go/No-Go 
25°C D.C. Parameters 



Group A 

Subgroup 1 VIS/MEC, 
LTPD 5, 

Subgroup 2 D.C. @ 25°C 
LTPD 5 



STANDARD PRODUCTS 

MIL-STD-750 



Stabilization Bake 
Method 1032. 
24 Hrs. 9 150"C 



Fine Leak 1%AQL (2) 
Method 1 071 , Condition G 
orH, 

Maximum Leak Rate 
TO-3 = 

Cond. G 5 x 10" 7 atm cc/sec 
Cond. H 1 x 1 0" 7 atm cc/sec 
Others = 5 x 1 0" 8 atm cc/sec 
I 



Gross Leak (2) 
Method 1071 , Condition C 



Electrical Test 
100% Go/No-Go, 
25°C D.C. Parameters 



Group A 

Subgroup A 0.65% AQL 
Subgroup 1 VIS/MEC, 
Subgroup 2 D.C. @ 25°C 



Note 1 : Processing consists of 100% screening and Group A only. 

Generic Group B, C, & D data available on request. 
Note 2: Hermetic packages only. 
Note 3: HTRGB-High temperature reverse gate bias. 



Note 4: Read and Record with delta and percent values is optional. 
Note 5: Optional. 

Note 6: Preseal visual for SXV flow only. Not applicable for SX flow 
All test methods are per MIL-STD-750 unless specified otherwise. 

5-4 



DMOS High 
Reliability Products 



The following products are available with High Reliability processing per test methods and flows of MIL-STD-750 and MIL-STD-883. 
For ordering purposes, add the process flow prefix to the device number as shown in the following examples: 

Process Flow Device Type High Rel Part Number 

SX VN0104N2 SXVN0104N2 

RB VN0106N7 RBVN0106N7 



Device Type 


RB 


SX 


sxv 


SJ 


sc 


2N6659 




• 


• 


• 


• 


2N6660 




• 


• 


• 


• 


2N6661 




• 


• 


• 


• 


TN0102N2 




• 


• 


• 


• 


TN0104N2 




• 


• 


• 


• 


TN0106N2 




• 


• 


• 


• 


TN0110N2 




• 


• 


• 


• 


TN0520N2 




• 


• 


• 


• 


TN0524N2 






• 






TN0602N2 






• 






TN0604N2 






• 






TN0606N2 






• 






TN0606N7 


• 










TN0610N2 






• 






TN0620N2 






• 






TN0624N2 






• 






TP0102N2 






• 






TP0104N2 






• 






TP0602N2 






• 






TP0604N2 












TP0606N2 












TP0606N7 












TP061 0N2 






TP0616N2 




• 




• 


• 


TP0620N2 










• 


TQ3001 N7 












VC0106N7 


• 










VN0104N2 




• 


• 


• 


• 


VN0104N7 


• 










VN0104N9 




• 


• 


• 


• 


VN0106N2 




• 


• 


• 


• 


VN0106N7 


• 










VN0106N9 




• 


• 


• 


• 



Device Type 


RB 


SX 


SXV 


SJ 


SC 


VN0109N2 




• 


• 


• 


• 


VN0109N9 




• 


• 


• 


• 


VN0116N2 




• 


• 


• 


• 


VN0120N2 




• 


• 


• 


• 


VN0335N1 




• 


• 


• 


• 


VN0335N2 




• 


• 


• 


• 


VN0340N1 




• 


• 


• 


• 


VN0340N2 




• 


• 


• 


• 


VN0345N1 




• 


• 


• 


• 


VN0345N2 




• 


• 


• 


• 


VN0350N1 




• 


• 


• 


• 


VN0350N2 




• 


• 


• 


• 


VN0300B 




Refe 


r to TN06 


04N2 




VN0535N2 




• 


• 


• 


• 


VN0540N2 




• 


• 


• 


• 


VN0545N2 




• 


• 


• 


• 


VN0550N2 




• 


• 


• 


• 


VN0635N2 




• 






• 


VN0640N2 










• 


VN0645N2 












VN0650N2 












VN10KN9 












VN1106N2 












VN1110N2 












VN1116N2 












VN1120N2 












VN1204N2 












VN1206N2 












VN1210N2 












VN1216N2 












VN1220N2 












VN1206B 




Refe 


r to TN0620N2 




VN1210B 




Refer to TN0620N2 





DMOS High Reliability Products 



Device type 


Hb 


C V 

OA 




C i 


CP 


\/M1 Qfi/1 MO 












\/M1 Qf1fiM9 
V IN 1 OUOINt 












V IN 1 O 1 UIN£ 












VN17flfiR 

V IN 1 # uDD 




Reft 




>2 ON 2 




VN171C1R 

V IN 1 / 1 ULJ 




Reft 


>r tn TNOf 


>20N2 




V INit 1 UQIN r 












VN91 f DNF 

V INt 1 1 UIN l 












\/Pfl1 flAMO 












\/Pfi1 ("14N.7 
V rU I UM-IN / 
























VP0106N2 












V r U 1 UDIN / 












\/pni nfiMQ 

V rU I UDINy 












v ru i in^i 












v ru i uyiNa 












v ru t i uin*l 












V ru I ^:UIN^ 












V rUOOOlN I 












UpnoQCMo 
V r UOOOINt 












vrUo^UIN 1 












V r UO^tUIN^: 












Vr0345N1 












VP0345N2 












VP0350N1 












VP0350N2 












VP0300B 




Ref 


sr to TPOf 


S04N2 




VP0535N2 




• 


• 


• 


• 



LJcviut; i ypc 


RB 


SX 


SXV 


SJ 


sc 


VP0540N2 
























VP0550N2 












VP0635N2 












VP0640N2 












VP0645N2 












VP0650N2 












VP0808B 




Refer to TP0610N2 




VP1 008B 




Reft 


it to r poi 


310N2 




VP1 106N2 












Vr 1 1 1 UN<i 












VP1 1 1fiN? 

Villi \JI It 












VP1 190.N? 












VP1204N2 












VP1206N2 










• 


VP1210N2 

VI It lul it 












VP1216N2 












VP199flM9 
v n i tiiuiN^i 












VP1304N2 












VP1 ^flfiN? 












VP1 ^10N? 

V i 1 O 1 VI it 












V W 1 L/UUIN f 












VUl UU i r 












vu I uu*tr 












VQ2001 P 












VQ2006P 












VQ3001N7 












VQ7254N7 













Alphanumeric Index and Ordering Information 




Corporate Profile 


wm 


Applications Notes 


mm 


Quality Assurance and Handling Procedures 


mm 


Process Flow 


mm 


Selector Guides and Cross Reference 


Em 


N- and P-Channel Low Threshold MOSFETs 


wm 


DMOS N-Channel Discretes 


mm 


DMOS P-Channe! Discretes 


mm 


DMOS Arrays and Special Functions 


urn 


High Voltage Driver/Interface ICs 


mm 


High Voltage Analog Switches and Multiplexers 


* 


High Voltage Power Supply ICs 




CMOS Consumer/Industrial Products 


mm 


Surface Mount Packages and Lead Bend Options 




Package Outlines 


* 


uig opeuiiioaiion» 


■ , ■ 1 
t. 


Representatives/Distributors 





unapter 6 - Selector Guides and Cross Reference 

DMOS Selector Guide 6-1 

DMOS Array Selector Guide 6-3 

HVCMOS Selector Guide 6-5 

DMOS FETs Cross Reference 6-10 



^ Super tex inc. 



DMOS 
Selector Guide 



N-Channel Low Threshold Enhancement-Mode MOSFETs 



Device 
Family 


BV DSS 
Min(V) 


RDS (0N) 
Max (ohms) 


'd(ON) 

Min(A) 


Typ(pf) 


VGS<th) 

Max(V) 


Package Options 


TO-39 






CATQQ 


uuaa 


uie 


TN01L 


20, 40 


1.8 


2.0 


45 


1.6 














TN01A 


60, 100 


3.0 


2.0 


50 


1.6 














TN05C 


200, 240 


10.0 


0.3 


45 


1.5 














TN05D 


350, 400 


22.0 


0.25 


48 


2.0 















TN06L 


20, 40 


0.75 


4.0 


100 


1.6 














TN06A 


60, 100 


1.50 


3.0 


100 


1.6 


• 




• 




• 




TN06C 


200, 240 


6.0 


1.0 


110 


1.6 


• 




• 








TN06D 


350, 400 


10.0 


1.0 


105 


1.8 














TN07L 


20 


1.3 


0.5 


130 


1.0 














TN25L 


20,40 


1.0 


4.0 


100 


1.6 














TN25A 


60, 100 


1.5 


3.0 


100 


1.6 














TN25C 


200, 240 


6.0 


1.0 


110 


2.0 














TN25D 


350, 400 


12.0 


1.0 


105 


1.8 














TN25U 


18 


2.5 


0.25 


110 


0.8 














TN26D 


350, 400 


5.0 


2.0 




2.0 




• 











Note: 1 . Refer to Arrays and Special Functions section for packages available. 



P-Channel Low Threshold Enhancement-Mode MOSFETs 



Device 
Family 


BV DSS 
Min (V) 


RDS (ON) 
Max (ohms) 


'd(ON) 

Min (A) 


C|SS 

Typ (pt) 


V GS<th) 

Max (V) 


Package Options 


TO-39 


TO-92 


TO-220 


SOT89 


Quad 1 


Die 


LP07 


-16.5 


1.5 


-1.2 


120 


-1.0 














TP01L 


-20, -40 


4.0 


-0.85 


45 


-2.4 


• 












TP06L 


-20, -40 


2.0 


-2.0 


100 


-2.4 


• 








• 




TP06A 


-60, -100 


3.5 


-1.5 


100 


-2.4 










• 




TP06C 


-160, -200 


12.0 


-0.75 


100 


-2.4 


• 




• 








TP25L 


-20, -40 


2.0 


-2.0 


100 


-2.4 








• 






TP25A 


-60, -100 


3.5 


-1.5 


100 


-2.4 














TP25C 


-160, -200 


12.0 


-0.75 


110 


-2.4 








• 






TP25D 


-350, -400 


25.0 


-0.4 


100 


-2.4 




• 




• 






Note: 1 . Refer to Arrays and Special Functions section for packages available. 

N-Channel Depletion-Mode MOSFETs 


Device 
Family 


BV DSS 

Min (V) 


RDS (0N) 
Max (ohms) 


V GS(OFF) 

Gate to Source 
OFF Voltage 


l DSS @V GS = 0V 
Saturated Current 


TO-39 
N2 


TO-92 
N3 


TO-220 
N5 


SOT-89 
N8 


Die 
ND 


Min (V) 


Max (V) 


Min (mA) 


Max (mA) 




LND1 


500 


1000 


-1.0 


-3.0 


1.0 


3.0 




• 




• 


• 


DN25 


350, 400 


25 


-1.0 


-5.0 


150 




• 


• 


• 


• 


• 



6-1 



DMOS Selector Guide 



N-Channel Enhancement-Mode MOSFETs 



Device 


BV DSS 


RDS (ON) 

Max (ohms) 


'd(ON) 

Min (A) 


C ISS 


Package Options 


Family 


Min (V) 


Typ (pf) 


TO-3 


TO-39 


TO-52 


TO-92 


TO-220 


Quad 1 


Die 


VN01 A 


40, 60, 90 


3.0 


2.0 


45 






• 


• 




• 




VN01 C 


h en orvi 
1 60, 200 


10.0 


0.4 


45 








• 








VN03D 


350, 400 


2.5 


3.0 


550 


• 














VN03E 


450, 500 


4.0 


2.0 


[TEA 

OOU 


• 














VN03F 


rrn cnn 

550, 600 


o.u 


1 .5 


rrA 
OOU 


• 














\ /Mncn 


350, 400 


or r\ 

oo.U 


n oc 


4o 
















VN05E 


450, 500 


60.0 


0.1 5 


45 














# 


VINUOL* 


OOU, *fUU 


I u.u 


n 7K 


1 nc 
I uo 




_ 










# 


VNUOt 


4ou, OUU 


1 O.U 


-DU 


-1 OK 
















\/MARC 
V iNUor 


Oi>U, DUU 




n oe 


UK 
OO 
















VIM! 1A 


DU, 1 uu 


f*l 1 
U. / 


o.u 
















# 


\/mi 1 
VIN I 1 U 


1 en onn 
\ DU, *iUU 


O.U 


o n 


cCJU 
















\/M1 O A 

VNi<:A 


/in en inn 
4U, DU, 1 UU 


U.o 


on n 


vnn 
/UU 
















VN13A 


40, 60, 100 


8.0 


0.50 


25 








• 








VN21A 


60, 100 


3.0 


0.5 


45 












• 




VN22A 


60, 100 


0.35 


8.0 


400 
















VN22C 


200, 240 


1.25 


5.0 


300 








• 








Note: 1 . Refer to Arrays and Special Functions section for packages available. 










P-Channel Enhancement-Mode MOSFETs 








Device 


BV DSS 




'□(ON) 




Package Options 


Family 


Min (V) 


Max (ohms) 


Min (A) 


Typ (pf) 


TO-3 


TO-39 


TO-52 


TO-92 


TO-220 


Quad 1 


Die 


VP01A 


-40, -60, -90 


8.0 


-0.50 


45 






• 


• 


• 


• 




VP01C 


-160, -200 


25.0 


-0.35 


50 








• 


• 






VP03D 


-350, -400 


6.0 


-1.5 


600 


• 








• 






VP03E 


-450, -500 


7.5 


-1.0 


500 


• 








• 






VP05D 


-350, -400 


75.0 


-0.20 


45 
















VP05E 


-450, -500 


125.0 


-0.10 


45 








• 








VP06D 


-350, -400 


25.0 


-0.40 


105 
















VP06E 


-450, -500 


25.0 


-0.20 


95 








• 








VP11A 


-60, -100 


2.0 


-5.0 


300 
















VP11C 


-160, -200 


5.0 


-1.5 


300 
















VP12A 


-40, -60,-100 


0.8 


-6.0 


550 
















VP12C 


-160, -200 


2.5 


-4.0 


600 
















VP13A 


-40, -60,-100 


25.0 


-0.25 


25 








• 




• 




VP21A 


60, 100 


12.0 


0.50 


45 








• 








VP22A 


-40, -60, -100 


-0.9 


4.0 


450 








• 









Note: 1 . Refer to Arrays and Special Functions section for packages available. 



6-2 







DMOS Array 
£ Selector Guide 


Lit Sua 


ertex in 





Low Voltage N-Channel Arrays 



Device 
No. 1 


Number of 
Channels/Type 


BV DSS 
Min (V) 


R DS (ON) 

Max (LI) 


Package Options 


Plastic Dip 


Ceramic Dip 


SOW-20 


Ceramic LCC 


Die 


VN0104 


4N 


40 


3 


• 










VN0106 


4N 


60 


3 












TN0604 


4N 


40 


1.0 






• 






TN0606 


4N 


60 


1.5 


• 


• 








VN2106 


4N 


60 


3 








• 




VN2110 


4N 


100 


3 








• 




VQ1000 


4N 


60 


5.5 












VQ1001 


4N 


30 


1 




• 








VQ1004 


4N 


60 


3.5 


• 


• 









Notel: Excluding package suffix. 



Low Voltage P-Channel Arrays 



Device 
No. 1 


Number of 
Channels/Type 


BV DSS 
Min (V) 


" DS(ON) 

Max (< >) 


Package Options 


Plastic Dip 


Ceramic Dip 


SOW-20 


Ceramic LCC 


Die 


VP0104 


4P 


-40 


8 


• 


• 








VP0106 


4P 


-60 


8 


• 


• 








TP0604 


4P 


-40 


2 






• 






TP0606 


4P 


-60 


3.5 


• 


• 








VQ2001 


4P 


-30 


2 




• 








VQ2006 


4P 


-90 


5 




• 









Note 1 : Excluding package suffix. 



Low Voltage Complementary Arrays 



Device 
No. 1 


Number of 
Channels/Type 


BV DSS 
Min (V) 


R DS (ON) 

Max (12) 


Package Options 


Plastic Dip 


Ceramic Dip 


SOW-20 


Ceramic LCC 


Die 


TC0604 


2N + 2P 


40 


3.0 2 






• 






VC0106 


2N + 2P 


60 


11.0 2 












TQ3001 


2N + 2P 


40 


3.0 2 








• 




VQ3001 


2N + 2P 


40 


3.0 2 


• 


• 




• 




VQ7254 


2N + 2P 


20 


3.0 2 


• 


• 









Notes: 

1 . Excluding package suffix. 

2. One N-channel plus one P-channel. 



6-3 



AN0120 


8N 


200 


300 


* 




* 


AN0130 


8N 


300 


300 


* 




— ' 


AN0140 


8N 


400 


350 


' 


• 




AN0420 


8N 


200 


300 


: ■ 




— ' 


AN0430 


8N 


300 


300 


■ '- ■ 




— 


AN0440 


8N 


400 


350 


' 


• 


— ' 


AP0120 


8P 


-200 


600 


' 






AP0130 


8P 


-300 


600 








AP0140 


8P 


-400 


700 




• 






or 




ouu 








AP0430 


8P 


-300 


600 








AP0440 


8P 


-400 


700 




• 





Notes: 

1 . Excluding package suffix. 

2. Monolithic 8 Channel Array. 



High Voltage Low Leakage Arrays 2 3 



Device 


Number of 


BV DSS 
Min (V) 


"dS (ON) 

Max (L>) 


Package Options 


No. 1 


Channels/Type 


Plastic Dip 


SOW-20 


Die 


AN0116 


8N 


160 


350 








AN0132 


8N 


320 


350 








AN0416 


8N 


160 


350 








AN0432 


8N 


320 


350 








AN0516 


8N 


160 


350 








AN0532 


8N 


320 


350 








AP0116 


8P 


-160 


700 








AP0132 


8P 


-320 


700 








AP0416 


8P 


-160 


700 








AP0432 


8P 


-320 


700 








AP0516 


8P 


-160 


700 








AP0532 


8P 


-320 


700 









Notes: 

1. Excluding package suffix. 

2. Monolithic 8 Channel Array. 

3. Low l DSS Leakage (refer to data sheet for details). 



High Voltage Level Translators 



Device 
No. 1 


Number of 
Channels 


v PP 

Max (V) 


'source 
Min (mA) 


'sink 
Min (mA) 


Package Options 


Plastic Dip 


Ceramic Dip 


SOW-20 


Die 


HT0130 


8 


300 


0.2 


0.1 











Notes: 

1 . Excluding package suffix. 



6-4 



HVCMOS 
Selector Guide 



High Voltage Driver/Interface ICs 
High Voltage Source/Sink Outputs (Push-Pull) 



Device 
Number 


Out- 
puts 


Logic Configuration 


Output 
Operating 
Voltage 


Output 
Current/ 
Channel 


Similar Devices 


Applications 


HV04 
HV06 


64 


Serial to parallel converter w/ 
latches, polarity and blanking 


60V 
80V 


+10mA 
-20mA 




EL column drivers, non- 
impact printers, LCD displays 


HV04H 
HV06H 


64 


Serial to parallel converter w/ 
latches, polarity and blanking 

W/ 1 IUIoWIIUi 1 IvdLJdUMIly 


60V 
80V 


+10mA 
-20mA 




EL column drivers, non- 
impact printers, LCD displays 


HV33 


32 
+22 


Serial to parallel converter w/ 

Oil uuc 


36V 


+4mA 


— 


Printhead driver 


HV34 


64 


Serial to parallel converter w/ 

IdlOMco, jJUIdlily dilu UldllMliy, 

V DD = 5V 


180V 


+5mA 


— 


Electrostatic and ink-jet 

nrint*3rc;/nl(->ttorQ PI ✓ i rtri\/£>rQ 
jji ii itcji o/ jjiwiici o, r i — z_ i uiivcio 


nvoo 




OeNdl lU pdldllcl OOllVGIlCI 


£./ JV 






ClfcJOirubldUU dllU lllr\-JtrL 

printers/plotters, PLZT drivers 


uwoc 

nvoo 


4 


"\\\ UlUUfc; UflVfcil 


220V 


10mA 




Pin H ir\iHo Hriwor 
r hi uiuuc uiivt-i 


HV38 


32 


Gray shade column driver w/ 
16 analog levels 


60V 


±15mA 


— 


Video and gray shade EL and 
LCD displays 


HV53 
HV54 


32 


Serial to parallel converter w/ 
latches, output enable 


80V 


±20mA 


Tl SN75555/75556 
Sprague UCN5853/5854 


EL column drivers and non- 
impact printers, LCD drivers 


HV57 
HV58 


32 


Serial to parallel converter w/ 
latches, polarity and blanking 


80V 


±20mA 


Tl SN75555/75556 
Sprague UCN5853/5854 


Non-impact printers/plotters, 
EL displays, LCD drivers 


HV500 


32 


AC plasma driver w/ multi- 
plexed 8-bit shift register 


100V 


±15mA 


Tl SN75500/55500 


AC plasma display drivers, 
printers 


HV501 


32 


Serial to parallel AC plasma 
driver w/ shift register 


100V 


±15mA 


Tl SN75501/55501 


AC plasma display drivers, 
printers 


HV518 


32 


Serial to parallel converter w/ 
latch enable and strobe pins 


80V 


+50nA 
-25mA 


Tl SN75518 
Sprague VCN5818-1 


Plasma and vacuum 
fluorescent display driver 


HV60 


32 


LCD driver w/ active return 
to ground 


±40V 


±15mA 


None with return to 
GND capability 


High voltage LCD displays 


HV65 


32 


Serial to parallel converter w/ 
backplane output 


60V 


±5mA 


Tl SN75555/75556 


EL column drivers, non- 
impact printers, LCD display 
drivers 


HV6810 


10 


Serial to parallel converter w/ 
latches 


80V 


+100uA 
-25mA 


Tl TL4810 
Sprague UCN5810 


Vacuum fluorescent display 
drivers 


HV70 


34 


Serial to parallel converter w/ 
polarity and output enable 


230V 


±70mA 


Tl SN755563 
SN755564 


Row driver for EL, plasma 
and other panels 


HV72 


40 


Serial to parallel converter w/ 
polarity and output enable 


250V 


±70mA 


NEC uPD1 6302 


AC TFEL row drivers 


HV77 


64 


Serial to parallel converter w/ 
four 16-bit shift registers 


80V 


±15mA 




EL row drivers with high data 
throughput 


HV78 


64 


Serial to parallel converter w/ 
two 32-bit shift registers 


80V 


±15mA 




EL row drivers with high data 
throughput 



6-5 



HVCMOS Selector Guide 



High Voltage Source/Sink Outputs (Push-Pull) - continued 



Device 
Number 


Out- 
puts 


Logic Configuration 


Output 
Operating 
Voltage 


Output 
Current/ 
Channel 


Similar Devices 


Applications 


HV701 
HV711 


40 


Serial to parallel VF driver w/ 
shift register 


220V 


+0.5mA 
-3.0mA 


Tl 755701/711 


Vacuum-fluorescent displays 


HV702 
HV712 


40 


Serial to parallel VF driver w/ 
shift register 


220V 


+2. 5m A 
-10mA 


Tl 755702/712 


Vacuum-fluorescent displays 


HV83 
HV84 


32 


Serial to parallel converter w/ 
latches, output enable, 
V DD = 5V 


80V 


±20mA 


Tl SN75555/75556 
Sprague UCN5853/5854 


EL column drivers, non-impact 
printers, LCD displays 


HV87 
HV88 


32 


Serial to parallel converter w/ 
latches, polarity and blanking, 
V DD = 5V 


80V 


±20mA 
-5mA 


Tl SN75555/75556 
Sprague UCN5853/5854 


EL column drivers, non-impact 
printers, LCD displays 


HV93 
HV94 


32 


Serial to parallel converter w/ 
latches, output enable, 
V DD = 5V 


80V 


+5mA 
-20mA 


Tl SN75555/75556 
Sprague UCN5853/5854 


EL column drivers, non-impact 
printers, LCD displays 


HV97 
HV98 


32 


Serial to parallel converter w/ 
latches, polarity and blanking, 
V DD = 5V 


80V 


+5mA 
-20mA 


Tl SN75555/75556 
Sprague UCN5853/5854 


Non-impact printers/plotters, 
EL displays, LCD drivers 



High Voltage Sink-Only Outputs (Open Drain N-Channel) 



Device 
Number 


Out- 
puts 


Logic Configuration 


Output 
Operating 
Voltage 


Output 
Current/ 
Channel 


Similar Devices 


Applications 


HV03 
HV05 


64 


Serial to parallel converter w/ 
latches, Supertex logic 


220V 
300V 


+ 100mA 




EL row drivers, non-impact 
printers/plotters 


HV31 


64 


Serial to parallel converter w/ 
output enable 


375V 


+1mA 




Electrostatic printers 


HV51 
HV52 


32 


Serial to parallel converter w/ 
output enable and strobe 


225V 


+100mA 


Tl 75551/75552 
Sprague UCN585 1/5852 


EL row driver, non-impact 
printers/plotters 


HV55 
HV56 


32 


Serial to parallel converter 
latches, polarity and blanking 


220V 
300V 


+ 100mA 


Tl 75551/75552 
Sprague UCN5851/5852 


Non-impact printers/plotters, 
EL row drivers 



High Voltage Source-Only Outputs (Open Drain P-Channel) 



Device 
Number 


Out- 
puts 


Logic Configuration 


Output 
Operating 
Voltage 


Output 
Current/ 
Channel 


Similar Devices 


Applications 


HV41 
HV42 


32 


Serial to parallel converter w/ 
output enable and strobe 


-225V 


-80mA 




EL row drivers, non-impact 
printers 


HV45 
HV46 


32 


Serial to parallel converter 
latches, polarity and blanking 


-220V 
-300V 


-60mA 




Non-impact printers/plotters, 
EL display row drivers 


HV49 


64 


Serial to parallel converter 


-375V 


0.5mA 




Electrostatic printers 



6-6 



Qf) Supertax inc. 



HVCMOS 
Selector Guide 



High Voltage Analog Switches and Multiplexers 



High Voltage Bilateral Switches 



Device 
Number 


Out- 
puts 


Logic Configuration 




■ Vnltana 
I VOI lay e 


Hi itr\i it 

Current/ 
Channel 


un* 
Resistance/ 
Channel 


Applications 


Supply 


Analog 
Signal 


HV10 


4 


Parallel Inputs, latches 


160V 


130V 


±3.0A 


30£J 


Medical ultrasound, HV 
multiplexers, ink-jet printers 


HV12 


8 


Shift register, latches 


160V 


130V 


+1.5A 


35£J 


Medical ultrasound, HV 
multiplexers, ink-jet printers 


HV14 


8 


Decoders, latches, chip select 
and data in 


160V 


130V 


±1.5A 


35Q 


Medical ultrasound, HV 
multiplexers, ink-jet printers 


HV15 


8 


Decoders, latches and 
chip selects 


160V 


130V 


±1 .5A 


35Q 


Medical ultrasound, HV 
multiplexers, ink-jet printers 


HV16 


8 


Shift register, latches 


160V 


130V 


+1.5A 


35£2 


Medical ultrasound, HV 
multiplexers, ink-jet printers 


HV18 


8 


Shift register, latches, and 
clear 


160V 


130V 


±1.5A 


35£2 


Medical ultrasound, HV 
multiplexers, ink-jet printers 



Low-Power High Voltage Bilateral Switches 



Device 
Number 


Out- 
puts 


Logic Configuration 


Operating 


1 Voltage 


Output 
Current/ 
Channel 


On- 
Resistance/ 
Channel 


Applications 


Supply 


Analog 
Signal 


HV204 


8 


Shift register, latches, clear, 
low charge injection 


200V 


180V 


+2.0A 


27Q 


Medical ultrasound, HV 
multiplexers, ink-jet printers 


HV21 


8 


Shift register, latches 


160V 


140V 


±2.0A 


27Q 


Medical ultrasound, HV 
multiplexers, ink-jet printers 


HV22 


8 


Shift register, latches, and 
clear 


160V 


140V 


±2.0A 


27Q 


Medical ultrasound, HV 
multiplexers, ink-jet printers 


HV217 


8 


Shift register, latches, and 
low noise 


160V 1 


140 V 


±2.0A 


25Q 


Medical ultrasound, HV 
multiplexers, ink-jet printers 


HV218 


8 


Shift register, latches and 
low noise 


160V 2 


140V 


±2.0A 


25H 


Medical ultrasound, HV 
multiplexers, ink-jet printers 


HV227 


8 


Shift register, latches, clear 
and low noise 


160V 1 


140V 


±2.0A 


25£i 


Medical ultrasound, HV 
multiplexers, ink-jet printers 


HV228 


8 


Shift register, latches, clear 
and low noise 


160V 2 


140V 


+2.0A 


25£i 


Medical ultrasound, HV 
multiplexers, ink-jet printers 



Notes: 



1 . V PP = 40V to 80V and V pp - V NN = 1 60V. 

2. Vpp = 80V to 1 50V and V pp - V NN = 1 60V. 



6-7 



HVCMOS Selector Guide 



High Voltage Analog Switches 



Device 
Number 


Switches 


Switch Operating 
Voltage 


Max Switch 
Resistance 


Similar Devices 


Applications 


HV341 


Dual SPST 


100V P-P 


110Q 


MAX 341 


High voltage switching, mil 
electronics and instrumentation 


HV343 


Dual SPDT 


100V P-P 


1100 


MAX 343 


High voltage switching, mil 
electronics and instrumentation 


HV345 


Dual DPST 


100V P-P 


110a 


MAX 345 


High voltage switching, mil 
electronics and instrumentation 


HV348 


Dual SPST 


100V P-P 


550 


MAX 348 


High voltage switching, mil 
electronics and instrumentation 



High Voltage Power Supply ICs 
High Voltage Switchmode PWM Controllers with MOSFET 



Device 
Number 


+v IN 

Min 


+v IN 

Max 


Max 
Feedback 
Voltage 


Max 
Duty 
Cycle 


MOSFET 
Switch 

B V DSS 


MOSFET 
Switch 

^DS(ON) 


Similar Devices 


Applications 


HV9100 


10V 


70V 


±1% 


49% 


150V 


5.00 


Siliconix SI9100 
TeledyneTSC9100 


DC/DC converters, 
distributed power systems 


HV9101 


10V 


70V 


±10% 


49% 


150V 


5.00 


Siliconix SI9101 
TeledyneTSC9101 


DC/DC converters, 
distributed power systems 


HV9102 


10V 


120V 


+1% 


49% 


200V 


7.0Q. 


Siliconix SI9102 


DC/DC converters, 
distributed power systems 


HV9103 


10V 


120V 


+1% 


99% 


200V 


7.on 




DC/DC converters, 
distributed power systems 


HV9105 


10V 


120V 


±2% 


49% 


200V 


5.00 


Siliconix SI9105 
PWR-SMP400 


DC/DC converters, 
distributed power systems 


HV9106' 


12V 


450V 


+2% 


49% 


600V 


20.00 


PWR-SMP3 
PWR-SMP210 


DC/DC converters, 
distributed power systems 


HV9108 


10V 


120V 


±2% 


99% 


200V 


5.0Q 




DC/DC converters, 
distributed power systems 


HV9109 1 


12V 


450V 


±2% 


99% 


600V 


20.00 




DC/DC converters, 
distributed power systems 



1 . Consult factory for availability. 



6-8 



HVCMOS Selector Guide 



High Voltage Switchmode PWM Controllers 



Device 


M V ' N 


+v 1N 


Max 
Feedback 

v Ullage 


Max 
Duty 
Cycle 


Similar Devices 


Applications 


HV9110 


10V 


120V 


±1% 


49% 


SiliconixSI9110 
i eieayne iboyniu 


DC/DC converters, 
distributed power systems 


HV91 1 1 


10V 


120V 


±10% 


49% 


Siliconix SI9101 
Tefedyne TS09101 


DC/DC converters, 
distributed power systems 


HV9112 


9V 


80V 


±2% 


49% 


Siliconix SI9122 


DC/DC converters, 
distributed power systems 


HV9113 


10V 


120V 


±1% 


99% 


'. — 


DC/DC converters, 
distributed power systems 


HV9114 1 


11V 


200V 


±1% 


49% 


Siliconix SI9114 


DC/DC converters, 
distributed power systems 


HV9117 1 


11V 


200V 


±1% 


99% 




DC/DC converters, 
distributed power systems 


HV9120 


10V 


450V 


+2% 


49% 


Siliconix SI9120 
Teledyne TSC9116 
PWR-SIVIP520 


DC/DC converters, 
distributed power systems 


HV9123 


10V 


450V 


±2% 


99% 




DC/DC converters, 
distributed power systems 


HV9124, 


12V 


450V 


±1% 


49% 


— 


DC/DC converters, 
distributed power systems 


HV9127 1 


12V 


450V 


±1% 


99% 




DC/DC converters, 
distributed power systems 


HV9220 12 


10V 


450V 


±1% 


49% 




Two- and four-switch fixed frequency 
switchmode power converters 



Notes: 

1 . Consult factory for availability. 

2. Two-output device. 



6-9 



Oft 



DMOS FETs 
Cross Reference* 



Industry 


Supertex 


Industry 


Supertex 


Industry 


Supertex 


Industry 


Supertex 


Part 


Part 


Part 


Part 


Part 


Part 


Part 


Part 


Number 


Number 


Number 


Number 


Number 


Number 


Number 


Number 


2N6659 


2N6659 


2SK409 


TN0620N5 


BSS98 


VN0106N3 


D84DK2 


VN1206N5 


2N6660 


2N6660 


2SK41 1 


VN0360N1 


BST120 


TP0104N8 


D84DL2 


VN1210N5 


2N6661 


2N6661 


2SK428 


VN1206N5 


BST122 


TP0104N8 


IRF320 


VN0340N1 


2N6759 


VN0335N1 


2SK440 


VN1220N5 


BST70A 


VN0109N3 


IRF321 


VN0335N1 


2N6761 


VN0345N1 


2SK441 


VN0650N2 


BST72 


VN1310N3 


IRF322 


VN0340N1 


2N6781 


VN1106N2 


2SK680 


TN0104N8 


BST72A 


VN1310N2 


IRF323 


VN0335N1 


2N6782 


VN1110N2 


AM0610LL 


TN0624N3 


BST74 


TN0620N3 


IRF332 


VN0340N1 


2N7000 


2N7000 


AM10LM 


VN0106N3 


BST74A 


TN0620N3 


IRF333 


VN0335N1 


2N7007 


2N7007 


AM2222LL 


VN0106N3 


BST76 


TN0620N3 


IRF420 


VN0350N1 


2N7008 


2N7008 


AM2222LM 


VN0106N3 


BST76A 


TN0620N3 


IRF421 


VN0345N1 


2N7009 


VN0550N3 


AN0110NA 


AN0116NA 


BST84 


TN2524N8 


IRF422 


VN0350N1 


2N7010 


VN2206N3 


AN0120NA 


AN0120NA 


BST86 


TN2524N8 


IRF423 


VN0345N1 


2N701 1 


VN2206N3 


AN0130NA 


AN0130NA 


BUZ20 


VN1210N5 


IRF432 


VN0350N1 


2N7014 


VN1110N5 


AN0140NA 


AN0140NA 


BUZ30 


VN1220N5 


IRF433 


VN0345N1 


2SJ101 


VP1204N5 


AP0120NA 


AP0120NA 


BUZ40 


VN0350N5 


IRF510 


VN1210N5 


2SJ102 


VP1206N5 


AP0130NA 


AP0130NA 


BUZ42 


VN0350N5 


IRF511 


VN1206N5 


2SJ117 


VP0340N5 


AP0140NA 


AP0140NA 


BUZ43 


VN0350N1 


IRF512 


VN1210N5 


2SJ121 


VP1204N5 


BS107 


VN0120N3 


BUZ46 


VN0350N1 


IRF513 


VN1206N5 


2SJ76 


VP0116N5 


BS107P 


VN0120N3 


BUZ60B 


VN0340N5 


IRF520 


VN1210N5 


2SJ77 


TP0616N5 


BS107PT 


VN1320N3 


BUZ63B 


VN0340N1 


IRF521 


VN1206N5 


2SJ78 


VP1220N5 


BS170 


VN0106N3 


BUZ72 


VN1210N5 


IRF522 


VN1210N5 


2SJ79 


VP0120N5 


BS170P 


VN0106N3 


BUZ72A 


VN1210N5 


IRF523 


VN1206N5 


2SJ79K 


VP0120N5 


BS229 


TN0624N3 


BUZ73A 


VN1220N5 


IRF530 


VN1210N5 


2SK196H 


VN0116N2 


BS250 


VP0106N3 


BUZ74 


VN0350N5 


IRF531 


VN1206N5 


2SK213 


TN0620N5 


BS250P 


VP0106N3 


BUZ74A 


VN0350N5 


IRF532 


VN1210N5 


2SK214 


TN0620N5 


BSR78 


TP0604N3 


BUZ76 


VN0340N5 


IRF533 


VN1206N5 


2SK215 


TN0620N5 


BSS100 


TN0610N3 


BUZ76A 


VN0340N5 


IRF710 


VN0340N5 


2SK216 


TN0620N5 


BSS101 


TN0524N3 


D80AK2 


TN0606N3 


IRF711 


VN0335N5 


2SK216K 


TN0620N5 


BSS110 


VP0106N3 


D80AL2 


TN0610N3 


IRF712 


VN0340N5 


2SK259 


VN0335N1 


BSS124 


TN0640N3 


D80AM2 


TN0620N3 


IRF713 


VN0335N5 


2SK260 


VN0340N1 


BSS125 


VN0660N3 


D80AN2 


TN0620N3 


IRF720 


VN0340N5 


2SK294 


VN1210N5 


BSS129 


TN0624N3 


D84BK2 


VN1206N5 


IRF721 


VN0335N5 


2SK295 


VN1210N5 


BSS135 


VN0660N3 


D84BL2 


VN1210N5 


IRF722 


VN0340N5 


2SK296 


VN0335N5 


BSS149 


TN0624N3 


D84BM2 


VN1216N5 


IRF723 


VN0335N5 


2SK298 


VN0340N1 


BSS192 


TP2520N8 


D84BN2 


VN1220N5 


IRF732 


VN0340N5 


2SK302 


TN0104N8 


BSS192 


TP2520N8 


D84BQ1 


VN0335N5 


IRF733 


VN0335N5 


2SK310 


VN0340N5 


BSS229 


TN0624N3 


D84BQ2 


VN0340N5 


IRF820 


VN0350N5 


2SK311 


VN0345N5 


BSS250 


VP0106N3 


D84CK2 


VN1206N5 


IRF821 


VN0345N5 


2SK319 


VN0340N5 


BSS295 


VN2206N3 


D84CL2 


VN1210N5 


IRF822 


VN0350N5 


2SK345 


VN1204N5 


BSS296 


VN2210N3 


D84CM2 


VN1216N5 


IRF823 


VN0345N5 


2SK346 


VN1206N5 


BSS297 


TN0620N3 


D84CN2 


VN1220N5 


IRF832 


VN0350N5 


2SK382 


VN0350N5 


BSS87 


TN2524N8 


D84CQ1 


VN0335N5 


IRF833 


VN0345N5 


2SK383 


VN1210N5 


BSS88 


TN0624N3 


D84CQ2 


VN0340N5 


IRF9510 


VP1210N5 


2SK402 


VN0340N1 


BSS89 


TN0620N3 


D84CR1 


VN0345N5 


IRF9511 


VP1206N5 


2SK408 


TN0620N5 


BSS92 


TP0620N3 


D84CR2 


VN0350N5 


IRF9512 


VP1210N5 



The Supertex devices are a "form, fit, and function" replacement for the industry standard part types, but subtle differences in characteristics and/or specifications may exist. 

6-10 



DMOS FETs Cross Reference 



Industry 


Supertex 


Industry 


Supertex 


Industry 


Supertex 


Industry 


Supertex 


Part 


Part 


Part 


Part 


Part 


Part 


ran 


Part 


Number 


Number 


Number 


Number 


Number 


Number 


Number 


Number 


IDrQCI O 

1 nryo I O 


v r I tUONO 


rvir ty i u 


\/M1 nk'MQ 
VIM I UMNy 


IVI I rolN*HJ 


V INUO'tUNu 


□ CI 1 D1 A 

HrLl r 1 U 


TDAftl AMO 

1 rUb 1 UNt: 


IRF9520 


VP1210N5 


MFE9200 


VN2406L 


MTP4N08 


VN1110N5 


RFL2N05 


VN1106N2 


IRF9521 


VP1206N5 


MFE930 


TN0604N2 


MTP4N10 


VN1110N5 


RFL2N06 


VN1106N2 


IRFQo99 


wpi 91 o.mc 

vr It I UlNO 


MCFQftA 

ivircyou 


TMAft("tftM9 
I NUOUOINt 


^ylXPc;MA(^ 
ivi i roiNUO 


\/M1 1 AftKlft 
VN I I UOlNO 


□ Ch/IOM/1 C 

nrlvloN40 


V/MAO/1 Chi 1 

VNUO40N I 




\/P1 90.fiMC 
V r I tUOINO 


ivir cyyu 


TMAftl AM9 
1 INUD 1 UINt 


HATPf^MAft 

ivi i roiNUO 


\/M1 OAftMC 
VN I tUONO 


DCMQMCA 

ririVloNOU 


V/MAOCAM 1 

VNUooUN I 




\/P1 91 nwc 

Vr l£ I UlNO 


ivirvj i uuuu 


1 INUOUOIN / 


ivi I roiNUO 


\/M1 91 AMC 
V IN 1 1 I UNO 


QQlM MOC 

ririvi4N00 


V/MAOOCM1 

VNUoooNl 


IRF9533 


VP1206N5 


MFQ170P 


TN0606N6 


MTP8N10 


VN1210N5 


RFM4N40 


VN0340N1 


IRF9612 


VP1120N5 


MFQ6660C 


TN0606N7 


MTP8P08 


VP1210N5 


RFP12N08 


VN1210N5 


IRFQP.1 9. 
inryo i o 


\/Pi 1 1 ami; 

Vrl I I OINO 


MFOCCftAD 
IVirUDDDUr 


TMACnftMC 
1 NUOUONO 


MTDAD1 A 

IVI I ror l U 


\/D1 01 AMC 

Vrl 1 1 UNO 


□ CD1 OK1 1 A 

HrrltiN 1U 


\/M 1 Ol AMC 

VNl^lUNo 


IRFF1 10 


WMi 910M9 
VlN It I UINt 


ivirwooo i r 


V W 1 UUDJ 


iviatoou 


TM9£9/1 Mfl 
1 INtOt^-NO 


□CP1 CMAC 

nrr I ONUO 


\/KH OARMC 
VN I^UuNO 


IRFF1 1 1 


v 1 N 1 tUUI Nt 


ivir rtou 


V IN 1 O 1 UlNO 


H/IYPCAA 

iviatouu 


1 INtOt*fNO 


PCP1 CM Aft 

nrr I ONUO 


\/M1 OACMC 
VN \ tUONO 


IRFF112 


VN1110N2 


MPF481 


VN1310N3 


MXF930 


TN0104N8 


RFP1N35 


VN0635N5 


IRFF113 


VN1106N2 


MPF500 


VN0550N3 


MXF960 


TN0104N8 


RFP1N40 


VN0640N5 


irffi on 
inrr I c\} 


\/M1 91 AM9 
V IN I t I UINt 


MPPfiCCO 
MrrDDDy 


l NUOU4NO 




TMOCOyl MO 

I NtO£4No 


□CDOM AD 


TMflC^ AMC 

I Nubl UNO 


IRFF191 
inrr i c. i 


V IN i tUOINt 


ivir rooou 


TMACACMO 
1 NUOUONO 


r ivi i uu 1 1_ 


TMAftl AMO. 
1 NUOl UlNO 


□ CDOK1 1 A 


WMI 1 1 AMC 

VNl 1 1 UNo 


IRFF1 22 


WMI 91 AMO 
VIN It I UINt 


ivirrooo i 


1 INUD 1 UNO 


PM1 AA9I 

r ivi i uut l 


TMAftl AMQ 
1 NUO 1 UNO 


DCDOM1 Q 

nr rjiNl 


\/Mi 1 OAMC 

VNl lt!UNo 


IRFF123 


VN1206N2 


MPF910 


VN0106N3 


PM1003P 


VN1110N5 


RFP2N20 


VN1120N5 


IRFF130 


VN1210N2 


MPF9200 


TN0620N3 


PM1004P 


VN1110N5 


RFP2P08 


TP0610N5 


IRFP1 9.1 

inrr i o i 


\/M1 9AftM9 
V IN I tUOINt 


mpcqoa 
ivirryou 


TMACA/1 MO 
1 NUOU4N0 


rM I UUor 


\/M1 AMC 
VN \<L I UNO 


□CDOD1 A 


TD(1C1 AMC 

I rUbl UNO 


|Pjpp-| 32 


\/M1 910M9 
v IN I t I UINt 


ivirryou 


1 INUDUDNO 


DM1 A1 AP 

r IVI I u i ur 


\/M1 01 AMC 
VN I d\ UNO 


□ CDOM A C 

nrroN4o 


WMAO A CMC 

VNUo4oNo 


I PPP1 oq 
inrr I oo 


\/M1 91 HMO 
v IN I t I UINt 


ivirryyu 


1 INUD 1 UNO 


DM1 OA1 I 
rM I tU I L 


TMACOAMQ 

I NUo^UNo 


□ CDOhICA 

HrroNoU 


\ /MAOCAMC 

VnUooUNo 


IRFF210 


VN2220N2 


MTM2N45 


VN0345N1 


PM503L 


TN0606N3 


RFP4N05 


VN1106N5 


IRFF211 


VN2220N2 


MTM2N50 


VN0350N1 


PM506L 


TN0606N3 


RFP4N06 


VN1106N5 


IRFF91 9 
Inrr^ I t 


\/M1 1 onMo 
V IN I 1 1 UN t 


mtmop/i c 
Ivl l Mtr40 


VrUo40lNl 


rMOUyr 


V/KM OACMC 

VN I *:UoNo 


nrn<i moc 

Hrr4Noo 


VNOoooNo 


IRFF91 9 




MTMODCA 

M I IVI<£rOU 


VrUooUN I 


rMbl Ur 


VN120ONO 


RFP4N40 


Vn0340No 


Inrr^U 




MTMOMOC 
M I MoNoO 


VNUOOOINl 


DMC1 OD 

rlvlol^r 


\/M1 OACMC 

VNltiUONO 


□ CDC O AO 

HrroPOo 


\ IOA OH AMC 

VP1210N5 


IRFF221 


VN2220N2 


MTM3N40 


VN0340N1 


PM601L 


VN0106N3 


RFP6P10 


VP1210N5 


IRFF222 


VN2220N2 


MTP10N05 


VN1206N5 


PM602L 


TN0606N3 


RFP8P08 


VP1210N5 


IRPPOQQ 


\/M999flN9 
VINtttUlNt 


MTP1 nMfM? 
IVI I r I UNUO 


\/mi oriftMt; 
VIN I tUDlNO 


D^J^CAQ^ 
rmbUoL 


TM AC Aft MO 
I NUOUONO 


DCDOD1 A 

Hrror 10 


\ /OH OH AMC 

VP1210N5 


IRPPOOO 


\/M999flM9 
V INtttUINt 


mtpi nMnp 
IVI I r 1 UNUo 


\/M1 o-\ nMc 
VlNl *l1 UlNO 


DMCA/1 D 

r!Vlou4r 


\/M1 1 AftMC 

VN I lUoNO 


on 1 1 AAPU D 

bUl lOOOrlr 


V/MAC itCMn 

VNUo4oND 


IRFF999 


\/M999flM9 

vn^^un*: 


mtpi nMm 
Ivl I rl UN1U 


\/M1 Oi AMC 
V IN 1 1 1 UlNO 


rMoUor 


\/M1 OACMC 

VN1 tiUbNo 


bU1 100HU 


\ /MAC A C MO 

VN0545N2 


IRFF310 


VN0340N2 


MTP12N05 


VN1206N5 


PM606L 


TN0606N3 


SD1101BD 


VN0640N3 


IRFF311 


VN0335N2 


MTP12N06 


VN1206N5 


PM608P 


VN1206N5 


SD1101CHP 


VN0540ND 


IRPPO-IO 

InrrJ 1 t 


V INUO*HJINt 


mtpi 9Maq 
ivi i r i sl inuo 


\/M 191 OMR 
VlNl d. I UNO 


PMRAQP 


\/M1 OACMC 
VlNl <iUoN0 


cm 1 ai uin 
oUl 1 U 1 HL) 


W MAC /l AMO 

VN0b40N2 


IRPPO-I O 

inrro i o 


WMAoqcMO 
V INUoODIN t 


MTP1 9Min 

IVI I rl^NlU 


\/M1 01 AMK 
VIN 1^1 UNO 


rIVIoUyn 


\/M1 OACMC 

VNI^UoNo 


om 1 noon 
bul 102dU 


\ IK 1 ACOCK IO 

VN0635N3 


IRPpoon 


WMAO/f AMO 
VNUo4UN*l 


MTD1 CMAC 

IVI 1 rl ONUO 


VN 1 tiUONO 


DhXftl AD 

KMblur 


\/M1 OACMC 


SD1 102CHP 


» tK loco cik tr\ 

VN0635ND 


IRFF321 


VN0335N2 


MTP15N06 


VN1206N5 


PM612P 


VN1206N5 


SD1102HD 


VN0635N2 


IRFF322 


VN0340N2 


MTP1N45 


VN0645N5 


PM614P 


VN1206N5 


SD1104BD 


TN0610N3 


IRPpooq 


V INUOOOINt 


mtpi Men 
ivi i r i inou 


VNUoOUinO 


□ MQA1 | 

rMoUl L 


\/MA1 AQMO 

VNU1 UiJNo 


om i t\A r\r\ 
bUl 104UU 


X/MAH AAMA 

VN0109N9 


IRPPOOO 


V INU04UINt 


MTP1 MKR 
IVI I r 1 NOO 


VNUoOOInO 


DMQAOI 


TMAC1 AMO 


o m i f\A lj n* 
bUl 104HD 


TMOCH OMO 

TN0610N2 


IRFF999 


WMAQ9CM9 
VNUOOONt 


»iTDi mca 
IVI I r I NbU 


\/MAQftAMC 

VInUooUInO 


rMoUor 


\/M1 01 AMC 

VNl £\ UNO 


o rm i nccn 
bD1 105BD 


TMOCH OMO 

TN0610N3 


IRFF420 


VN0350N2 


MTP20N08 


VN1210N5 


PM808P 


VN1210N5 


SD1105DD 


VN0109N9 


IRFF421 


VN0345N2 


MTP20N10 


VN1210N5 


PM814P 


VN1210N5 


SD1105HD 


TN0610N2 


IRFFA99 
Inrr4tt 


VINUOOUNt 


MTDOMOC 

IVI 1 r^ilMoo 


\/Mr>OOCMC 

VNUooONO 


□ CI 1 MAD 

HrL i Inuo 


TMAC1 AMO 
I NUO IUN2 


PHH H A£? A l~\ 

bD1 106AD 


V / M AH OCK IO 

VN0106N3 


IRFF499 


wmao,ic.mo 

V INU040INt 


IVI 1 rtN4U 


\/MAQ/1 AMC 
VNUO4UN0 


np H KM A 

HrL I IM I U 


TMAC1 AMO 
1 NOo 10N2 


Om 1 ACAUD 

bDI 106OHP 


VN0106ND 


IRFC^QI 1 9 


1 rUDUOIN / 


ivi i rtN40 


\/MI*10/1 CMC 
V InUO^OInO 


□ CI 1 M 1 O 

rirLi n i d. 




bUl IUoUU 


VN0106N9 


IRFS1Z0 


TN2524N8 


MTP2N50 


VN0350N5 


RFL1N15 


VN2220N2 


SD1107BD 


TN0110N3 


IRFS1Z3 


TN0104N8 


MTP2P45 


VP0345N5 


RFL1N18 


VN1120N2 


SD1107CHP 


TN0110ND 


MFE350 


VN0535N2 


MTP2P50 


VP0350N5 


RFL1N20 


VN1120N2 


SD1107DD 


VN0109N9 


MFE500 


VN0550N2 


MTP3N35 


VN0335N1 


RFL1P08 


TP0610N2 


SD1107HD 


TN0110N2 



•The Supertex devices are a "form, fit, and function" replacement for the industry standard part types, but subtle differences in characteristics and/or specifications may exist. 



6-11 



DMOS FETs Cross Reference 



Industry 


Supertex 


Industry 


Supertex 


Industry 


Supertex 


Industry 


Supertex 


Part 


Part 


Part 


Part 


Part 


Part 


Part 


Part 


Number 


Number 


Number 


Number 


Number 


Number 


Number 


Number 


SD1 107N 


VQ1000N6 


SN0130NA 


AN0130NA 


VN1706L 


VN1706L 


VND011B 


VN1210N2 


SD1112BD 


TN0620N3 


SN0130NB 


AN0130NB 


VN1706M 


VN1706L 


VNE010B 


VN1210N2 


SD1112HD 


TN0620N2 


SN0140NA 


AN0140NA 


VN1710L 


VN1710L 


VNE011B 


VN1210N2 


SD1113BD 


TN0520N3 


SN0140NB 


AN0140NB 


VN1710M 


VN1710L 


VP0104N3 


VP0104N3 


SD1113CHP 


TN0520ND 


SN7000 


2N7000 


VN2010L 


VN2010L 


VP0104ND 


VP0104ND 


SD1 1 13HD 


TN0520N2 


SP0610L 


VP0106N3 


VN2222KM 


VN2222LL 


VP0106N3 


VP0106N3 


SD1114BD 


VN0109N3 


TN0106N3 


TN0106N3 


VN2222L 


VN2222LL 


VP0106ND 


VP0106ND 


SD1114DD 


VN0109N9 


TN0106ND 


TN0106ND 


VN2222LL 


VN2222LL 


VP0109N3 


VP0109N3 


SD1114HD 


VN0109N2 


TN01 10N3 


TN01 10N3 


VN2222LM 


VN2222LL 


VP0109ND 


VP0109ND 


O i~v j u j r- r~> r™\ 

SD1 1 15BD 


VN0109N3 


TN01 10ND 


"I-* 1 /"\ A JAM |~\ 

TN01 10ND 


\ /K IAAAAI II Jl 

VN2222LM 


VN1306N3 


VP0300B 


VP0300B 


SD1 1 15DD 


VNO 109N9 


TZ400BD 


\ / P\ I r\ A A Jl MA 

VN0104N3 


VN2406B 


VN2406B 


VP0300L 


VP0300L 


SD1115HD 


VN0109N2 


TZ402BD 


VN1304N3 


VN2406D 


VN2406D 


VP0300M 


VP030OL 


SD1117BD 


TN0606N3 


TZ403BD 


VN1304N3 


VN2406L 


VN2406L 


VP0535N3 


VP0535N3 


SD1 1 17DD 


VN0106N9 


TZ404BD 


VN1304N3 


VN2406M 


VN2406L 


VP0535ND 


VP0109ND 


SD1 1 17HD 


TN0606N2 


TZ404CY 


TN0104N8 


VN2410L 


VN2410L 


VP0535ND 


VP0535ND 


O P"\ H H H7M 

SD1 117N 


VQ1001J 


1 1 PM P il A A 

UFNF433 


VN0345N2 


VN2410M 


VN2410L 


VP0540L 


VP0640N5 


SD1122BD 


TN0520N3 


VN01000D 


VN1210N5 


VN30ABA 


VN0104N2 


VP0540N3 


VP0540N3 


SD1122CHP 


TN0520ND 


VN0104N3 


VN0104N3 


VN3501A 


VN0335N1 


VP0540ND 


VP0540ND 


SD1 124BD 


VN0106N3 


VN0104ND 


VN0104ND 


VN3501D 


VN0335N5 


VP0610L 


VP0106N3 


SD1 127BD 


VN0106N3 


VN0106N3 


VN0106N3 


VN3515L 


VN3515L 


VP0614L 


VP0106N3 


SD1 127CHP 


VN0106ND 


VN0106ND 


VN0106ND 


VN35AB 


TN0606N2 


VP0808B 


VP0808B 


SD1137BD 


TN0606N3 


VN0109N3 


VN0109N3 


VN35AK 


TN0606N2 


VP0808L 


VP0808L 


SD1137CHP 


TN0606ND 


VN0109ND 


VN0109ND 


VN4001A 


VN0340N1 


VP0808M 


VP0808L 


SD1200CHP 


VN0545ND 


VN0300D 


VN0300D 


VN4001D 


VN0340N5 


VP1008B 


TP0610N2 


SD1201BD 


VN0540N3 


VN0300L 


VN0300L 


VN4012L 


VN4012L 


VP1008L 


VP1008L 


SD1201CHP 


VN0540ND 


VN0300M 


VN0300L 


VN40AD 


VN0104N5 


VP1008M 


TP0610N3 


SD1202BD 


TN0520N3 


VN0401D 


VN1204N5 


VN4502A 


VN0345N1 


VQ1000J 


VQ1000N6 


SD1202CHP 


TN0520ND 


VN0601D 


VN1206N5 


VN4502D 


VN0345N5 


VQ1000P 


VQ1000N7 


SD1500BD 


VN0660N3 


VN0606M 


VN0606LL 


VN46AD 


VN0104N5 


VQ1001J 


TN0606N6 


SD1500CHP 


VN0660ND 


VN0610L 


VN0610LL 


VN5002A 


VN0350N1 


VQ1001P 


VQ1001P 


SD1501BD 


VN0655N3 


VN0610LL 


VN0610LL 


VN5002D 


VN0350N5 


VQ1004J 


VQ1004J 


SD1501CHP 


VN0660ND 


VN0801 D 


VN1210N5 


VN6035L 


VN6035L 


VQ1004P 


VQ1004P 


SD204CHP 


VN2106ND 


VN0808M 


VN0808L 


VN66AD 


VN0106N5 


VQ2000J 


TP0606N6 


SD204HD 


\ /MA1 r\ 4MA 

VN0104N3 


VN10KE 


VN0106N9 


VN66AK 


VN0106N2 


VQ2000P 


VQ2006P 


SD2107BD 


\ / a r\r\K ir\ 

VP0109N3 


\ IK t A Al/K A 

VN10KM 


VN10KN3 


VN67AA 


VN0106N5 


VQ2001J 


TP0604N6 


SD2107CHP 


TP0610ND 


VN10KMA 


VN10KN3 


VN67AB 


VN0106N2 


VQ2001 P 


VQ2001 P 


SD2107DD 


VP0109N9 


VN10KN3 


VN10KN3 


VN67ABA 


VN0106N2 


VQ2004J 


TP0606N6 


SD2107HD 


TP0610N2 


VN10LE 


VN0106N9 


VN67AD 


VN0106N5 


VQ2004P 


VQ2006P 


r-» i-n s-\ a pi P"\ 

SD2204BD 


VP0540N3 


1 It 1 J rt| JL Jl 

VN10LM 


VN10KN3 


VN67AK 


VN0106N2 


VQ2006J 


TP0606N6 


SD2204CHP 


VP0540ND 


VN10LM 


VN10KN3 


VN88AD 


VN0109N5 


VQ2006P 


VQ2006P 


SD3300BD 


\ imaaj r\K in 

VN2210N3 


VN10LP 


VN1306N3 


VN89ABA 


VN0109N2 


VQ3001J 


VQ3001N6 


SD3300CHP 


VN2210ND 


VN1206B 


VN1206B 


VN89AD 


VN0109N5 


VQ3001 P 


VQ3001N7 


SD3300HD 


TN0610N2 


VN1206D 


VN1206D 


VN90AB 


VN0109N2 


VQ7254J 


VQ7254N6 


SD3301 BD 


TN0604N3 


VN1206L 


VN1206L 


VN90ABA 


VN0109N2 


VQ7254P 


VQ7254N7 


SD3301CHP 


V IK innnAl 1 r\ 

VN2206ND 


\ IKi A r\r\/-K n 

VN1206M 


VN1206L 


VN98AK 


VN0109N2 


ZVN01 04A 


VN0104N3 


SD3301 HD 


TN0604N2 


VN1210L 


VN1210L 


VN99AB 


VN0109N2 


ZVN0104B 


VN0104N2 


SD5101N 


VN1304N6 


VN1210M 


VN1210L 


VN99AK 


VN0109N2 


ZVN0104L 


VN0104N5 


SGSP531 


VN0340N1 


VN1216B 


VN2216N2 


VNC010B 


VN1206N2 


ZVN0106A 


VN0106N3 


SN0120NA 


AN0120NA 


VN1706B 


VN1706B 


VNC011B 


VN1206N2 


ZVN0106B 


VN0106N2 


SN0120NB 


AN0120NB 


VN1706D 


VN1706D 


VND010B 


VN1210N2 


ZVN0106L 


VN0106N5 



"The Supertex devices are a "form, fit, and function" replacement for the industry standard part types, but subtle differences in characteristics and/or specifications may exist. 



6-12 



DMOS FETs Cross Reference 



Industry 


Supertex 


Industry 


Supertex 


Industry 


Supertex 


Industry 


Supertex 


Part 


Part 


Part 


Part 


Part 


Part 


Part 


Part 


Number 


Number 


Number 


Number 


Number 


Number 


Number 


Number 


ZVN0108A 


VN0109N3 


ZVN0335B 


VN0335N2 


ZVN1135M 


VN0335N1 


ZVN1410A 


VN1310N3 


ZVN0108B 


VN0109N2 


ZVN0335L 


VN0335N5 


ZVN1140B 


VN0340N2 


ZVN1410B 


VN1310N2 


ZVN0108L 


VN0109N5 


ZVN0335M 


VN0335N1 


ZVN1140L 


VN0340N5 


ZVN1414A 


VN0116N3 


ZVN0109A 


VN0109N3 


ZVN0340B 


VN0340N2 


ZVN1140M 


VN0340N1 


ZVN1414B 


VN0116N2 


ZVN0109A 


VN0109N3 


ZVN0340L 


VN0340N5 


ZVN1145B 


VN0345N2 


ZVN1416A 


VN0116N3 


ZVN0109B 


VN0109N2 


ZVN0340M 


VN0340N1 


ZVN1145L 


VN0345N5 


ZVN1416B 


VN1316N2 


ZVN0109L 


VN0109N5 


ZVN0345B 


VN0345N2 


ZVN1145M 


VN0345N1 


ZVN1420A 

£— V 1 V 1 'L \-l t\ 


VN0120N3 


ZVN0110A 


VN1310N3 


ZVN0345L 


VN0345N5 


ZVN11A2B 


VN1204N2 


ZVN1420B 


VN0120N2 


ZVN0110B 


VN1310N2 


ZVN0345M 


VN0345N1 


ZVN11A2L 


VN1204N5 


ZVN2106A 


TN0606N3 


ZVN0110L 


TN0610N5 


ZVN0350L 


VN0350N5 


ZVN11A3B 


VN1204N2 


ZVN2106B 


TN0606N2 


ZVN0114A 


TN0620N3 


ZVN0350M 


VN0350N1 


ZVN11A3L 


VN1204N5 


ZVN2106L 


TN0606N5 


ZVN0114B 


TN0620N2 


ZVN0355B 


VN0355N2 


ZVN1204B 


VN1204N2 


ZVN2110A 


TN0610N3 


ZVN0114L 


TN0620N5 


ZVN0355L 


VN0355N5 


ZVN1204L 


VN1204N5 


ZVN2110B 


TN0610N2 


ZVN0116A 


VN0116N3 


ZVN0355M 


VN0355N1 


ZVN1206B 


VN1206N2 


ZVN2110L 


TN0610N5 


ZVN0116B 


VN0116N2 


ZVN0360B 


VN0360N2 


ZVN1206L 


VN1206N5 


ZVN2120A 


VN0120N3 


ZVN0116L 


VN0116N5 


ZVN0360L 


VN0360N5 


ZVN1208B 


VN1210N2 


ZVN2120B 


VN0120N2 


ZVN01 1 7TA 


VN0120N3 


ZVN0360M 


VN0360N1 


ZVN1208L 


VN1210N5 


ZVN2120CSM 


TN2524N8 


ZVN0120A 


VN0120N3 


ZVN0450M 


VN0350N1 


ZVN1209B 


VN1210N2 


ZVN2120L 


VN0120N5 


ZVN0120B 


VN0120N2 


ZVN0530A 


VN0535N3 


ZVN1209L 


VN1210N5 


ZVN2206B 


VN1206N2 


ZVN0120L 


VN0120N5 


ZVN0530B 


VN0535N2 


ZVN1210B 


VN1110N2 


ZVN2206L 


VN1206N5 


ZVN0124A 


TN0524N3 


ZVN0535A 


VN0535N3 


ZVN1210L 


VN1110N5 


ZVN2210B 


VN1110N2 


ZVN0124B 


TN0524N2 


ZVN0535B 


VN0635N2 


ZVN1214B 


VN2220N2 


ZVN2210L 

£— v i v * < i \j i_ 


VN1 1 IONS 

VIII 1 1 Ul u 


ZVN0124L 


TN0624N5 


ZVN0535L 


VN0635N5 


ZVN1220B 


VN2220N2 


ZVN2220B 


VN1120N2 


ZVN01A2A 


TN0102N3 


ZVN0540A 


VN0540N3 


ZVN12A2B 


VN1204N2 


ZVN2220L 


VN1120N5 


ZVN01A2B 


TN0602N2 


ZVN0540B 


VN0540N2 


ZVN12A3B 


VN1204N2 


ZVN2224B 


TN0624N2 


ZVN01A2L 


VN0300D 


ZVN0540L 


VN0640N5 


ZVN12A3L 


VN1204N5 


ZVN2224L 


TN0624N5 


ZVN01 A3B 


TN0604N2 








VN1 ?fl4NI3 

V IV 1 OVJ*TlVw 


Z_ v 1 1L. JJ 


V 1 lujuj liu 


ZVN01A3L 


TN0606N5 


ZVN0545B 


VN0545N2 


ZVN1304B 


VN1304N2 


ZVN2535B 


VN0535N2 


ZVN0204B 


TN0104N2 


ZVN0545L 


VN0645N5 


ZVN1306A 


VN1306N3 


ZVN2535L 


VN0535N5 


ZVN0204L 


TN0606N5 


ZVN1104B 


TN0604N2 


ZVN1306B 


VN1306N2 


ZVN3210L 


VN1210N5 


ZVN0206B 


TN0606N2 


ZVN1104L 


VN1106N5 


ZVN1308A 


VN1310N3 


ZVN3220L 


VN2220N5 


ZVN0206L 


TN0606N5 


ZVN1106B 


VN1106N2 


ZVN1308B 


VN1310N2 


ZVN3306A 


VN0106N3 


ZVN0208B 


TN0610N2 


ZVN1106L 


VN1106N5 


ZVN1309A 


VN1310N3 


ZVN3306B 


VN0106N2 


ZVN0208L 


TN0610N5 


ZVN1108B 


VN1110N2 


ZVN1309B 


VN1310N2 


ZVN3310A 


VN1310N3 


ZVN0209B 


TN0610N2 


ZVN1108L 


VN1110N5 


ZVN1310A 


VN1310N3 


ZVN3310B 


VN1310N2 


ZVN0209L 


TN0610N5 


ZVN1109B 


VN1110N2 


ZVN1310B 


VN1310N2 


ZVN3320A 


VN0120N3 


ZVN0210B 


TN061 0N2 


ZVN1109L 


VN1 1 10N5 


ZVN1314A 


VN01 16N3 


7VN3320R 

i— V 1 1-J JL.UU 


Vllu 1 L.UI lO 


ZVN0210L 


TN0610N5 


ZVN1110B 


TN0610N2 


ZVN1314B 


VN0116N2 


ZVN4206A 


TN0606N3 


ZVN0214B 


TN0620N2 


ZVN1110L 


TN0610N5 


ZVN1316A 


VN1316N3 


ZVNL120A 


VN0120N3 


ZVN0216B 


TN0620N2 


ZVN1114B 


VN2220N2 


ZVN1316B 


VN1316N2 


ZVNL535A 


VN0535N3 


ZVN0216L 


TN0620N5 


ZVN1114L 


VN2220N5 


ZVN1320A 


VN1320N3 


ZVP0104A 


VP0104N3 


ZVN0220B 


TN0620N2 


ZVN1116B 


VN1116N2 


ZVN1320B 


VN1320N2 

V 11 1 JLUI 1L 


ZVP0104B 

L.V 1 \J \ u*tu 




ZVN0220L 


TN0620N5 


ZVN1116L 


TN0620N5 


ZVN1404A 


VN1304N3 


ZVP0104L 


VP0104N5 


ZVN02A2B 


TN0602N2 


ZVN1120B 


VN1120N2 


ZVN1404B 


VN1304N2 


ZVP0106A 


VP0106N3 


ZVN02A2L 


VN0300D 


ZVN1120L 


VN1120N5 


ZVN1406A 


VN1306N3 


ZVP0106B 


VP0106N2 


ZVN02A3B 


TN0604N2 


ZVN1130B 


VN0335N2 


ZVN1406B 


VN1306N2 


ZVP0106L 


VP0106N5 


ZVN02A3L 


VN0300D 


ZVN1130L 


VN0335N5 


ZVN1408A 


VN1310N3 


ZVP0108A 


VP0109N3 


ZVN0330B 


VN0335N2 


ZVN1130M 


VN0335N1 


ZVN1408B 


VN1310N2 


ZVP0108B 


VP0109N2 


ZVN0330L 


VN0335N5 


ZVN1135B 


VN0335N2 


ZVN1409A 


VN1310N3 


ZVP0108L 


VP0109N5 


ZVN0330M 


VN0335N1 


ZVN1135L 


VN0335N5 


ZVN1409B 


VN1310N2 


ZVP0109A 


VP0109N3 



•The Supertex devices are a "form, fit, and function- replacement for the industry standard part types, but subtle differences in characteristics and/or specifications may exist. 



6-13 



DMOS FETs Cross Reference 



Industry 

Part 
Number 



Supertex 

Part 
Number 



Industry 

Part 
Number 



Supertex 

Part 
Number 



Industry 

Part 
Number 



Supertex 

Part 
Number 



Industry 

Part 
Number 



Supertex 

Part 
Number 



ZVP0109B 
ZVP0109L 
ZVP0110A 
ZVP0110B 
ZVP0110L 

ZVP0120A 
ZVP0120B 
ZVP0120L 
ZVP0204A 
ZVP0204B 

ZVP0206A 
ZVP0206B 
ZVP0208A 



VP0109N2 
VP0109N5 
VP0109N3 
VP0109N2 
VP0109N5 

VP0120N3 
VP0120N2 
VP0120N5 
TP0606N3 
TP0606N2 

TP0606N3 
TP0606N2 
TP0610N3 



ZVP0208B 
ZVP0535A 
ZVP0535B 
ZVP0535L 
ZVP0540A 

ZVP0540B 
ZVP0545A 
ZVP0545B 
ZVP0545L 
ZVP1320A 



TP0610N2 
VP0535N3 
VP0535N2 
VP0635N5 
VP0540N3 

VP0540N2 
VP0545N3 
VP0545N2 
VP0645N5 
VP1320N3 



ZVP1320B 
ZVP2106A 
ZVP2106B 
ZVP2106L 
ZVP2110A 

ZVP2110B 
ZVP2110L 
ZVP2120A 
ZVP2120B 
ZVP2120L 



VP1320N2 
TP0606N3 
TP0606N2 
TP0606N5 
VP0109N3 

VP0109N2 
TP0610N5 
VP0120N3 
VP0120N2 
VP0120N5 



ZVP2206B 
ZVP2206L 
ZVP2210B 
ZVP2210L 
ZVP2220B 

ZVP2220L 
ZVP3306A 
ZVP3306B 
ZVP3310A 
ZVP3310B 



VP1206N2 
VP1206N5 
VP1110N2 
VP1110N5 
TP0620N2 

TP0620N5 
VP0106N3 
VP0106N2 
VP1310N3 
VP1310N2 



•The Supertex devices are a "form, fit, and function" replacement for the industry standard part types, but subtle differences in characteristics and/or specifications may exist. 

6-14 



Alphanumeric Index and Ordering Information 




rtMOtt MMtarwfT *oj t«no & Corporate Profile 


wm 


Applications Notes 


mm 


Quality Assurance and Handling Procedures 


mm 


Process Flow 


vm 


Selector Guides and Cross Reference 




N- and P-Channel Low Threshold MOSFETs 


mm 


DMOS N-Channel Discretes 


mm 


DMOS P-Channel Discretes 


wm 


DMOS Arrays and Special Functions 


mm 


High Voltage Driver/Interface ICs 


am 


High Voltage Analog Switches and Multiplexers 


wm 


High Voltage Power Supply ICs 


\*m 


CMOS Consumer/industrial Products 


am 


Surface Mount Packages and Lead Bend Options 


M 


Package Outlines 


urn 


Die Specifications 


wm 


Representatives/Distributors 





Chapter 7 - N- and P-Channel Low Threshold MOSFETs 

LP07 -16.5V, 1.5 ohms 7-1 

TN01 A 60, 1 00V, 3 ohms 7-5 

TN01 L 20, 40V, 1 .8 ohms 7-9 

TN05C 200, 240V, 1 ohms 7-13 

TN05D 350, 400V, 22 ohms 7-17 

TN06A 60, 1 00V, 1 .5 ohms 7-21 

TN06C 200, 240, 6 ohms 7-25 

TN06D 350, 400V, 10 ohms 7-29 

TN06L 20, 40V, 0.75 ohms 7-33 

TN07L 20V, 1 .3 ohms 7-37 

TN25A 60, 1 00V, 1 .5 ohms 7-41 

TN25C 200, 240V, 6 ohms 7-45 

TN25D 350, 400V, 1 2 ohms 7-49 

TN25L 20, 40V, 1 ohm 7-53 

TN25U 1 8V, 2.5 ohms 7-57 

TN26D 350, 400V, 5 ohms 7-61 

TP01 L -20, -40V, 4 ohms 7-63 

TP06A -60, -1 00V, 3.5 ohms 7-67 

TP06C -160, -200V, 12 ohms 7-71 

TP06L -20, -40V, 2 ohms 7-75 

TP25A -60, -1 00V, 3.5 ohms 7-79 

TP25C -1 60, -200V, 1 2 ohms 7-83 

TP25D -350, -400V, 25 ohms 7-87 

TP25L -20, 2 ohms 7-91 



LP07 




P-Channel Enhancement-Mode 
Lateral MOSFET 



Ordering Information 



BV / 

** * DSS ' 

BV 


□ 

"DSION) 

(max) 


'd(ON) 

(min) 


V 

GS(lh) 

(max) 


Order Number / Package 


TO-92 


DICE 


-16.5V 


1.5Q 


-1.25A 


-1.0V 


LP0701N3 


LP0701ND 



Features 

□ Ultra low threshold 

J High input impedance 

[j Low input capacitance 

□ Fast switching speeds 

□ Low on resistance 

□ Freedom from secondary breakdown 

□ Low input and output leakage 

□ Complementary N- and P-channel devices 



Applications 

□ Logic level interface 

□ Solid state relays 

□ Battery operated systems 

□ Photo voltaic drive 

□ Analog switch 

□ General purpose line driver 



Absolute Maximum Ratings 



BV„ 



Drain-to-Gate Voltage 


DSS 

BV DGS 


Gate-to-Source Voltage 


± 10V 


Operating and Storage Temperature 


-55°C to+150°C 


Soldering Temperature* 


300°C 



Advanced MOS Technology 

These enhancement-mode (normally-off) transistors utilize a lat- 
eral MOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and negative temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. The low threshold voltage and low on- 
resistance characteristics are ideally suited for hand held battery 
operated applications. 



Package Options 




*Distance of 1 .6 mm from case for 10 seconds. 



7-1 



LP07 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed)* 


Power Dissipation 
@ T c = 25°C 


c/w 


°c/w 


'or 


1 * 


TO-92 




-1.25A 


1W 


125 


170 


-0.9A 


-1.25A 



* l p (continuous) is limited by max rated T. 



Electrical Characteristics (@ 25°C unless otherwise specified) (Notes 1 and 2) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source Breakdown Voltage 


-16.5 






V 


V GS = 0, l D = -1mA 


V GS(th) 


Gate Threshold Voltage 


-0.5 


-0.7 


-1.0 


V 


V G s = V DS , l D = -1-0mA 


A ^GS(th) 


Change in V GS(th) with Temperature 






-4.0 


mV/°C 


V GS = V DS , Id = -1 .0mA 


'gss 


Gate Body Leakage 




1-100 


nA 


V GS = ±10V, V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






-100 


nA 


V DS = -15V,V GS = 0V 






-1.0 


mA 


V DS = 0.8 Max Rating, 
V GS = 0V, TA= 125°C 


'd(ON) 


ON-State Drain Current 




-0.4 




A 


V GS = V DS = -2V 


-0.6 


-1.0 




V GS = V DS = -3V 


-1.25 


-2.3 




A 


V G s = V DS = -5V 


^DS(ON) 




Static Drain-to-Source 
ON-State Resistance 




2.0 


4.0 


n 


V gs = -2V, l D = -50mA 




1.7 


2.0 


V GS = -3V, l D = -150mA 




1.3 


1.5 


V GS = -5V, l D = -300mA 


A RdS(ON) 


Change in R DS( on) with temperature 






0.75 


%/°c 


V GS = -5V, l D = -300mA 


G FS 


Forward Transconductance 


500 


700 




mu 


V DS = -15V, l D = -1A 


C|SS 


Input Capacitance 




120 


250 


PF 


V es = 0V, V DS = -15V, f = 1MHz 


Coss 


Common Source Output Capacitance 




100 


125 


Crss 


Reverse Transfer Capacitance 




40 


60 


'd(ON) 


Turn-ON Delay Time 






20 


ns 


V DD =-15V, l D = -1.25A, 
Rqen = 25Q 


t, 


Rise Time 






20 


td(OFF) 


Turn-OFF Delay Time 






30 


tf 


Fall Time 






20 


V SD 


Diode Forward Voltage Drop 




-1.2 


-1.5 


V 


V GS = 0V, l SD = -500mA 



Note 1 : All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 
Note 2: All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 



INPUT 



OUTPUT 




7-2 



Typical Performance Curves 

Output Characteristics 



-2 5 



-2.0 































»GS = 






































































r — 















































































0-4-8 -12 

V DS (volts) 



Transconductance vs. Drain Current 



1.0 



0.8 



2 0.4 



0.2 





















>°C 






s - " 


13V 










= -5! 




































T A 


= 25 


°C 


































T A 


= 12 


5°C 

















































































-1.0 -2.0 

l D (amperes) 



Maximum Rated Safe Operating Area 



-10 



-0.01 





































































TO-92^pulsed| 
















-TO 


-92 


(D 


DM* 






























I 




















s 



































































































-0.1 -1.0 -10 -100 

V DS (volts) 



7-3 



Saturation Characteristics 



-2 5 



-20 



| 

E 

































s - 


5V- 








































-4V" 








































-3V- 









































































































-1 -2 -3 -4 -5 

V DS (volts) 



Power Dissipation vs. Case Temperature 



2 























































TO-92 









































































25 50 75 100 125 150 

T c (°C) 



Thermal Response Characteristics 




0.001 0.01 0.1 1.0 10 

tp (seconds) 



LP07 



Typical Performance Curves 

BV DSS Variation with Temperature 




Transfer Characteristics 



a) 
a. 
E 

CO 

















-» — 
f 


t 








5V 






1 




— / 






— T 




ccot 








/ 










r. » 


i 






















/ 


















g 

f t 




= 12 


5°C 














/ 

/ 





































































-1 -2 -3 -4 -£ 

V GS (volts) 
Capacitance vs. Drain-to-Source Voltage 



i 

to 
o 
o 

O 







f = 1MHz 






Ciss 






Coss 






Crss 



-5 -10 

V DS (volts) 



-15 



On-Resistance vs. Drain Current 



E 6 

z 

o 

S 4 



V GS = -2V 
























v GS = 


:-3V 


















= -5V 





























































-1 -2 

l D (amperes) 
V (th) and R DS Variation with Temperature 



N 

E 

o 
c 

1 08 

CO 

0.6 



0.4 

























-1m/ 














\ 














































































-5V, 


300rr 


)A — 










DN) @ 

























"S 

N 

| 
o 



50 

T, rc) 



100 150 



Gate Drive Dynamic Characteristics 



a> -6 
o 





























ov 












































-20 


/ 


















38p 




















F 








































































iss- 


115 


OF 













12 3 4 

Q G (nanocoulombs) 



7-4 



TN01A 

Low Threshold 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


^DS(ON) 

(max) 


'd(ON) 

(min) 


(max) 


Order Number / Package 


TO-39 


TO-92 


DICE* 


60V 


3£i 


2A 


1.6V 


TN0106N2 


TN0106N3 


TN0106ND 


100V 


3U 


2A 


1.6V 


TN0110N2 

i 


TN0110N3 


TN0110ND 



f MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

1 Low threshold — 1 .6V max. 
High input impedance 
Low input capacitance — 50 pF typical 
Fast switching speeds 

□ Low on resistance 

Free from secondary breakdown 
_ Low input and output leakage 

□ Complementary N- and P-channel devices 



Applications 



□ Logic level interface - ideal for TTL and CMOS 
Solid state relays 

□ Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

: General purpose line driver 

□ Telecom switches 

Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Package Options 




7-5 



TN01A 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 
@ T c = 25°C 


% 

c/w 


C/W 


'dr* 


'drm 


TO-92 


0.5A 


2.0A 


LOW 


170 


125 


0.5A 


2.0A 


TO-39 


0.8A 


2.5A 


3.5W 


125 


35 


0.8A 


2.5A 



* l D (continuous) is limited by max rated T. 



Electrical Characteristics (@ 25°C unless otherwise specified) 



Symbol 


Parameter 


Uin 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


TN0110 


100 






V 


l D = 1mA, V GS = 


TN0106 


60 


V GS(th) 


Gate Threshold Voltage 


0.6 




1.6 


V 


V GS = v ds. Id = 0-5mA 


AV GS(th) 


Change in V GS(th) with Temperature 




-3.2 


-5.0 


mV/°C 


V GS = V DS , Id = 1 0mA 


l G ss 


Gate Body Leakage 






100 


nA 


V GS = +20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = Max Rating 


500 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'D(ON) 


ON-State Drain Current 


u. to 


1 A 




A 


V GS = 5V, V DS = 25V 


2.0 


3.4 




V GS = 10V, V DS = 25V 


^DS(ON) 


Static Drain-to-Souroe 
ON-State Resistance 




2.0 


4.5 


a 


V GS = 5V, l D = 250mA 


1 .6 


3.0 


V GS = 10V, l D = 500mA 




Change in R DS( on) witn Temperature 




0.6 


1 .1 


%/°c 


l D = 0.5A, V GS = 10V 


G FS 


Forward Transconductance 


225 


400 




mt! 


V DS = 25V, l D = 500mA 


G ISS 


Input Capacitance 




50 


60 


PF 


V GS = 0, V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




25 


35 


C RSS 


Reverse Transfer Capacitance 




4.0 


8.0 


•d(ON) 


Turn-ON Delay Time 




2.0 


5.0 


ns 


V DD = 25V 
l D = 1.0A 
R G EN = 25£2 


«, 


Rise Time 




3.0 


5.0 


l d(OFF) 


Turn-OFF Delay Time 




6.0 


7.0 


t, 


Fall Time 




3.0 


6.0 


V SD 


Diode Forward Voltage Drop 




1.0 


1.5 


V 


l SD = 0.5A, V GS = 


t„ 


Reverse Recovery Time 




400 




ns 


l SD =0.5A, V GS = 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




7-6 



Typical Performance Curves 

Output Characteristics 

























































" G S = 


10V 
















— 


























A 
































































































































































10 20 30 40 50 

V DS (volts) 



3- 



TN01A 

Saturation Characteristics 















































































10V 








































i 8V 











































































































































4 6 

V DS (volts) 



10 



Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



E 

■2- 

I 

































= -55°C 


































t a 


= 25°C 


















L,L- 
















t a 


= 15C 


°C 












































































v DS 


= 2 


5V 























.6 1.2 1.8 2.4 3.0 

l D (amperes) 



TO-39 




Maximum Rated Safe Operating Area 



Thermal Response Characteristics 



0.01 























































































~j-f-±t 








s, 














TO-92 (pulse 
TO-39 (DC) 


i 






\ 
































V 
































> 











































TO-S 


2 ([ 



















































































































































































10 100 

V DS (volts) 



1 

.2 0.8 
to 

I 

o 



E 
S 

F 































TO-39 








■c 

P D = 3 


5W 


























TO-92 










-T c =25°( 
P D =1W 











001 0.01 0.1 1 

tp (seconds) 



7-7 



TN01A 



Typical Performance Curves 

BV D ss Variation with Temperature 




Transfer Characteristics 



2 1.8 

9 

Q. 

i 

Q 1.2 



























3 =2 


5V 




1 


A = 


-55 ° 


C V 






















7 


















>5°C 


✓ 
















f 1 


50 °( 

l 
















r 4 


< 


















t 





































































6 8 10 



Capacitance vs. Drain-to-Source Voltage 



100 



| ao 

a. 

O 









f = 1MHz 








Ciss 








Coss 








Chss 



10 20 30 40 

V DS (volts) 



On-Resistance vs. Drain Current 



o 
rr 









\ 




= 5V 








Vgs 


= K 


V 



























































































































































































10 2.0 3.0 4.0 50 

l D (amperes) 
V (th) and R DS Variation with Temperature 



I u 



I.0 

,5, 

1 0.8 
CO 























(th)@ 


0.5m> 














\ 
















j,® 1 


OV, 


5A — 








V 1- 


DS(Of 



















































































1.0 « 
O 

0.8 § 
to 

I 



-50 50 100 150 

Tj(°C) 

Gate Drive Dynamic Characteristics 



a 
> 

























v D s 


= 1 


OV 
























55pF 
























' 4C 


V 












































































































5C 


PF 















1.0 2.0 3.0 4.0 5.0 

Q G (nanocoulombs) 



7-8 



TN01L 

Low Threshold 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


"ds<on) 
(max) 


VGS<th) 

(max) 


f J 


Order Number / Package 


TO-39 


TO-92 


TO-243AA* 


DICE+ 


20V 


1.8£1 


1.6V 


2.0A 


TN0102N2 


TN0102N3 




TN0102ND 


40V 


1.8a 


1.6V 


2.0A 


TN0104N2 


TN0104N3 




TN0104ND 


40V 


2.0Q 


1.6V 


2.0A 






TN0104N8 





* Same as SOT-89. 

f MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Low threshold —1 .6V max. 

□ High input impedance 

□ Low input capacitance 

□ Fast switching speeds 

□ Low on resistance 

□ Free from secondary breakdown 

□ Low input and output leakage 

□ Complementary N- and P-channel devices 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertax's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Package Options 



Applications 



□ Logic level interface - ideal for TTL and CMOS 

□ Solid state relays 

□ Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

1 General purpose line driver 

□ Telecom switches 

Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 




BV DGS 


Gate-to-Source Voltage 




±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 




300°C 


* For TO-39 and TO-92. distance of 1 .6 mm from c 


asefoMOsecor 


ds. 




TO-39 



3 Package Outline section for 




TO-92 



discrete pinouts. 



7-9 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 

<8 I c = 25 O 


WW 


% 
WW 


■dr 


'drm 


TO-39 


1.25A 


2.90A 


3.5W 


35 


125 


1.25A 


2.90A 


TO-92 


0.80A 


2.40A 


LOW 


125 


170 


0.80A 


2.40A 


TO-243AA 


1.40A 


2.90A 




15 


78+ 


1.40A 


2.90A 



* l (continuous) is limited by max rated T. 

f Mounted on FR5 Board, 25mm x 25mm x 1 ,57mm. Signficant P D increase possible on ceramic substrate. 

Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


B^dss 


Drain-to- Source 
Breakdown Voltage 




TN0104 


40 






V 


V GS = 0, l D = 1 .0mA 






TN0102 


20 






V G s ( th) 


Gate Threshold Voltage 


0.6 




1.6 


V 


Vr, = Vr,,;, In = 500llA 




Change in V GS(th) with Temperature 




-3.8 


-5.0 


mV/°C 


V GS = V DS , L = 1 .0mA 


^GSS 


Gate Body Leakage 




0.1 


100 


nA 


V GS = ±20V, V DS = 


^DSS 


Zero Gate Voltage Drain Current 






1 


uA 


V GS =0, V os = Max Rating 














100 


uA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


b(ON) 


ON-State Drain Current 








0.35 






V GS = 3V, V DS = 20V 










0.5 


1.1 




A 


V GS = 5V, V DS = 20V 










2.0 


2.6 






V GS = 10V, V DS = 20V 


^DS(ON) 


Static Drain-to-Source 








5.0 






V GS = 3V. l D = 50mA 




ON-State Resistance 


All Packages 




2.3 


2.5 




Vqs = 5V, l D = 250mA 






TO-39, TO-92 




1.5 


1.8 


a 


V GS =10V, l D = 1A 






TO-243AA 






2.0 




V GS = 10V, l D = 1A 


A ^DS(ON) 


Change in RDS(ON) with Temperature 




0.7 


1.0 


%/°C 


V GS =10V, l D = 1A, 




Forward Transconductance 


0.34 


0.45 




u 


V DS = 20V, l D = 0.5A 


C\ss 


Input Capacitance 






70 




V GS = 0, V DS = 20V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 






50 




Crss 


Reverse Transfer Capacitance 






15 




l d(ON) 


Turn-ON Delay Time 




3.0 


5.0 






t r 


Rise Time 








7.0 


8.0 


ns 


V DD = 20V, l D = 1A 
R GEN = 25Q 


'd(OFF) 


Turn-OFF Delay Time 




6.0 


9.0 


tf 


Fall Time 




5.0 


8.0 






V SD 


Diode Forward 


TO-39, TO-92 




1.2 


1.8 




V GS = 0, l SD = 1.0A 




Voltage Drop 


TO-243AA 






2.0 


V 


v G s = 0. Isd = 0.5A 


V 


Reverse Recovery Time 




300 




ns 


V GS = 0, Isd = 1a 



Notes: 

1 . All D.G. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 



OUTPUT 



ov 



10% -, 




^90% 




km 




t(OFF) 




*d(ON) t, 


•aiOFF) 


If 








90% ' 


t 1 


"-10% 

i 




7-10 



Typical Performance Curves 

Output Characteristics 



Q. 

E 

CO 























































\ 


GS- 


10V 








































8V 



































































































































10 20 30 40 50 

V DS (VOltS) 



Saturation Characteristics 



a 1.5 











































































— V 


GS= 


nv 
























'-8V 



































































































































2 4 6 8 

V DS (volts) 



Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



1 



1 1 1 

\/ OC\l 






























= -5£ 


°C 




































t a 


= 2E 


°C 
















1 
















Ta = 


125 


°C 


T 















































































0.5 1.0 1.5 2.0 2.5 

l D (amperes) 
Maximum Rated Safe Operating Area 



E 



































































P, 




d 


) 




















— rrr 






































TO-39 (DC) 


t" 




















■TO-92 (DC) 4- 






1 I I I 






















TO-243AA (DC) ^ 








s 












( ' A 


= d 


















































































— 































































































































0.1 



1 10 

V DS (volts) 



























TO-39 




































-TO-243 
(T A = 2 


AA 










5°C) 










TO-92 





































25 50 75 100 125 150 

T C (°C) 

Thermal Response Characteristics 



CD 
GC 

I 

CD 





0.001 































































/ 10- 


92 






PD 


= 1W 






1 



0.01 0.1 1 

tp (seconds) 



7-11 



Typical Performance Curves 



TN01L 




7-12 



TN05C 

Low Threshold 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BVcos 


"dS(ON) 

(max) 


11 


^GS(th) 

(max) 


Order Number / Package 


TO-39 


TO-92 


DICE+ 


200V 


10a 


300mA 


1.5V 


TN0520N2 


TN0520N3 


TN0520ND 


240V 


10£1 


300mA 


1.5V 


TN0524N2 


TN0524N3 


TN0524ND 



+ MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Low threshold — 1 .5V max. 

□ High input impedance 

□ Low input capacitance — 45 pF typical 

□ Fast switching speeds 

□ Low on resistance 

□ Free from secondary breakdown 

□ Low input and output leakage 

□ Complementary N- and P-channel devices 

Applications 

□ Logic level interface - ideal for TTL and CMOS 

□ Solid state relays 

□ Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°CtO+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Package Options 




7-13 



TN05C 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 






'dr* 


•drm 








@ T c = 25°C 


c/w 


"C/W 






TO-39 


0.7A 


1.5A 


3.5W 


35 


125 


0.7A 


1.5A 


TO-92 


0.3A 


1.0A 




125 


170 


0.3A 


1.0A 



* l D (continuous) is limited by max rated T„ 

Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


isOnaiiions 


HV DSS 


Drain-to-Source 
Breakdown Voltage 


TN0524 


OAC\ 






V 


V gs= °. l D =1mA 


TN0520 




w 

v GS(ttl) 


Gate Threshold Voltage 


U.D 




I .o 


\/ 
V 


V GS = v ds. 'd = i.omA 


AV GS(th) 


Change in V GS(lh) with Temperature 




-3.0 


-4.0 


mV/°C 


Vgs = V ds . I D = 1-0mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = Max Rating 


500 


V DS = 0, V GS = 0.8 Max Rating 
T A = 125°C 




ON-State Drain Current 


100 


360 




mA 


V GS = 3V, V DS = 25V 


300 


850 




V GS = 5V, V DS = 25V 


^DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




9.0 


15 


Q 


V GS = 3V, l D = 50mA 


7.0 


10 


V GS = 5V, l D = 100mA 


AR DS(ON) 


Change in R DS (on) witn Temperature 




0.9 


1.5 


%/°C 


V GS = 5V, l D = 0.2A 


G FS 


Forward Transconductance 


0.15 


0.35 




u 


V DS = 25V, l D = 0.2A 




Input Capacitance 




45 


60 


pp 


V GS = 0, V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




15 


35 


Crss 


Reverse Transfer Capacitance 




3.0 


8.0 


•dfON) 


Turn-ON Delay Time 




3.0 


5.0 


ns 


V DD = 25V 
l D = 0.3A 
R GEN = 25£2 


'r 


Rise Time 




3.0 


5.0 


'd(OFF) 


Turn-OFF Delay Time 




5.0 


10 


tf 


Fall Time 




3.0 


9.0 


v SD 


Diode Forward Voltage Drop 




1.1 


2.5 


V 


V GS = 0, l SD = 100mA 




Reverse Recovery Time 




400 




ns 


V GS = °. I SD = 100mA 



1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300ms pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 



INPUT 



OUTPUT 



0V 



! d(OFF) 



90% \ / 90% 





o OUTPUT 



D.U.T. 



7-14 



TN05C 



Typical Performance Curves 

Output Characteristics 



1.6 



g 1.2 

I 
E 

™. 

~ 0.8 



0.4 

























































\ 


GS ~ 


10V 




























— f- 
























































6V 






























































4V 




i 






































2V 

























20 40 60 80 100 

V DS (volts) 



Saturation Characteristics 



i 0.4 













I I 

v„„- mv 






























































4V 




































































































2V 























4 6 8 

V DS (volts) 



Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



0.4 



E 



« 0.2 

































T A 


= -5! 


°C 
































T A 


= 25 


°C 
































t a 


= 1S 






























































V 


DS a 


25V 























0.2 0.4 0.6 0.8 1.0 

l D (amperes) 



o? 2 



























TO-3! 




























































TO-9! 





































25 50 75 100 125 150 

T C (°C) 



Maximum Rated Safe Operating Area 



Thermal Response Characteristics 



2 
E 



0.001 



nr 


















r 


3-92 

s 


pu 




) 














































. T 


0-: 


9 


( 


3C) 








































































T 


0-9 


2 


( 


JC)? 







































































































































































































































10 100 

V DS (volts) 



2 

W 
'(0 
O 

rr 

i 



^ 0.8 

CO 

1 
o 





































TO-39 






P D = 3.5W 






T C = 


25°C 































0.001 0.01 



0.1 1.0 

t p (seconds) 



7-15 



Typical Performance Curves 

BV DSS Variation with Temperature 




100 150 



Transfer Characteristics 



1.2 



a 0.9 



V DS = 25V 




_ 

r" 


= 2 


5°C ( 


/ 

• 


















/ 

/— 






— 1 


A = 


-55° 


*» 1 






/ 












4 


/ 

■ 
















4 


/ 

f 





— 

125° 


C 












/ 



























































































2 4 6 

V GS (volts) 



8 10 



Capacitance vs. Drain-to-Source Voltage 



100 



2 

(0 

o 

o 

o 









f = 1MHz 








C ISS 










I"" 






Cqss 




J CrSS 



10 20 30 

V DS (volts) 



On-Resistance vs. Drain Current 



TN05C 



o, 
o 

S 8 

DC 





























3S = 


3V 
























iS - 


5V 
















v c 





































































































































0.2 0.4 0.6 0.8 1.0 

l D (amperes) 
V (th ) and R D s Variation with Temperature 







































Rd 


S(ON) 


@ 5V 


0.1A 


















/(th) ® 


1.0m 












1 


A 











































































1.6 



0.4 



50 



100 150 



Gate Drive Dynamic Characteristics 



























v DS 


= 10V i 






















f V 


3S = 


40V 






















































125 






































































50pF 

I I 

















0.4 0.8 1.2 1.6 2 

Q G (nanocoulombs) 



7-16 



TN05D 

Low Threshold 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


"ds<on) 


'ckon) 




Order Number / Package 


BV^s 


(max) 


(min) 


(max) 


TO-92 


DICE+ 


350V 


22Q 


250mA 


2.0V 


TN0535N3 


TN0535ND 


400V 


220 


250mA 


2.0V 


TN0540N3 


TN0540ND 



+ MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Low threshold — 2.0V max. 

□ High input impedance 

□ Low input capacitance — 48 pF typical 

□ Fast switching speeds 

□ Low on resistance 

□ Free from secondary breakdown 

□ Low input and output leakage 

□ Complementary N- and P-channel devices 

Applications 

□ Logic level interface - ideal for TTL and CMOS 
d Solid state relays 

□ Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


' Distance of 1.6 mm from case for 10 seconds. 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertax's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Package Options 




7-17 



TN05D 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 


% 




l * 

'DR 


'drm 








@ T c = 25°C 


c/w 


°c/w 






TO-92 


140mA 


750mA 


LOW 


170 


125 


140mA 


750mA 



* l D (continuous) is limited by max rated T. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


B^DSS 


Drain-to-Source 
Breakdown Voltage 


TN0540 


400 






V 


Vr-o = In = 1 mA 


TN0535 


350 




udlu llllcfollUlU vUlldyfc} 


0.8 




2.0 


V 


V r e = Vhq, ln= 1mA 


^^GS(th) 


Phannp in \/ \A/ith Ttsmrvsrati ir^ 
\s\ Idl iyc 111 Vfjjg/jrij Willi 1 fcM 1 IfJfcM dlUI c 




-3.5 


-4.5 


mV/°C 


Vr-o = Vno, In = 1 mA 
tab Uo" U 


'gss 








100 


nA 


V GS = ±20V, V DS = 


'dss 


7arrt ato \/oltanta (""train fiirrant 
Udlc VUllctyc Ula\U IsUKcilL 






10 


uA 


V GS = 0, V DS = Max Rating 


500 


uA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 




550 




mA 


V GS = 5V, V DS = 25V 


250 


750 




V GS = 10V,V DS = 25V 


^DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




20 


22 


£2 


V GS = 4.5V, l D = 100mA 


19 


22 


V GS = 10V, l D = 150mA 


AR DS(ON) 


Change in R DS (on) wiln Temperature 




0.9 


1.5 


%/°C 


V GS = 10V, l D = 0.1A 


G FS 


Forward Transconductance 


125 


200 




mU 


V DS = 25V, l D = 0.1A 


Ciss 


Input Capacitance 




48 


60 


PF 


V GS = 0, V DS = 25V 
f = 1 MHz 


C-oss 


Common Source Output Capacitance 




11 


15 


Crss 


Reverse Transfer Capacitance 




3.0 


8.0 




Turn-ON Delay Time 




5.0 


8.0 


ns 


V DD = 25V, 
l D = 250mA, 
Rgen = 25Q 


% 


Rise Time 




5.0 


8.0 


'd(OFF) 


Turn-OFF Delay Time 




5.0 


9.0 


% 


Fall Time 




5.0 


8.0 


V SD 


Diode Forward Voltage Drop 




0.8 


1.2 


V 


V GS = 0, l SD = 150mA 


t rr | Reverse Recovery Time 




400 




ns 


V GS = 0. I SD = 150mA 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit v DD 




7-18 



TN05D 



Typical Performance Curves 

Output Characteristics 



































s = 


10V 








































6V 
















































































4V 







































20 40 60 80 100 

V DS (volts) 



Saturation Characteristics 



I 0.2 

































V GS 


= 1 c 


y 










































































4V- 
















































































2V 







4 6 

V DS (volts) 



Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



o.i 























-v D 


s =• 
















































1 


A = 


-55° 


C 














T A = 25°C 






t 










~r-r 














T 




25°< 






















i 

























































0.1 0.2 0.3 0.4 0.5 

l D (amperes) 



i 

o o.e 



















































TO-92 









































































25 50 75 100 125 150 
T C fC) 



Maximum Rated Sate Operating Area 



Thermal Response Characteristics 



E 

to 





uLiJJ- 






















TO-92 


(F 


ulsed 


) 


































s 

< 


s 










TO-92 (DC) 
















































































































T( 


; = '• 


5° 


C 




































































k 































































10 100 

V DS (volts) 



.M 0.8 

CO 

I 

o 



0> 



E 

0.2 























































/ T 


0-92 






/ P D =1W 






T 


; = 25°C 











0.001 0.01 0.1 1 

tp (seconds) 



7-19 



Typical Performance Curves 



TN05D 




7-20 



TN06A 

Low Threshold 



»EfS 

mm 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


R DS(ON) 

(max) 


if 


VGS<th) 

(max) 


Order Number / Package 


TO-39 


TO-92 


TO-220 


Quad P-DIP 


Quad C-DIP* 


DICE* 


60V 


1.5Q 


3.0A 


1.6V 


TN0606N2 


TN0606N3 


TN0606N5 


TN0606N6 


TN0606N7 


TN0606ND 


100V 




3.0A 


1.6V 


TN0610N2 


TN0610N3 


TN0610N5 


- 




TN0610ND 



* 14 pin side brazed ceramic DIP 
1 MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Low threshold — 1 .6V max. 

□ High input impedance 

□ Low input capacitance — 1 00 pF typical 

□ Fast switching speeds 

□ Low on resistance 

□ Free from secondary breakdown 

□ Low input and output leakage 

□ Complementary N- and P-channel devices 



Applications 



~ Logic level interface - ideal for TTL and CMOS 

□ Solid state relays 

□ Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 



Absolute Maximum Ratings 


Drain-to-Source Voltage 


BV DSS 


Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Package Options 





Note 1 : See Package Outline section for discrete pinouts. 
Note 2: See Array section for quad pinouts. 



Distance of 1 .6 mm from c 



3 for 10 



7-21 



TN06A 



Thermal Characteristics 



Package 


l D (continuous)* 


1 /mil«*arl\ 

l D (pulsed) 


Power Dissipation 

@ T c = 25°C 


CAV 


% 
°C/W 


■dr 


■ 

'drm 


TO-92 


0.8A 


3.2A 


1W 


125 


170 


0.8A 


3.2A 


TO-39 


1.5A 


4.0A 


6W 


20 


125 


1.5A 


4.0A 


TO-220 


3.0A 


4.1A 


45W 


2.7 


70 


3.0A 


4.1A 


Plastic DIP 


Refer to Arrays & Special Functions Section. 


Ceramic DIP 



* l (continuous) is limited by max rated T . 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 




Drain-to-Source 
Breakdown Voltage 


TN0610 


100 






V 


V GS = 0, l D = 1mA 


TN0606 


60 


V G S(th) 


Gate Threshold Voltage 


0.6 




1.6 


V 


v gs = v ds. I D = 1mA 




Change in V GS(th) with Temperature 






-4.5 


mV/°C 


v gs = v ds. I D = 1mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±20V, V DS = 


'dSS 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = Max Rating 


1.0 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C (note 2) 


'D(ON) 


ON-State Drain Current 


1.2 


2.0 






V r o = 5V V no = 25V 

GS ' DS 


3.0 


6.7 


V GS = 10V, V DS = 25V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




1.5 


2.0 


£2 


V GS = 5V, l D = 0.75A 


1.0 


1.5 


V GS = 10V, l D = 0.75A 


AR DS(ON) 


Change in R ds( on) with Temperature 






0.75 


%/°C 


V GS = 10V, l D = 0.75A 


G FS 


Forward Transconductance 


0.4 


0.5 




V 


V DS = 25V, l D = 1.0A 




Input Capacitance 




100 


150 


pF 


V GS = 0, V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




50 


85 


Crss 


Reverse Transfer Capacitance 




10 


35 


'd(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = 25V 
l D = 1.5A 
Rgen = 251J 


t, 


Rise Time 






10 


'd(OFF) 


Turn-OFF Delay Time 






20 


tf 


Fall Time 






12 


V SD 


Diode Forward Voltage Drop 




0.8 


1.8 


V 


V GS = 0, l SD = 1.5A 


trr 


Reverse Recovery Time 




300 




ns 


V GS = 0, l SD = 1 5A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300ms pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




7-22 



TN06A 



Typical Performance Curves 

Output Characteristics 



£ 6 

I 

E 



























































V GS 



























































































































































































10V 
9V 

8V 
7V 
6V 
5V 
3V 



10 20 30 40 50 

V DS (volts) 
Transconductance vs. Drain Current 















I I 


















3 "« 


3V 
























































T A = 
— - 


-55 °C 
— ^ — 














— — 


T A = 25°C 
— * — K — 


















150 


°c 

























































Id (amperes) 
Maximum Rated Safe Operating Area 



1.0 



8. 



0.01 













FFfi 


















TO-39 (pulsed) 








































~\ 








T 




(D 


k 


















it" 




-T 








































































p 




\ 












TO-92 (DC)"- 



























































































10 100 

V DS (volts) 



Saturation Characteristics 




V DS (volts) 
Power Dissipation vs. Case Temperature 



J3 20 
0. 



TO-22 

































































































TO-39 












TO-92 







25 50 75 100 125 
T C (°C) 

Thermal Response Characteristics 



150 



1.0 



0.6 

CD 



in 0.4 
CD 

rr 

o 
E 



CD 





0.001 













ro-220 






P D =45W 








r c = 25°C 


























S TO-C 


9 






P D = 


5.6W 






Tc = 


25° C 











0.01 0.1 

tp (seconds) 



7-23 



TN06A 



Typical Performance Curves 

BV DSS Variation with Temperature 



o 1.0 



CO 

1 

rS 




Transfer Characteristics 



m 

a. 
£ 
to 

a 1 























\ 


'ds 


= 25' 


/ 








= -5 


5°C 








































2E 


°c 




















— jr 
















<> 








































<» 

15 


0°C 













































2 4 6 

V GS (volts) 



8 10 



Capacitance vs. Drain-to-Source Voltage 



CO 



o 
o 

O 







f = 


1MHz 








Ciss 








c oss 








Crss 



10 20 30 40 

V DS (volts) 



On-Resistance vs. Drain Current 



I 3 
2 

o 

s 2 

tr 





























S = 


5V 




































































i = i 


ov 














/ 

























































































2 4 6 

l D (amperes) 



8 10 



V( t h) and Rrjs Variation with Temperature 



0.8 





































. v (th 


)@ 1n 


1A 


































-Rds 


@ 1C 


V, 0.7 


5A_ 













































































1.2 « 

O 
c 

0.8 § 
CO 

I 

0.4 



-50 



50 

Ti(°C) 



100 150 



Gate Drive Dynamic Characteristics 



CO 

o 
> 





























v DS 


= 10V 










































■v D! 


; =4 


OV 






























172 


PF 







































































95 


pF 















0.5 1.0 1.5 2.0 2.5 

Q G (nanocoulombs) 



TN06C 

Low Threshold 



1 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


"dS(ON) 


'd(ON) 


V GS(th) 


Order Number / Package 


BV DGS 


(max) 


(min) 


(max) 


TO-39 


TO-92 


TO-220 


DICE* 


200V 


6£2 


1.0A 


1.6V 


TN0620N2 


TN0620N3 


TN0620N5 


TN0620ND 


240V 


6£i 


1.0A 


1.6V 


TN0624N2 


TN0624N3 


TN0624N5 


TN0624ND 



' MIL visual screening available 



High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 



Features 

□ Low threshold — 1 .6V max. 

□ High input impedance 

□ Low input capacitance — 1 1 pF typical 

□ Fast switching speeds 

□ Low on resistance 

□ Free from secondary breakdown 

□ Low input and output leakage 

□ Complementary N- and P-channel devices 

Applications 

□ Logic level interface - ideal for TTL and CMOS 

□ Solid state relays 

□ Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertax's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Package Options 




7-25 



TN06C 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 






I * 

MM 


'dhm 








@ T c = 25°C 


C/W 


°C/W 






TO-39 


0.7A 


2.5A 


6W 


20 


125 


0.7A 


2.5A 


TO-92 


0.4A 


2.0A 


1W 


125 


170 


0.4A 


2.0A 


TO-220 


1.5A 


2.5A 


45W 


2.7 


70 


1.5A 


2.5A 



' l D (continuous) is limited by max rated T 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


TN0624 


240 






V 


V GS = 0, l D = 2.0mA 


TN0620 


200 


V G S(th) 


f-ifltp Thrp^hfilH Vnltanp 


0.6 




1.6 


V 


Vgs = Vds. Id = 1 0mA 


AV GS(th) 


flhannp in V with Tfsmnprati irf> 

uuai lyc ui v GSIIhl win i i d i ijjci diui c 






-5.0 


mV/°C 


v gs = v ds. ! d = 1 0mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


UA 


V G s = 0, V DS = Max Rating 


1.0 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


0.5 






A 


V GS = 5V, V DS = 25V 


1.0 


V GS = 10V,V DS = 25V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




6 


8 


n 


Vqs = 5V, l D = 0.25A 


4 


6 


V GS = 10V, l c = 0.5A 


ARdsioni 


Change in R DS( on) with Temperature 






1.4 


%/°c 


V GS = 10V, l D = 0.5A 


G FS 


Forward Transconductance 


300 


400 




m!! 


V DS = 25V, l D = 0.5A 


G ISS 


Input Capacitance 




110 


150 


PF 


V GS = 0, V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




40 


85 


Crss 


Reverse Transfer Capacitance 




10 


35 


td(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = 25V 
l D = 1.0A 
Rgen = 25£J 


tr 


Rise Time 






8.0 


'd(OFF) 


1 ' 

Turn-OFF Delay Time 






20 


t t 


Fall Time 






20 


V S D 


Diode Forward Voltage Drop 






1.8 


V 


V GS = 0, l SD = 10A 


trr 


Reverse Recovery Time 




300 




ns 


V GS = 0, l SD = 10A 



1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 



10V 



INPUT 



OUTPUT 



'(ON) 



td(ON) 



*(OFF) 



'd(OFF) 



90%^ Jf90% 




O OUTPUT 



7-26 



TN06C 



Typical Performance Curves 

Output Characteristics 



















1 






































v G s = 






/ 

h 






















— 










- 
















-i 




















t 






































t 











































1 





J 





3 





A 


5 



10V 

8V 

6V 



V DS (volts) 
Transconductance vs. Drain Current 















\ 


'ds 


= 25 


{ 






















































1 




-55° 


C 














1 1 1 














T A =25°C 

■ — mt — <b M. a 














1 


A = 


150 c 


c 































































0.5 1.0 1.5 2.0 

l D (amperes) 
Maximum Rated Safe Operating Area 



2. 
E 

10 



0.01 





























































































■ - h -t -I 4h- 




— ■ 






V 










TO-220 (DC 






1 — I — !— 

TO-39 (DC) 
























1 








TO-92 (DC) 




\ 












r 










s 


s 








s 
























s 








\ 
































































s 







































































































Saturation Characteristics 




2 4 

V DS (volts) 
Power Dissipation vs. Case Temperature 



m 

to 
S 



TO-2 


20 






























































































TO-39 

— i-— 










TO-92 











25 50 75 100 125 150 

T C (°C) 

Thermal Response Characteristics 



I 
o 



lX 

"to 




10 100 

V DS (volts) 



0.001 0.01 0.1 1 

tp (seconds) 



7-27 



Typical Performance Curves 



TN06C 




TN06D 

Low Threshold 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV DSS / 


R DS(ON) 


'd(ON) 


V GS(th) 


Order Number / Package 


BV DGS 


(max) 


(min) 


(max) 


TO-92 


DICE* 


350V 


10£2 


1.0A 


1.8V 


TN0635N3 


TN0635ND 


400V 


10£J 


1.0A 


1.8V 


TN0640N3 


TN0640ND 



1 MIL visual screening available 



Features 



□ Low threshold — 1 .8V max. 

□ High input impedance 

□ Low input capacitance — 85 pF typical 

□ Fast switching speeds 

□ Low on resistance 

□ Free from secondary breakdown 

□ Low input and output leakage 

□ Complementary N- and P-channel devices 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertax's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertax vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Applications 



Package Options 



□ Logic level interface - ideal for TTL and CMOS 
Solid state relays 

□ Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 




7-29 



TN06D 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 


8 i> 




■dr 


'drm 








© T c = 25°C 


x/w 


°c/w 






TO-92 


200mA 


1.5A 


LOW 


170 


125 


200mA 


1.5A 



* l„ (continuous) is limited by max rated T f 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Tim 

Typ 


Max 


Unit 


Conditions 


R\/ 

HV DSS 


Drain-to-Source 
Breakdown Voltage 


TN0640 


Ann 






V 


w _ n I — innn A 


TN0635 


OOU 


^GSfth) 


Gate Threshold Voltage 


0.6 




1.8 


V 


W W 1 1 m A 

V GS = V DS. 'd= 1mA 


AV GS(th) 


Change in V GS(th) with Temperature 




-2.5 


-4.0 


mV/°C 


v gs = v ds. Ip= 1mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ± 20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = Max Rating 


1 .0 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


InrnNt 


ON-State Drain Current 


0.3 


1.5 




A 


V GS = 5V, V DS = 25V 


1.0 


1.8 




V GS = 10V, V DS = 25V 


HricjfrtMl 


Static Drain-to-Source 
ON-State Resistance 




8.0 


10 


a 


V GS = 4.5V, l D = 150mA 


7.0 


10 


V QS = 10V, l D = 0.5A 


AR DS(ON) 


Change in R DS( on) with Temperature 






0.75 


%/°c 


V GS = 10V, l D = 500mA 


G FS 


Forward Transconductance 


125 


350 




mU 


V DS = 25V, l D = 100mA 


Ciss 


Input Capacitance 




85 


130 


PF 


V GS = 0, V DS = 25V 
f = 1 MHz 


CfJSS 


Common Source Output Capacitance 




30 


75 


C RSS 


Reverse Transfer Capacitance 




10 


20 


•d(ON) 


Turn-ON Delay Time 






20 


ns 


V DD = 25V, 
l D = 1.0A, 
^gen = 25£J 


t, 


Rise Time 






15 


'd(OFF) 


Turn-OFF Delay Time 






25 


tf 


Fall Time 






20 


V S D 


Diode Forward Voltage Drop 






1.8 


V 


V GS = 0, l SD = 200mA 


'rr 


Reverse Recovery Time 




300 




ns 


V GS = 0, i SD =1.0A 



Notes: 

1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




7-30 



TN06D 



Typical Performance Curves 

Output Characteristics 









1 1 1 












































































































































































-J— 




2V 







10 20 30 40 50 

V DS (volts) 
Transconductance vs. Drain Current 



£ 0.2 

O 







J = 2 


5V 


























■ 


"a = 


-55° 


C 
































































T A = 125°C 


f 



































































































0.1 0.2 0.3 0.4 0.E 

l D (amperes) 
Maximum Rated Sate Operating Area 



a 
E 



0.001 




























-92 


( 


P 


jlsed 






> 
















"TC 


I 






k 
































> 


. 






























N 




































- TC 


























\" 













































































































































































































































10 100 

V DS (volts) 



Saturation Characteristics 



-S- 0.75 

m 

a. 
E 

CO 0.50 













Vqs = 10V 

























































































































































































6V 
4V 



V DS (volts) 
Power Dissipation vs. Case Temperature 



ffl 1.0 

Q 
0_ 



0.2 



















































TO-92 









































































25 50 75 100 125 150 

T C (°C) 

Thermal Response Characteristics 



» 0.4 



a) 





































TO-92 

p D -iw - 






T C =25°C 





































0.001 0.01 0.1 10 

tp (seconds) 



7-31 



TN06D 



Typical Performance Curves 

BV DSS Variation with Temperature On-Resistance vs. Drain Current 





7-32 



TN06L 

Low Threshold 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information Standard Commercial Devices 



BV DSS / 
BV DGS 


R DS(ON) 

(max) 


! D(ON) 

(min) 


V GS(th) 

(max) 


Order Number / Package 


TO-39 


TO-92 


SOW-20* 


DICE+ 


20V 


0.75Q 


4.0A 


1.6V 




TN0602N3 




TN0602ND 


20V 


0.85£2 


4.0A 


1.6V 


TN0602N2 








40V 


0.75Q 


4.0A 


1.6V 




TN0604N3 




TN0604ND 


40V 


0.85£> 


4.0A 


1.6V 


TN0604N2 








40V 


1.0 n 


4.0A 


1.6V 






TN0604WG 





* Same as SO-20 with 300 mil wide body. 
T MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Low threshold — 1 .6V max. 

□ High input impedance 

C Low input capacitance — 140pF typical 

□ Fast switching speeds 

□ Low on resistance 

□ Free from secondary breakdown 

□ Low input and output leakage 

P Complementary N- and P-channel devices 

Applications 

□ Logic level interface - ideal for TTL and CMOS 

□ Solid state relays 

P Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 

Absolute Maximum Ratings 



Drain-to-Source Voltage 


BV DSS 


Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm Irom case for 1 seconds. 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 

Package Options 



TO-39 



TO-92 




SOW-20 



Note 1 : See Package Outline section for discrete pinouts. 
Note 2: See Array section for quad pinouts. 




7-33 



TN06L 



Thermal Characteristics 



Package 


l D (continuous)* 


I D (pulsed) 


Power Dissipation 






■ * 
'dr 


'drm 








@ T c = 25°C 


c/w 


°C/W 






TO-39 


2.5A 


4.6A 


6W 


20 


125 


2.5A 


4.6A 


TO-92 


1.0A 


4.6A 


1W 


125 


170 


1.0A 


4.6A 


SOW-20 


Refer to Arrays & Special Functions Section. 



* l D (continuous) is limited by max rated T ( . 

Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


TN0604 


40 






V 


V GS = 0. lo = 2.0mA 


TN0602 


20 


^GS(th) 


Gate Threshold Voltage 


0.6 




1.6 


V 


V GS = V DS. ! D = 1 0mA 


AV GS(th) 


Change in V GS(th) with Temperature 




-3.8 


-4.5 


mV/°C 


V GS = v ds. !d = 2 5mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V cs = Max Rating 


1.0 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


. 

'D(ON) 


ON-State Drain Current 


1.5 


2.1 




A 


V GS = 5V, V DS = 20V 


4.0 


7.0 




V GS = 10V, V DS = 20V 


R 

"DS(ON) 


Static Drain-to-Source 
ON-State Resistance 


All Packages 




0.9 


1.5 


a 


V GS = 5V, l D = 0.75A 


TO-92 




0.6 


75 


Vrs= 10V, l n = 1.5A 


TO-39 






0.85 


SOW - 20 






1.0 


A ^DS(ON) 


Change in R ds(0 n) with Temperature 




0.5 


0.75 


%/°c 


V GS = 10V, l D = 2.0A 




Forward Transconductance 


0.5 


0.8 




u 


V DS = 20V, l D = 2.0A 


Ciss 


Input Capacitance 




140 


190 


PF 


V GS = 0, V DS = 20V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




75 


110 


C RSS 


Reverse Transfer Capacitance 




25 


50 


'd(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = 20V 
l D = 0.5A 
FIqen = 25Ji 


t, 


Rise Time 






6.0 




Turn-OFF Delay Time 






25 


t. 


Fall Time 






20 


V SD 


Diode Forward Voltage Drop 




1.2 


1.8 


V 


V GS = 0, l so = 1-5A 


trr 


Reverse Recovery Time 





300 




ns 


V GS = 0, l SD = 1A 



1 : All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 
2: All A.C. parameters sample tested. 

Switching Waveforms and Test Circuit 



OUTPUT 




PULSE 
GENERATOR 





D.U.T. 



7-34 



TN06L 



Typical Performance Curves 

Output Characteristics 



g 6 



1 

CO 




Saturation Characteristics 




4 6 

V DS (volts) 



Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



9 
E 

.3> 1.0 

e 

o 











V D S = 25V 






































T„ 


= -55 


°C 


















T« = 25°C 














r-- 








r- 










Ta 


= 125 


°c — 
















i- 





























1 2 3 4 5 8 7 

l D (amperes) 



CO 



Q 







































TO-3E 




























































TO-92 













25 50 75 100 125 150 

T C (°C) 



Maximum Rated Safe Operating Area 



Thermal Response Characteristics 



1.0 



0.01 



II Ml 
















TO 


-92 


(pulse 


d) 








! -\— 






















\ 










-39 


(DC) 

uu 












V 

\ 














































































TO 


-92 


(D( 


5) 



















































































































1 10 

V DS (volts) 



CD 
fX 













TC 


)-39 






Tc = 25°C 

r» phi 








- uvv y 


































)-92 






Tc 


= 25°C 
= 1W — 






Pc 



0.001 0.01 0.1 

tp (seconds) 



TN06L 



Typical Performance Curves 

BV DSS Variation with Temperature 




100 150 



Transfer Characteristics 



<D 
Q- 

E 
a 





V DS = 25V 






































































Co. 

o . ' 












































j 































































2 4 6 8 1< 

V GS (volts) 
Capacitance vs. Drain-to-Source Voltage 



8 

Q. 

o 





f= 1M 


Hz 


— C iss - 
















C ss 














Crss 









20 30 

V DS (volts) 



On-Resistance vs. Drain Current 



1.0 

o 
to 































Vgs 


= 5 












































v 


3S = 


10V 






























































} 





































































a 5.0 io 

l D (amperes) 

V (th) and R DS Variation with Temperature 



ffi 

N 
I 



> 





































V(,h 


@ 1n 


lA 
































R[ 


)S@ " 


0V, 1 


5A 



















































































0.8 



50 100 

TjCC) 

Gate Drive Dynamic Characteristics 



C3 

> 

















































V DS = 10V J 
















70 | 


F 






17C 


pF 




































= 40V 



















































































1.0 2.0 3.0 4.0 

Q G (nanocoulombs) 



5.0 



7-36 



TN07L 

Low Threshold 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV DSS / 


R DS(ON) 


'd(ON) 


^GS(th) 


Order Number / Package 


BV DGS 


(max) 


(min) 


(max) 


TO-92 


DICE* 


20V 


1.3£2 


0.5A 


1.0V 


TN0702N3 


TN0702ND 



* MIL visual screening available 



Features 

□ Low threshold — 1 .0 volt max 

□ On resistance guaranteed at V GS = 2, 3, and 5 volts 

□ High input impedance 

□ Low input capacitance — 1 30 pF typical 

□ Fast switching speeds 

□ Low on resistance 

□ Free from secondary breakdown 

□ Low input and output leakage 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Applications 

□ Logic level interface 

□ Solid state relays 

□ Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



Package Options 



BV n 



Drain-to-Gate Voltage 


BV Des 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 



'Distance of 1.6 mm from case for 10 seconds maximum. 




7-37 



TN07L 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 






'dr* 


'drm 








@ T c = 25°C 


c/w 


C/W 






TO-92 


0.6A 


1.0A 


1W 


125 


170 


0.6A 


1.0A 



* l D (continuous) is limited by max rated Tj. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source Breakdown Voltage 


20 






V 


V GS = 0, l D = 1mA 


V GS(th) 


Gate Threshold Voltage 


0.5 


0.8 


1.0 


V 


v gs = v ds. Id = 1 0mA 


AV GS(th) 


Change in V GS(th) with Temperature 






-4.0 


mV/°C 


V gs = v ds> l D = 1.0mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±20V, V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






100 


nA 


V DS = 20V, V GS = 0V 








100 


uA 


v D s — u.o Max nanny, 
V GS = 0V,T A =125°C 


'd(ON) 


ON-Statp Drain Currpnt 

V-/ 1 v O ICllw \~J 1 CI 111 W Ul Iwl 11 


0.5 


1.0 




A 


V gs = V ds =5V 








4.0 


5.0 


Q 


Vr-= = 2V In = 50mA 

* fj£> *— " 5 ']_) Wl 1 II \ 


"DS(ON) 


ON-State Resistance 




1 .9 


2.5 




V„^ - 3V l„ - 200mA 








1.0 


1.3 




V GS = 5V, l D =500mA 


A RdS(ON) 


Change in R DS(0N) with Temperature 






0.75 


%/°C 


V GS = 5V, l D = 500mA 


G FS 


Forward Transconductance 


100 


500 




mt! 


V DS = 5V, l D = 500mA 


Ciss 


Input Capacitance 




130 


200 






Coss 


Common Source Output Capacitance 




70 


125 


PF 


V GS = 0V, V DS = 20V, f =1MHz 


Crss 


Reverse Transfer Capacitance 




30 


60 








Turn-ON Delay Time 






20 




V DD =20V, l D = 0.5A, 
Rgen = 25Q 


t, 


Rise Time 






20 


ns 


td(OFF) 


Turn-OFF Delay Time 






30 




t, 


Fall Time 






20 






V SD 


Diode Forward Voltage Drop 


I 10 


V 


V GS = 0V, l SD = 0.5A 



Notes: 

1 . All D C. parameters 1 00% tested at 25°C unless otherwide stated. (Pulse test: 300 us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




7-38 



Typical Performance Curves 



Output Characteristics 



5 

















— 

v G 




S = 8V 







A 
















/ 
















/ 








Vqs = 6V 














1 

S = 5V 












— V C 








i — 


, 1 1 












V GS =4V 














S=3V 














- V C 
















S = 2V 












Vc 










1 1 



5 10 15 20 



V DS (volts) 
Transconductance vs. Drain Current 



o 



























s = - 


































































-D 


= -f 




























I I 


















= 2 
- " 


5°C 


















T, 


r - 

>5°C 













































1 2 3 4 5 



l D (amperes) 
Maximum Rated Safe Operating Area 



0.1 



0.01 



























































































































T 


0-9 


'. (F 


U 


s 


>d) 
















































































H 
































































s 


s 



































































































































































0.1 1 10 100 



V DS (volts) 



Saturation Characteristics 



5 



4 





















1 

V GS = 8 


























































Vqs = 6V 


















I 

S = 5V — 
















U Vq 










I I 
















V GS = 4V 


















I 1— 

S = 3V — 














- v G 


















S = 2V — 
















- v G 



















2 4 6 8 10 



V DS (volts) 



Power Dissipation vs. Case Temperature 



2.0 



□ 
0- 























































TO- 


12 







































































25 50 75 100 125 150 



T C (°C) 



Thermal Response Characteristics 



10 



a 



o 





































TC 


-92 






T C = 25°C 








— 1 VV M 





























0.001 0.01 0.1 1 10 



tp (seconds) 

7-39 



Typical Performance Curves 

BV DSS Variation with Temperature 



On-Resistance vs. Drain Current 




7-40 



ft 



TN25A 

Low Threshold 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV DSS / 


"dS(ON) 

(max) 


^GS(lh) 

(max) 


'd<on) 
(min) 


Order Number / Package 


TO-243AA* 


DICE* 


60V 


1.5£1 


1.6V 


3.0A 




TN2506ND 


100V 


1.50 


1.6V 


3.0A 


TN2510N8 


TN2510ND 



* Same as SOT-89. 
1 MIL visual screening available. 

Features 

□ Low threshold — 1 .6V max. 

□ High input impedance 

□ Low input capacitance — 1 25 pF max. 

□ Fast switching speeds 

□ Low on resistance 

Free from secondary breakdown 

□ Low input and output leakage 

□ Complementary N- and P-channel devices 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-otf) transis- 
tors utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Applications 

□ Logic level interface - ideal for TTL and CMOS 

□ Solid state relays 

□ Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°CtO+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Package Options 



TO-243AA 
(SOT-89) 



Note: See Package Outline section for discrete pinouts. 



7-41 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 


6 ic 




■dr 


'drm 








@ T A = 25°C 


°c/w 


°c/w 






TO-243AA 


1.3A 


5.0A 


1.6W* 


15 


78t 


1.3A 


5.0A 



* l D (continuous) is limited by max rated T. 

t Mounted on FR5 board, 25mm x 25mm x 1.57mm. Significant P increase possible on ceramic substrate. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


TN2510 


100 






V 


V GS = 0, l D = 2mA 


TN2506 


60 


V GS(th) 


Gate Threshold Voltage 


0.6 




1.6 


V 


V GS = v ds. !d= 1mA 




Change in V GS(th) with Temperature 






-4.5 


mV/°C 


V G s = V DS . b= 10mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = + 20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = Max Rating 


1.0 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


1.2 


2.0 




A 


V GS = 5V, V DS = 25V 


3.0 


6.0 




V GS = 10V, V DS = 25V 


^DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




1.5 


2.0 


a 


V GS = 5V, l D = 750mA 


1.0 


1.5 


V GS = 10V, l D = 750mA 


AR DS(ON) 


Change in R ds(0 n) witn Temperature 






0.75 


%/°c 


V GS = 10V, l D = 0.5A 


Gfs 


Forward Transconductance 


0.4 


0.8 




u 


V DS = 25V, l D = 1.0A 


Ciss 


Input Capacitance 




70 


125 


PF 


V GS = 0, V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




30 


70 


Crss 


Reverse Transfer Capacitance 




15 


25 


•d(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = 25V, 
l D = 1 .5A, 
^GEN = 25£2 


tr 


Rise Time 






10 


'd(OFF) 


Turn-OFF Delay Time 






20 


t. 


Fall Time 






10 


v SD 


Diode Forward Voltage Drop 






1.8 


V 


V GS = 0, l SD = 1.5A 


trr 


Reverse Recovery Time 




300 




ns 


V GS = 0, l SD = 1.5A 



1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300ns pulse. 2% duty cycle.) 

2. All A.C. parameters sample tested. 




7-42 



Typical Performance Curves 



Output Characteristics 



TN25A 



Saturation Characteristics 



Q. 

E 

Q 




10 20 30 

V DS (volts) 
Transconductance vs. Drain Current 



i£ o.a 
CD 





I I 


















S = ' 
















































Ta 


= -5£ 


°C 
























































T A = 25°C 
















L-L. 


.. 
















Ta 


= 12 


5°C 













































1 2 3 4 5 

l D (amperes) 
Maximum Rated Safe Operating Area 



E 

CO 



































































































> 


< 


TO- 
. 


243 


kA 


P 


J 


ssd) 




















\ 










T A 


= 25 


'C 


















X 






























\ 
































N 


































k 








































































— T< 


>2< 


3A 


A 










































































































V DS (volts) 

Power Dissipation vs. Ambient Temperature 



D 
0- 















TO-2 


43AA 











































































































25 50 75 100 125 150 

T C (°C) 

Thermal Response Characteristics 



J* 0.8 

to 
E 

g 



CD 













































TO-2< 
PD = 


3AA 






t c = : 


).55W ^ 

>5°C / 





























10 100 

V DS (volts) 



0.001 0.01 0.1 1 10 

tp (seconds) 



7-43 



TN25A 



Typical Performance Curves 



BV DSS Variation with Temperature On-Resistance vs. Drain Current 




V DS (volts) Q G (nanocoulombs) 



7-44 



TN25C 

Low Threshold 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV DSS / 
BV D0S 


R DS(ON) 

(max) 


VGS(th) 

(max) 


'd(ON) 

(min) 


Order Number / Package 


TO-243AA* 


DICE 


200V 




2.0V 


1.0A 




TN2520ND 


240V 


en 


2.0V 


1.0A 


TN2524N8 


TN2524ND 



' Same as SOT-89. 



Features 

P Low threshold — 2.0V max. 

□ High input impedance 

Low input capacitance — 125 pF max. 

□ Fast switching speeds 

□ Low on resistance 

□ Free from secondary breakdown 

□ Low input and output leakage 

□ Complementary N- and P-channel devices 

Applications 

Logic level interface - ideal for TTL and CMOS 

i Solid state relays 

□ Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertax's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Package Options 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°CtO+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



TO-243AA 
(SOT-89) 



Note: See Package Outline section for discrete pinouts. 



7-45 



TN25C 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 


*ic 




I * 

>DR 


•drm 








@ T A = 25°C 


C/W 


C/W 






TO-243AA 


0.8A 


2.0A 


1.6W* 


15 


78t 


0.8A 


2.0A 



* l (continuous) is limited by max rated T. 

f Mounted on FR5 board, 25mm x 25mm x 1.57mm. Significant P D increase possible on ceramic substrate. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


TN2524 


240 






V 


V GS = 0, l D = 2mA 


TN2520 


200 




Gate Threshold Voltage 


0.6 




2.0 


V 


V G s = v ds. *d= 1mA 




Change in V GS(lh) with Temperature 






-5.0 


mV/°C 


v gs = v ds. b= 1mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = + 20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = Max Rating 


1.0 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


!d(ON) 


vjiN-oiaie urain L/Urreni 


u.o 


1 Q 




A 


V GS = 4.5V, V DS = 25V 


1 n 






V GS = 10V, V DS = 25V 


■*DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




4.0 


6.0 


a 


V^o - 4 5V U= 250mA 


*t,v 


n 


VQg — lUV, Iq — U.DM 


— = 

" n DS(ON) 


Change in R DS( on) wittl Temperature 






1.4 


%/°c 


V^c = 10V. L = 5A 


G FS 


Forward Transconductance 


300 


600 




mrj 


V DS = 25V, l c = 0.5A 


C ISS 


Input Capacitance 




65 


125 


pF 


V GS = 0, V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




35 


70 


Crss 


Reverse Transfer Capacitance 




10 


25 


•d(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = 25V, 
l D = 1 OA, 
Rqen = 25Q 


tr 


Rise Time 






10 


'd(OFF) 


Turn-OFF Delay Time 






20 


tf 


Fall Time 






20 


V SD 


Diode Forward Voltage Drop 






1.8 


V 


V GS = 0, l sc = 1.0A 




Reverse Recovery Time 




300 




ns 


V GS = 0, l SD = 1-0A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




Typical Performance Curves 

Output Characteristics 



0.8 







































L 


















v 


3S = 


10V 




















OV 






— 














6V 


























































4V 






















t 


















3V 








































2V 



10 20 30 40 50 

V DS (volts) 
Transconductance vs. Drain Current 




Maximum Rated Safe Operating Area 



8. 
E 
a 



0.01 























! , ! 


























































TO-243AA 


(pulsed) 




























N 

\ 


S— 




























































S 
































"r- 
> 


































< 


» 






























> 






































































































TO-243AA (DC) ^ 















































10 100 1000 

V DS (volts) 



TN25C 

Saturation Characteristics 



2.0 



c§ 1.0 







































s = ' 


OV. 














8 




6V- 






































4V 




























































3V 








































2V 





4 6 

V DS (volts) 



8 10 



Power Dissipation vs. AmbientTemperature 



Q 
0- 































0-243A 





























































































25 50 75 100 125 150 

T C (°C) 

Thermal Response Characteristics 



1.0 



J 0.8 
3 

I 

-S 0.6 

<u 
u 
c 

(0 

I 0.4 

6 
0C 





































TA 


O A A 






P D =0.55W J 






Tc=2 































0.001 0.01 0.1 

tp (seconds) 



10 



7-47 



Typical Performance Curves 

BV DSS Variation with Temperature 




E 

£ 



Q 
DC 



TN25C 



On-Resistance vs. Drain Current 

























— \ 


'gs 


= 4.5 








































FV 


3S = 


10V 































































































































12 3 4 

l D (amperes) 



Transfer Characteristics 



V (th) and R DS Variation with Temperature 



Q. 

E 

CO 





I I 

V DS = 25V 




' 1 


1 

5°C 
i 


/ 










Ta = 


-55 


C / 


/ 
/ 


4 

t 

1 


15C 
















' J 
t 

t 


• 
















'/ ' 
// 





















































2 4 6 8 1( 

V GS (volts) 

Capacitance vs. Drain-to-Source Voltage 



200 



o 

Q. 



t 


= 1MHz 
















' 




C ISS 














c oss 








Cqss 



10 20 30 

V DS (volts) 



CO 

E 

o 1.0 

I 

J? 0,8 



























3S(ON 


@ 1( 


)V, 0.! 


>A 








R 






1mA 











































































































1.6 « 
E 



0.4 



50 100 150 

TjCC) 

Gate Drive Dynamic Characteristics 



> 































V 


OS - 


10V 




























































v D s 

pF 


= 4( 


V - 














- 15 






— 


























































63pF 















0.4 0.8 1.2 1.6 2.0 

Qg (nanocoulombs) 



7-48 



(fi) Supertexinc. 



TN25D 

Low Threshold 



1 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV DSS / 
BV DGS 


"ds<on) 
(max) 


(max) 


81 


Order Number / Package 


TO-243AA* 


DICE* 


350V 


i2n 


1.8V 


1.0A 




TN2535ND 


400V 


12Q 


1.8V 


1.0A 


TN2540N8 


TN2540ND 



* Same as SOT-89. 

* MIL visual screening available. 

Features 

Low threshold — 1 ,8V max. 

□ High input impedance 

Low input capacitance — 1 25 pF max. 

□ Fast switching speeds 
Low on resistance 

Free from secondary breakdown 
Low input and output leakage 
Complementary N- and P-channel devices 

Applications 

□ Logic level interface - ideal for TTL and CMOS 
Solid state relays 

Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

I General purpose line driver 

□ Telecom switches 

Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertax's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Package Options 



















TO-243AA 
(SOT-89) 




Note: See Package Outline section for discrete pinouts. 





TN25D 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 






I * 
■dr 


'drm 








@ T A = 25°C 


cm 


cm 






TO-243AA 


570mA 


1.8A 


1.6Wt 


15 


78t 


570mA 


1.8A 



* l D (continuous) is limited by max rated T. 

T Mounted on FR5 board, 25mm x 25mm x 1 .57mm. Significant P D increase possible on ceramic substrate. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


TN2540 


400 






V 


V GS = 0, l D = 100uA 


TN2535 


350 


V GS(th) 


Gate Threshold Voltage 


0.6 




1.8 


V 


v gs = V D s. b= 1mA 




Change in V GS(th) with Temperature 




-2.5 


-4.0 


mV/°C 


V GS = V DS , l D = 1 mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±20V, V DS = 


bss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = Max Rating 


1.0 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


!d(ON) 


ON-State Drain Current 


0.3 


0.5 




A 


V GS = 4.5V, V DS = 25V 


1.0 


1.4 




V GS = 10V, V DS = 25V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




8.0 


12 


n 


V GS = 4.5V, l D = 150mA 


8.0 


12 


V GS = 10V, l D = 0.5A 


AR DS(ON) 


Change in R DS (on) witn Temperature 






0.75 


%/°c 


V GS = 10V, l D = 500mA 




Forward Transconductance 


125 


200 






V DS = 25V, l D = 100mA 


C ISS 


Input Capacitance 




95 


125 


pF 


V GS = 0, V DS = 25V 
f = 1 MHz 


&OSS 


Common Source Output Capacitance 




20 


70 


Crss 


Reverse Transfer Capacitance 




10 


25 


'd(ON) 


Turn-ON Delay Time 






20 


ns 


V DD = 25V, 
l D = 1A, 
R GEN = 25C2 


tr 


Rise Time 






15 


'd(OFF) 


Turn-OFF Delay Time 






25 


tf 


Fall Time 






20 


V SD 


Diode Forward Voltage Drop 






1.8 


V 


v gs = 0. Isd = 200mA 


trr 


Reverse Recovery Time 


i 


300 




ns 


V GS = 0, l SD = 1A 



Notes: 

1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




7-50 



TN25D 



Typical Performance Curves 

Output Characteristics 



g 12 



<n 

Q. 

£ 
to 















1 








































\ 


10V 






























> 































































































































































10 20 30 40 50 

V DS (volts) 
Transconductance vs. Drain Current 



CD 



Vr. 


s =2£ 


V 








































































= -55°C 












— 25°C — 












— — 

125 


r 

c 



































0.2 0.4 0.6 0.8 1.0 1.2 1.4 

l (amperes) 
Maximum Rated Safe Operating Area 



E 
Q 























1 1 1 


























= 2 


























■ 1 
















































\ 


TC 


-2h 


3 






sed 




















\ 






























V 
































S 

-* 
































— 


> 
































> 

\ 
































\ 








































TO-243A/I 


(DC 


















































































10 100 

V DS (volts) 



■ 

Saturation Characteristics 



o 







































iS 


v 





































































































































































































2 4 6 8 10 

V DS (volts) 

Power Dissipation vs. Ambient Temperature 



g 
□ 
a. 















TO-2 


43AA 











































































































25 50 75 100 125 150 
T C (°C) 

Thermal Response Characteristics 



-— 0.8 



8 0-4 































TO-243A/ 


I / 






P D =0.55W / 






' c — 





































0.001 0.01 0.1 1 

tp (seconds) 



7-51 



TN25D 



Typical Performance Curves 

BV DSS Variation with Temperature 




100 150 



Transfer Characteristics 



£ 0.9 
<B 

a. 
E 

-2- 

a 0.6 





I I 


















3 =* 


sv 


















































= 55' 


C 


































25°C v 





































' — 






















"125 























2 4 6 8 1( 

V GS (volts) 
Capacitance vs. Drain-to-Source Voltage 



03 

8 100 



o 





JHz 






















Crss 









On-Resistance vs. Drain Current 



J 30 
o 



o 

» 20 

Q 



























v G s = 


4.5\ 






















s = 


10V 

















































































































































0.4 0.8 1.2 1.6 2.0 

l D (amperes) 
V (th) and R DS Variation with Temperature 



ns 
E 

6 i.o 















I 








R 


3S(ON 




)@ 1C 


V, 0.5A 


v 




1mA 























































































































1.5 « 
O 

1.0 o 
0.5 



-50 50 100 

TjfC) 

Gate Drive Dynamic Characteristics 



> 





















































V D! 


5=1 


OV 




























































^DS 


= 40 


V - 














60 p 














F — 



































































10 20 30 

V DS (volts) 



0.4 0.8 1.2 1.6 2.0 

Qlq (nanocoulombs) 



7-52 



TN25L 

Low Threshold 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV DSS / 


"ds<on) 




'd(ON) 


Order Number / Package 




(max) 


(max) 


(min) 


TO-243AA* 


DICE* 


20V 


1.0£2 


1.6V 


4.0A 




TN2502ND 


40V 


i.on 


1.6V 


4.0A 


TN2504N8 


TN2504ND 



* Same as SOT-89. 

' MIL visual screening available. 



Features 

□ Low threshold — 1 .6V max. 
I High input impedance 

I Low input capacitance — 1 25 pF max. 

I Fast switching speeds 

P Low on resistance 

□ Free from secondary breakdown 

□ Low input and output leakage 

□ Complementary N- and P-channel devices 



Low Threshold 



Technology 



These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Applications 

□ Logic level interface - ideal for TTL and CMOS 
Solid state relays 

B Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 



Package Options 



Distance of 1 .6 mm from case for 1 seconds. 




TO-243AA 
(SOT-89) 



Note: See Package Outline section for discrete pinouts. 



7-53 



TN25L 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 






■ * 
■dr 


'drm 








@ T A = 25°C 


°c/w 


°c/w 






TO-243AA 


2.0A 


4.5A 


1.6W1- 


15 


78* 


2.0A 


4.5A 



* l D (continuous) is limited by max rated Tj. 

t Mounted on FR5 board, 25mm x 25mm x 1 .57mm. Significant P D increase possible on ceramic substrate. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to- Source 
Breakdown Voltage 


TN2504 


40 






V 


V GS = 0, l D = 2mA 


TN2502 


20 


V GS(th) 


Gate Threshold Voltage 


0.6 




1.6 


V 


V G s = V DS . I D = 1 mA 


AV GS(th) 


Change in V GS(th) with Temperature 




-3.8 


-4.5 


mV/°C 


V GS = v ds> 1d= 1mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V QS = 0, V DS = Max Rating 


1 


mA 


V G s = °. v ds = 0.8 Max Rating 
T A = 1 25°C 


!d(on) 


ON-State Drain Current 


1.0 


1.7 




A 


V GS = 5V,V DS = 15V 


4.0 


4.5 




V GS =10V, V DS = 15V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




1.25 


1.5 


n 


V GS = 5V, l D = 300mA 


0.8 


1.0 


V GS = 10V, l D = 1.5A 


AR DS(ON) 


Change in R ds(0 n) with Temperature 






0.75 


%/°c 


V GS = 10V, l D = 1.5A 


G FS 


Forward Transconductance 


0.5 


0.7 




u 


V DS = 15V, l D = 2.0A 


C lSS 


Input Capacitance 




70 


125 


PF 


V GS = 0, V DS = 20V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




50 


70 


Crss 


Reverse Transfer Capacitance 




20 


25 


'd(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = 20V, 
l D = 500mA, 
R GEN = 25£J 


tr 


Rise Time 






10 


l d(OFF) 


Turn-OFF Delay Time 






25 


<f 


Fall Time 






13 


v SD 


Diode Forward Voltage Drop 




1.2 


1.8 


V 


V GS = 0, l SD = 1 -5A 


trr 


Reverse Recovery Time 




300 




ns 


V GS = 0, l SD = 1A 



I , 1 1 1 1 1 

Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300ns pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




7-54 



TN25L 



Typical Performance Curves 

Output Characteristics 




10 20 30 40 

V DS (volts) 
Transconductance vs. Drain Current 



o 

I 1.0 



























,= 1 


5V 


















































































= -5 


5°C 


















_2 


























125°C 










A 







































12 3 4 

l D (amperes) 
Maximum Rated Safe Operating Area 



CD 
Q- 

E 



TO 


- 
24 


- 
3A 


W 
A 


■J 

(puis 


' — 
ed 


) 




1 

T A = 


r— 
25' 


— 
C 












































— 
> 


N 














































































TC 


)-2 


43 


W 


i (DC 


) 















































































































1 10 

V DS (volts) 



100 



Saturation Characteristics 



o « 









i i i 

V^n=10V 










































































































































A 
















w 


V 


















f M 
















■4V 






















r2 


















— — 



4 6 8 

V DS (volts) 



10 



Power Dissipation vs. Ambient Temperature 



B 
a 
S 















































TO 


-243A 







































































25 50 75 100 125 150 

T c CO 

Thermal Response Characteristics 





































TO-243AA 






| P D = 0.55W- 

T c = 25°C / 





































0.001 0.01 0.1 1 

tp (seconds) 



10 



7-55 



TN25L 



Typical Performance Curves 

BV DSS Variation with Temperature 




a 6 



50 100 

Tj (°C) 
Transfer Characteristics 

























V 


DS - 


15V 
















































-55 
















Ia = 

I 














25 


°c- 





















































































On-Resistance vs. Drain Current 



E 
sz 

o 



D? 




V,, h) and Ros Variation with Temperature 



e 1-2 
I 

CO 

E 



■> 0.8 



























} 10V 


, 1.5/ 







































































































































<» 
N 

1.2 To 
E 

o 
c 

io i 



2 4 6 8 10 

V GS (volts) 



50 

T, (°C) 



100 150 



Capacitance vs. Drain-to-Source Voltage 



Gate Drive Dynamic Characteristics 



■o 

CO 

I 

o 




10 20 30 40 

V DS (volts) 



10 



-> 4 































= 1 


OV 
















I I J 

130 dF7 


















































































' \ 


'ds - 


40\ 


t 












































I 

















0.4 0.8 1.2 1.6 2.0 

Q G (nanocoulombs) 



7-56 



TN25U 



Low Threshold 



Preliminary 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV DSS / 


R DS(ON) 


'd(ON) 


V GS (th) 


Order Number /Package 


BV DGS 


(max) 


(min) 


(max) 


TO-243AA* 


DICE+ 


18V 


2.5a 


250mA 


0.8V 


TN2501N8 


TN2501ND 



*Same as SOT-89. 

t MIL visual screening available. 

Features 

P Low threshold — 0.8V max. 

□ High input impedance 

□ Low input capacitance — 1 1 0pF max. 

□ Fast switching speeds 

□ Low on resistance 

p Free from secondary breakdown 

□ Low input and output leakage 



Applications 

Z Logic level interface - ideal for TTL and CMOS 

D Solid state relays 

□ Battery operated systems 
C Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 



Absolute Maximum Ratings 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±15V 


Operating and Storage Temperature 


-55°C to+150°C 


Soldering Temperature* 


300°C 



Distance ol 1 .6 mm from case for 10 seconds. 



Low Threshold DMOS Technology ^ 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Package Options 




7-57 



TN25U 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 
® T A = 25°C 


°c/w 


% 
°C/W 


'dr 


'drm 


TO-243AA 


400mA 


750mA 


1.6Wt 


15 


78t 


400mA 


750mA 



* l D (continuous) is limited by max rated T r 

t Mounted on FR5 board, 25mm x 25mm x 1 .57mm. Significant P D increase possible on ceramic substrate. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source Breakdown Voltage 


18 






V 


V GS = 0, l D = 1.0mA 


V GS(tti) 


Gate Threshold Voltage 


0.3 




0.8 


V 


V G s = V D s. l D =10mA 


AV GS(th) 


Change in V GS(ttl) with Temperature 






-4.0 


mV/°C 


V G s = V D s. I D = 1.0mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±15V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = Max Rating 


1.0 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


250 


600 




mA 


V GS = V DS = 3.0V 


^DS(ON) 


Static Drain-to-Source 
ON-Statp Rp<SKt?inrp 






25 


Q 


V GS = 1 .0V, Ip = 3.0mA 






3.5 


V GS = 2.0V, l D = 50mA 






2.5 


V GS ■ 3.0V, l D = 200mA 


AR DS(ON) 


Change in R ds(0 n) with Temperature 






0.75 


%/°C 


V GS = 3.0V, Ip = 200mA 




Forward Transconductance 


0.15 


0.3 




u 


V DS = 3.0V, l D = 200mA 




Input Capacitance 






110 


pF 


V GS = 0, V DS = 15V 
f = 1 MHz 


c oss 


Common Source Output Capacitance 






60 


C RSS 




Reverse Transfer Capacitance 






35 


td(ON) 


Turn-ON Delay Time 






5.0 


ns 


V DD = 15V, 
Ip = 250mA, 
R GEN = 25Ji 


t r 


Rise Time 






15 


'd(OFF) 


Tum-OFF Delay Time 






15 


t) 


Fall Time 






8.0 


V SD 


Diode Forward Voltage Drop 




1.1 


1.8 


V 


V GS = 0, l SD = 200mA 


trr 


Reverse Recovery Time 




100 




ns 


V GS = 0, l SD = 200mA 



Notes: 

1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300usec pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




TN25U 



Typical Performance Curves 

Output Characteristics 



0) q 
J) J 

s 

a. 
E 

tO 

2 





























— 








* 

GS~ 


ov 








f 












8V 






j 

/ 




















-H 
1/ 


















[ 
















6V 




V 










































































4V 








































3V 
















1 — 1 — 







10 

V DS (volts) 



s? 
1 

CL 

B 0.4 



Saturation Characteristics 

































































— 














Vqs 


= 4V 






r 






















































.21 






















t 


















2V 






































1V 



2 4 6 

V DS (volts) 



Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



s 

g> 0.5 



1 




= 3V 
































































^ = "! 


55°C 






































^25°C 


















^ T 1 

125°C 





































































0.2 0.4 0.6 0.8 1.0 

l D (amperes) 



a 

0- 















TO-2 


43AA 











































































































25 50 75 100 125 150 

T C (°C) 



Maximum Rated Sate Operating Area 



0.01 



TO-243AA(pulsed) 



TO-243AA (DC) 



1.0 10 

V DS (volts) 



100 



Thermal Response Characteristics 



o 

1 





























TO 


•243AA 






P D =1.6W 






Tc 


= 25°C 





































0.001 0.01 0.1 

tp (seconds) 



7-59 



TN25U 



Typical Performance Curves 

BV DSS Variation with Temperature 



2 1.0 




Transfer Characteristics 



S 0.6 























5 =1 
























































































= -5 


5°C 




✓ 


















■25°( 
















V 






















125' 


C 

























2 4 6 8 1( 

V GS (volts) 
Capacitance vs. Drain-to-Source Voltage 



2 
a 
o 
o 

O 





f = 1MHz 












Ciss 












Coss 








Crss 



5 10 15 

V DS (volts) 



On-Resistance vs. I D 



o 

co 4 

























































= 2\ 


















































Vq 


s = 




































1 








— x 





























































0.2 0.4 0.6 0.8 1.0 

l D (amperes) 
V (th ) and R DS Variation with Temperature 



as 
E 

o 1.0 



£ 0.1 





















Rds< 


3N) • 


Vgs 


= 3V, 


Id = 


.2A j 






















V (t h)@ 


1mA 











































































































1.2 a 

i 

o 



SO 100 

TjfC) 

Gate Drive Dynamic Characteristics 



> 















































v DS = iov y 














K 


SO pF 


























Vd. 


5=1 


5V 






















































































I 

















0.4 0.8 1.2 1.6 2.0 

Qq (nanocoulombs) 



7-60 



TN26D 

Low Threshold 



Preliminary 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV DSS / 


"ds<on) 
(max) 


V GS<th) 

(max) 


II 


Order Number / Package 


TO-92 


DICE+ 


350V 


5.0£2 


2.0V 


2.0A 


TN2635N3 


TN2635ND 


400V 


5.0ii 


2.0V 


2.0A 


TN2640N3 


TN2640ND 



* MIL visual screening available. 

Features 

C Low threshold — 2.0V max. 

□ High input impedance 

□ Low input capacitance 

□ Fast switching speeds 

□ Low on resistance 

□ Free from secondary breakdown 

□ Low input and output leakage 

□ Complementary N- and P-channel devices 

Applications 

□ Logic level interface - ideal for TTL and CMOS 
D Solid state relays 

n Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 

Absolute Maximum Ratings 

Drain-to-Source Voltage 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Package Options 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°CtO+150°C 


Soldering Temperature* 


300°C 


* Distance of 1.6 mm from case for 10 seconds. 



TO-92 



Note: See Package Outline section for discrete pinouts. 




TN26D 



Thermal Characteristics 



Package 



l D (continuous)* 



l D (pulsed) 



Power Dissipation 
@ T c = 25°C 



C/W 



C/W 



TO-92 



0.4A 



3 (continuous) is limited by max rated T. 



2.0A 




LOW 



125 

' ' 



170 



0.4A 2.0A 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


TN2640 


400 






V 


V GS = 0, l D = 1mA 


TN2635 


350 


^GSIth) 


Gate Threshold Voltage 


0.8 




2.0 


V 


v GS = v DS . !d= 2mA 


A V GS(t ri) 


Change in V GS(th) with Temperature 




-2.5 


-4.0 


mV/°C 


V G s = V DS , l D =1mA 


'gss 




Gate Body Leakage 






100 


nA 


V GS = ± 20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


(iA 


V GS = 0, V DS = Max Rating 


1 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'□(ON) 


ON-State Drain Current 


1.5 


3.5 




A 


V GS = 5V, V DS = 25V 


2.0 


4.0 




V GS = 10V, V DS = 25V 




Static Drain-to-Source 
ON-State Resistance 




3.2 


5.0 


Q 


V GS = 5V, l D = 150mA 


3.0 


5.0 


V GS = 10V, l D = 500mA 




Change in R ds(0 n) witn Temperature 






0.75 


%/°C 


V GS = 10V, l D = 500mA 


G FS 


Forward Transconductance 


200 


330 




mU 


V DS = 25V, l D = 100mA 


C ISS 


Input Capacitance 




180 


225 


PF 


V GS = 0, V DS = 25V 
f = 1 MHz 


c oss 


Common Source Output Capacitance 




35 


70 


Crss 


Reverse Transfer Capacitance 




7 


25 


td(ON) 


Turn-ON Delay Time 




4 


15 


ns 


V DD = 25V, 
l D = 2A, 
R G EN = 


t, 


Rise Time 




15 


20 


'd(OFF) 


Turn-OFF Delay Time 




20 


25 


t, 


Fall Time 




22 


27 


V SD 


Diode Forward Voltage Drop 






0.9 


V 


V GS = 0, l SD = 200mA 


trr 


Reverse Recovery Time 




300 




ns 


v gs = 0. ho= 1A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




TP01L 

Low Threshold 



Sfii 



P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DGS 


"ds<on) 
(max) 


V GS(th) 

(max) 


>D(ON) 

(min) 


Order Number / Package 


TO-39 


TO-92 


TO-243AA* 


DICE* 


-20V 


4.0Q 


-2.4V 


-0.85A 


TP0102N2 


TP0102N3 




TP0102ND 


-40V 


4.on 


-2.4V 


-0.85A 


TP0104N2 


TP0104N3 


TP0104N8 


TP0104ND 



* Same as SOT-89. 

* MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Low threshold — 2.4V max. 

□ High input impedance 
'— Low input capacitance 

□ Fast switching speeds 

□ Low on resistance 

□ Free from secondary breakdown 

□ Low input and output leakage 

□ Complementary N- and P-channel devices 

Applications 

□ Logic level interface - ideal for TTL and CMOS 

□ Solid state relays 

□ Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* For TO-39 and TO-92, distance of 1 .6 mm from ca 


se for 10 seconds. 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertax's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Package Options 




TO-243AA 
(SOT-89) 



TO-92 



Note: See Package Outline section for discrete pinouts. 



7-63 



TP01L 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 
e T c = 25°C 


ic 

CAW 


°C/W 


'dr* 


'drm 


TO-39 


-0.9A 


-2.0A 


3.50W 


35 


125 


-0.90A 


-2.0A 


TO-92 


-0.5A 


-2.0A 


1.00W 


125 


170 


-0.50A 


-2.0A 


TO-243AA 


-1.0A 


-2.0A 




15 


78t 


-0.26A 


-2.0A 



* l D (continuous) is limited by max rated Tj. 

t Mounted on FR5 board, 25mm x 25mm x 1.57mm. Significant P D increase possible on ceramic substrate. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


TP0104 


-40 






V 




V G s = °> 'd = " 1 0mA 


TP0102 


-20 


^GSfth) 


Gate Threshold Voltage 


-1.0 




-2.4 


V 


Vqs = V DS . Id = -1 -0mA 




Change in V GS(th) with Temperature 




-5.8 


-6.5 


mV/°C 


v gs = v ds. l D = -10mA 


'gss 


Gate Body Leakage 




-1.0 


-100 


nA 


V GS = ±20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






-10 


\iA 


V GS = 0, V DS = Max Rating 


-1 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'D(ON) 


ON-State Drain Current 




.n nft 




A 

A 


V GS = -3V, V DS = -20V 


-U.£lO 


-0.50 


V GS = -5V, V DS = -20V 


-0.85 


-1 .70 


V GS = -10V, V DS = -20V 


n DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




15 




£2 


V^o - -3V L - -25mA 


4.7 


7.5 


V GS = -5V, l D = -0.1A 


2.5 


4.0 


V GS = -10V, l D = -0.5A 


A RdS(ON) 


Change in R DS (oni) witn Temperature 




0.55 


1.0 


%/°C 


l D = -0.5A, V GS = -10V 


Gfs 


Forward Transconductance 


225 


250 




mi! 


Vn S = -20V, l D = -0.5A 


C ISS 


Input Capacitance 






60 


pF 


V GS = 0, V DS = -20V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 






50 


C RSS 


Reverse Transfer Capacitance 






25 


'd(ON) 


Turn-ON Delay Time 




4.0 


6.0 


ns 


V DD = -20V, l D =-0.85A 

R GEN = 25£1 


1, 


Rise Time 




7.0 


10 


'd(OFF) 


Turn-OFF Delay Time 




3.0 


9.0 


ti 


Fall Time 




4.0 


13 


v SD 


Diode Forward Voltage Drop 




-1.2 


-2.0 


V 


l SD =-0.25A, V GS = 


trr 


Reverse Recovery Time 




300 




ns 


l SD = -0.25A, V GS = 



Notes: 

1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 



INPUT 



OUTPUT 




TP01L 



Typical Performance Curves 

Output Characteristics 























































V 


GS = 


-10V 














































































-6V 




1 
































-4V 

























-10 -20 -30 -40 -50 

V DS (volts) 



Saturation Characteristics 




-2-4-6 

V DS (volts) 



Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



E 

Vo 

2 0.2 

o 





























>5V 




























T A 


= -5£ 


°C- 
















< 


























































































T A = 


125 


°C 











































-0.4 -0.8 -1.2 -1.6 -2.0 

l D (amperes) 



o? 2 



























TO-39 




































TO-24 
0a = 2 


3AA 










5°C) 










TO-92 





































25 50 75 100 125 150 

T C (°C) 



Maximum Rated Safe Operating Area 



Thermal Response Characteristics 



(i> 

CL 

E 







































































i 


"0-3< 


(p 


























jlsed) 


























TO-£ 


43A> 


31 - 




















^- ^ ' A " — 


































— L-Ui- 
































1 U 






; 
















\ 






























— 





























































































































































-1 -10 

V DS (volts) 



^ 0.8 
M 

E 



0.4 



a 
E 































^_ 






P D =3.5W > 






T C =2 


5°C ✓ 


















0-92 






F 


D =1W 

C=25°C" 






^ 1 



0.001 0.01 0.1 

tp (seconds) 



Typical Performance Curves 

BV DSS Variation with Temperature 




100 150 



Transfer Characteristics 



£ -1.5 



























> = - 


>5V 
























Ta 


= -£ 


5°C 






















25° C 




































125°C 



















































































0-2-4-6-8-10 

V GS (volts) 
Capacitance vs. Drain-to-Source Voltage 



o. 

o 



\ ,= 


1MHz 




















- Ciss 








c oss 











-10 -20 -30 

V DS (volts) 



TP01L 



On-Resistance vs. Drain Current 



o 

S 4 
rr 







L 




















r 


GS = 


-5V 


































J 


f 


















I 




















































v G 


S="1 


ov 































































8K -1 -2 

Id (amperes) 
V (th ) and R DS Variation with Temperature 



I 

o 1.0 





































V v 


dh)@ 


-1mA 


































Rc 


SION) 

)V, -0 


9 












-1( 


5A 





































































1.2 € 
CD 

i 

o 

0.8 % 

o 

£ 



50 100 

Tj(°C) 

Gate Drive Dynamic Characteristics 

























v DS 


= -1 


0V 


























' -A 


3V 










75 
















































































































I I 



















0.2 0.4 0.6 0.8 1.0 

Q e (nanocoulombs) 



7-66 



TP06A 

Low Threshold 



MM 



P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


" DS(ON) 

(max) 


'd(ON) 


^GS(th) 

(max) 


Order Number / Package 


TO-39 


TO-92 


TO-220 


Quad P-DIP 


Quad C-DIP* 


DICE+ 


-60V 


3.5Q 


-1.5A 


-2.4V 


TP0606N2 


TP0606N3 


TP0606N5 


TP0606N6 


TP0606N7 


TP0606ND 


-100V 


3.5Q 


-1.5A 


-2.4V 


TP0610N2 


TP0610N3 


TP0610N5 






TP0610ND 



* 14 pin side brazed ceramic DIP 
f MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Low threshold 2.4V max 

□ High input impedance 

□ Low input capacitance — 80 pF typical 
C3 Fast switching speeds 

□ Low on resistance 

□ Free from secondary breakdown 

□ Low input and output leakage 

□ Complementary N- and P-channel devices 

Applications 

□ Logic level interface - ideal for TTL and CMOS 

□ Solid state relays 

□ Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Package Options 



TO-39 



TO-92 





TO-220 



14-Lead DIP 



Note 1 : See Package Outline section for discrete pinouts. 
Note 2: See Array section for quad pinouts. 



7-67 



TP06A 



Thermal Characteristics 





1 /rnntiniinu^i* 
■q ^uui hii iuuu&i 


i fnulsedl 


Power Dissipation 

@ T c = 25°C 


ft 

c/w 


ft, 

C/W 


1 * 

■DR 


'drm 


TO-39 


-1.0A 


-4.0A 


6W 


20 


125 


-0.8A 


-4.0A 


TO-92 


-0.5A 


-3.5A 


1W 


125 


170 


-0.4A 


-3.5A 


TO-220 


-2.0A 


-4.5A 


45W 


2.7 


70 


-2.0A 


-4.5A 


Plastic Dip 


Refer to Arrays & Special Functions Section. 


Ceramic Dip 



* l D (continuous) is limited by max rated Tj. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to- Source 
Breakdown Voltage 


TP0610 


-100 






V 


V GS = 0, l D = -2.0mA 


TP0606 


-60 


V GS(th) 


Gate Threshold Voltage 


-1.0 




-2.4 


V 


Vgs = V DS . I D = -1.0mA 




Change in V GS(th) with Temperature 






-5.0 


mV/°C 


v gs = v ds. I D = "1 0mA 


'gss 


Gate Body Leakage 






-100 


nA 


V GS = ±20V, V DS = 


tass 


Zero Gate Voltage Drain Current 






-10 


uA 


V GS = 0, V DS = Max Rating 


-1.0 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


-0.4 


-0.6 




A 


V GS = -5V, V DS = -25V 


-1.5 


-2.5 


V GS = -10V, V DS = -25V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




5.0 


7.0 




V GS = -5V, l D = -250mA 


3.0 


3.5 


V GS = -10V, l D = -0.75A 


AR DS(ON) 


Change in R DS (on) with Temperature 






1.7 


%/°c 


V GS = -10V, l c = -0.75A 


Gfs 


Forward Transconductance 


300 


400 




mrj 


V DS = -25V, l D = -0.75A 


Ciss 


Input Capacitance 




80 


150 


PF 


V GS = 0, V DS = -25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




50 


85 


C RSS 


Reverse Transfer Capacitance 




15 


35 


'd(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = -25V 
l D = -1.0A 
R GEN = 25£1 


tr 


Rise Time 






15 


td(OFF) 


Turn-OFF Delay Time 






20 


tf 


Fall Time 






15 


V SD 


Diode Forward Voltage Drop 






-1.8 


V 


V GS = 0, l SD = -1.0A 


trr 


Reverse Recovery Time 




300 




ns 


V GS = 0, l SD = -1 OA 



Notes: 

1 . All D.C. parameters 1 00% tested at 25"C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




TP06A 



Typical Performance Curves 



Output Characteristics 



Saturation Characteristics 




-10 -20 -30 -40 

V DS (volts) 




Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



0.4 



E 
2 

m 

2 0.3 

a 





I 

S = 


>5V 








= -5! 


)°C~ 






A 
























= 25 


°C 




























Ta 


= 15 





































































-0.4 -0.8 -1.2 -1.6 -2.0 -2.4 -2.8 -3.2 

l D (amperes) 



I 

Q 20 
GL 



TO-22 

































































































TO-3S 












TO-92 











25 50 75 100 125 150 

T C (°C) 



Maximum Rated Safe Operating Area 



Thermal Response Characteristics 



CL 

E 

(0 



I I III 
















TO 


39 


pu 


se 










































TO-220 
1— 


,0 


5) 




\ 


s 












.TO-39 (DC) 


































































:to 


92 


DC 















































































































-10 -100 

V DS (volts) 





^ 0.8 

I 

o 

£ 0.6 











to-: 


!20 






Pd ■ 


= 45W J 






T c = 


25° C X 


























^ TO-39 








P D =6W 






T C =2 


5°C 











0.001 



0.01 0.1 

tp (seconds) 



10 



7-69 



TP06A 



Typical Performance Curves 

BV DSS Variation with Temperature 




Transfer Characteristics 



-2. 

Q -2 



























; = - 


25V 






































































oO 




















































S 1 r. 


































1 







-2 -4 -6 -8 -II 

V GS (volts) 
Capacitance vs. Drain-to-Source Voltage 



200 



o 
o 
'a. 

O 









f = 1MHz 
















Ciss 






Coss 




- — 




c rss 









-10 -20 -30 -40 

V DS (volts) 



On-Resistance vs. Drain Current 



o 

to 6 
o 

rr 

























V 


GS = 


-5V 
































































s = 


10V 









































































































3 -0.8 -1.6 -2.4 -3.2 -4.0 

l D (amperes) 
V (th) and R D s Variation with Temperature 



E 

O 1.0 



V 0.£ 





















































v (.h) 


@ -1r 


nA 


















F 


DS(0 
OV, - 


M) @ 
).75A 















































































2.0 



1.2 



E 
o 

0.8 I" 
CO 
D? 

0.4 



50 

T,(°C) 



100 150 



Gate Drive Dynamic Characteristics 



<n -6 
"5 



<3 

> 































Vds — 


10V 












































200 


pF 




































= -40V 






























































f 7 ^ 

















0.5 1.0 1.5 2.0 2.5 

Q G (nanocoulombs) 



7-70 



TP06C 

Low Threshold 



1 



P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BVdos 


^DS(ON) 

(max) 




V GS(th) 
(max) 


Order Number / Package 


TO-39 


TO-92 


TO-220 


DICE+ 


-160V 


12Q 


-0.75A 


-2.4V 


TP0616N2 


TP0616N3 


TP0616N5 


TP0616ND 


-200V 


12£2 


-0.75A 


-2.4V 


TP0620N2 


TP0620N3 


TP0620N5 


TP0620ND 



f MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 



Features 

□ Low threshold 2.4 V max 

□ High input impedance 

□ Low input capacitance — 85 pF typical 

□ Fast switching speeds 

□ Low on resistance 

□ Free from secondary breakdown 

□ Low input and output leakage 

□ Complementary N- and P-channel devices 

Applications 

□ Logic level interface - ideal for TTL and CMOS 

□ Solid state relays 

□ Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°C to+150°C 


Soldering Temperature* 


300°C 


* Distance of 1.6 mm from case for 10 seconds. 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Package Options 




7-71 



TP06C 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 




9 ia 


■dr 


'drm 








@ T c = 25°C 


°c/w 


cm 






TO-39 


-0.6A 


-1.5A 


6W 


20 


125 


-0.6A 


-1.5A 


TO-92 


-0.4A 


-0.8A 


1W 


125 


170 


-0.4A 


-0.8A 


TO-220 


-1.4A 


-2.5A 


45W 


2.7 

1 


70 


-1.4A 


-2.5A 



' l D (continuous) is limited by max rated T ( . 

Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


TP0620 


-200 






V 


Vro = 0, In = -2.0mA 


TP0616 


-160 


VgS(Ui) 


Gate Threshold Voltage 


-1.0 




-2.4 


V 


V GS = V DS , l D = -1 0mA 


AV GS(th) 


Change in V GS(th) with Temperature 






-4.5 


mV/°C 


v gs = v ds. l D = -10mA 


'gss 


Gate Body Leakage 






-100 


nA 


V es = ±20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






-10 


uA 


Vgs = °. v ds = Max Rating 


-1.0 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


-0.25 






A 


V GS = -5V, V DS = -25V 


-0.75 






V GS = -10V, V DS = -25V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




9.0 


15 


n 


V GS = -5V, l D = -0.1A 


7.0 


12 


V— - -1 OV U - -0 2 A 


AR DS(ON) 


Change in R D s(on) w '' n Temperature 






1.7 


%/°c 


V GS = -10V, l D = -0.2A 


G FS 


Forward Transconductance 


100 


150 




mu 


V DS = -25V, l D = -0.4A 


Ciss 


Input Capacitance 




85 


150 


PF 


V GS = 0, V DS = -25V 
f = 1 MHz 


c oss 


Common Source Output Capacitance 




30 


85 


C RSS 


Reverse Transfer Capacitance 




10 


35 


*d(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = -25V 
l D = -0.75A 
R G en = 25£i 


t r 


Rise Time 






15 


'd(OFF) 


Turn-OFF Delay Time 






20 


», 


Fall Time 






16 


V SD 


Diode Forward Voltage Drop 






-1.8 


V 


V GS = 0, l SD = -0.5A 




Reverse Recovery Time 




300 




ns 


V GS = 0, l SD = -0.5A 



1. AIID.C. 

2. AIIA.C. 



parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 
parameters sample tested. 



Switching Waveforms and Test Circuit 



PULSE 
GENERATOR 



OUTPUT 



'dlOFF) _ 



90% 90%" 



10%V 




7-72 




TP06C 



Typical Performance Curves 

Output Characteristics 

























































/ _ 




































— 1 — 
















-8V 
























































; 




















-6V 















































































































-10 -20 -30 -40 -50 

V DS (volts) 
Transconductance vs. Drain Current 



{£ 100 - 
C3 



I I I 


























■ 


A = 


-55° 


C 


































■ 


"A = 


25° C 
























] 














A = 


150= 


C 


r 















































































-1.0 -2.0 

l D (amperes) 
Maximum Rated Safe Operating Area 



i 























































































TO- 


39 


PL! 


sc 


d 


— 

) 


















._4._t_l.H-- 


















-TO-220 (DC) 




























III! 




















TO-39 (DC) 






















































DC 


























>- 







































































































































-10 -100 

V DS (volts) 



Saturation Characteristics 



-8V 



p 

i5 
a. 

CO -0.4 











I I 
V GS = -10V 
























-6V 







































































































































































CO 

S 





Power 


-2 -4 

v DS ( 

Dissipation vs 


-6 -8 -1 

volts) 

. Case Temperature 


















-220 
















































































TO-3 


9 










_TO^ 











25 50 75 100 125 150 

T C (°C) 

Thermal Response Characteristics 



CD 

rr 













TO-220 > 






Pp =46W / 
Tr.=?5°r. / 
































^— TO- 


39 

= 6W 






P D 






T C = 


= 25°C 











-1000 



0.001 0.01 0.1 1 

tp (seconds) 



10 



7-73 



Typical Performance Curves 



BV DSS Variation with Temperature 




TP06C 



On-Resistanoe vs. Drain Current 






7-74 



TP06L 

Low Threshold 




P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DGS 


(max) 


'[)(ON) 

(min) 


(max) 


Order Number / Package 


TO-39 


TO-92 


SOW-20* 


DICEt 


-20V 


2.0Q 


-2.0A 


-2.4V 


TP0602N2 


TP0602N3 




TP0602ND 


-40V 


2.on 


-2.0A 


-2.4V 


TP0604N2 


TP0604N3 


TP0604WG 


TP0604ND 



* Same as SO-20 with 300 mil wide body, 
t MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

t Low threshold 2.4V max. 

High input impedance 
p Low input capacitance — 95 pF typical 
_. Fast switching speeds 

□ Low on resistance 

Free from secondary breakdown 
Low input and output leakage 
Complementary N- and P-channel devices 

Applications 

□ Logic level interface - ideal for TTL and CMOS 

□ Solid state relays 

I i Battery operated systems 

i Photo voltaic drive 
n Analog switches 

□ General purpose line driver 

□ Telecom switches 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Package Options 



TO-39 




SOW-20 



Note 1 : See Package Outline section for discrete pinouts. 
Note 2: See Array section for quad pinouts. 



7-75 



Thermal Characteristics 



TP06L 



Package 



l D (continuous)* 



l D (pulsed) 



Power Dissipation 
© T c = 25°C 



c/w 



c/w 



TO-39 



-2.0A 



-4.8A 



6W 



20 



125 



-2.0A 



-4.8A 



TO-92 



-0.75A 



-4.2A 



1W 



125 



170 



-0.75A 



SOW-20 



Refer to Arrays & Special Functi< 
— 



o ns Section 







' l D (continuous) is limited by max 



Electrical Characteristics (@ 25°C unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


TP0604 


-40 






w 

V 


VQg — U, Iq — -t.urTIM 


TP0602 


-20 


^GS(Ih) 


Gate Threshold Voltage 


-1.0 




-2.4 


V 


V GS = V DS . Id = "1 




Change in V GS(t)1 ) with Temperature 




-3.0 


-4.5 


mV/°C 


V G s = V DS . I D = -1-OrnA 


'gss 


Gate Body Leakage 






-100 


nA 


V GS = ±20V, V DS = 


!dss 


Zero Gate Voltage Drain Current 






-10 


uA 


V GS = 0, V DS = Max Rating 


-1.0 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 




ON-State Drain Current 


-0.4 


-0.6 




A 


V GS = -5V, V DS = -20V 


-2.0 


-3.3 


V GS = -10V, V DS = -20V 


RdS(ON) 


Static Drain-to-Source 
ON-State Resistance 




2.0 


3.5 


a 


V GS = -5V, l D = -250mA 


1.5 


2.0 


V GS = -10V, l D = -1.0A 


AR DS(ON) 


Change in R ds(0 n) with Temperature 




0.75 


1.2 


%/°c 


V GS = -10V, l D = -1.0A 


G FS 


Forward Transconductance 


0.4 


0.6 




u 


V DS = -20V, l D = -1.0A 


C|SS 


Input Capacitance 




95 


150 


PF 


V GS = 0, V DS = -20V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




85 


120 


C RSS 


Reverse Transfer Capacitance 




35 


60 


•dlON) 


Tum-ON Delay Time 




5.0 


8 


ns 


V DD = -20V 
l D = -1.0A 
Rgen = 25£J 


t, 


Rise Time 




7.0 


18 


'd(OFF) 


Turn-OFF Delay Time 




10 


15 


«. 


Fall Time 




6.0 


19 






V SD 


Diode Forward Voltage Drop 




-1.3 


-2.0 


V 


V GS = 0, l SD = -1.5A 


t„ 


Reverse Recovery Time 




300 




ns 


V GS = 0, l so = -1.5A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300ns pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 



PULSE 
GENERATOR 



90% 



'd(ON) 



jKl0% 10%Nt 





7-76 



Typical Performance Curves 

Output Characteristics 



<D -3 
5. 

E 
& 

Q 



-2 



























































3S=" 1 


ov~ 
















v 













































































































































-8V 
-7V 



-5V 
-4V 



-10 -20 -30 -40 -50 

V DS (volts) 
Transconductance vs. Drain Current 



V DS = -25V 








T A = -55°C 






T A = 25° C 
















-T A = 150°C - 



























-1 -2 

l D (amperes) 



Maximum Rated Safe Operating Area 



-0.01 



— H 


-Hi- 


























■v 












TO-39 (pulse 


i) 






k 






TO-39 (D 


C) 












\ 


























TO-92 (DC 


) 












1 























































































































































-0.1 



-1 -10 

V DS (volts) 



-100 



Saturation Characteristics 



Si "3 
P 



E 

« -2 

























































V 


GS=" 


10V. 


































«» 


— — 


































-— 






























4 





































-9V 
-8V 

-7V 
-6V 
-5V 
-4V 



-2 -4 -6 -8 -11 

V DS (volts) 
Power Dissipation vs. Case Temperature 



I 







































TO- 


19 


























































TO- 


92 











25 50 75 100 125 150 



Thermal Response Characteristics 



N 0.8 















































S T( 


3-39 






/ P D =6W 






Tc 


; =25°C 



















0.001 0.01 0.1 

tp (seconds) 



10 



7-77 



Typical Performance Curves 

BV DSS Variation with Temperature 




Transfer Characteristics 



o 





V DS = -25V 


















































- 6 








































Ktrf — 



































































































-2-4-6-8-11 

V GS (volts) 
Capacitance vs. Drain-to-Source Voltage 



CO 

I 

8 100 
o 





f = 1MI 


Hz 










Ciss 












c oss 









C RSS 









-10 -20 -30 

V DS (volts) 



-40 



TP06L 

On-Resistance vs. Drain Current 



o 

2 3.0 
DC 

























v 


3S = 


-5V 




v G s = 


-10V 






































































































-7 








p. 



















































» -1 * -a^- -3 •"- -4 » -4 
l D (amperes) 

V (th) and Rps Variation with Temperature 



I 

o 1.0 



> 





















































V(,h 


@ -1 


nA 




















Rds 


ON) 4 
-1.0* 


» 












-10V 



































































1.2 | 



50 100 

T) PC) 

Gate Drive Dynamic Characteristics 



"w" -6 



G 

> 

















































V 


DS = 


-10 


/ / 
























18C 


pF 


































/ v DS 


= -40V 
































































75 


pF 

















0.5 1.0 1.5 2.0 2.5 

Qq (nanocoulombs) 



7-78 



TP25A 

Low Threshold 



MM 



P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV 0SS / 
BVdss 


"DS(ON) 

(max) 


^GSfth) 

(max) 


'd(ON) 

(min) 


Order Number / Package 


TO-243AA* 


DICE* 


-60V 


3.5H 


-2.4V 


-1.5A 




TP2506ND 


-100V 


3.5H 


-2.4V 


-1.5A 


TP2510N8 


TP2510ND 



* Same as SOT-89. 

T MIL visual screening available. 

Features 

Z Low threshold 2.4V max. 

□ High input impedance 

Z Low input capacitance — 125 pF max 
P Fast switching speeds 

□ Low on resistance 

Z Free from secondary breakdown 

p Low input and output leakage 

Z Complementary N- and P-channel devices 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normal ly-off) transistors 
utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range of 
switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Applications 



Z Logic level interface - ideal for TTL and CMOS 

□ Solid state relays 

Z Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

Z General purpose line driver 

□ Telecom switches 



Absolute Maximum 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1.6 mm from case for 10 seconds. 



Package Options 




Note: See Package Outline section for discrete pinouts. 



7-79 



TP25A 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 






■dr 


'drm 








@ T A = 25°C 


cm 


c/w 






TO-243AA 


-1.0A 


-2.5A 


1.6Wt 


15 


78t 


-1.0A 


-2.5A 



* l D (continuous) is limited by max rated Tj. 

T Mounted on FR5 board, 25mm x 25mm x 1 .57mm. Significant P increase possible on ceramic substrate. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Tvd 

1 If 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


TP2510 


-100 






V 


V^c = 0. In = -2mA 


TP2506 


-60 


' 

"GS(ttl) 


riatp Thrp^hnlri Vnltanp 


-1.0 




-2.4 


V 


V,. f . = Vno I ,.= -1 mA 

GS DS' 'D 1,1 "* 


^^GS(th) 


Change in Vgg^j with Temperature 






5.0 


mV/°C 


V/^e = Vnc ln= "1 mA 

GS DS' D M,IM 


'gss 


Gate Body Leakage 






-100 


nA 


V GS = ±20V, V DS = 


'DSS 


7prn fnatp Vnltpnp Drain Onrrpnt 






-10 


uA 


V GS = 0, V DS = Max Rating 


-1 .0 


mA 


V~- = Vr>o = 08 Max Ratina 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


-0.4 


-0.6 




A 


V GS = -5V, V DS = -25V 


-1.5 


-2.5 




V GS = -10V, V DS = -25V 


Rds(on) 


Static Drain-to-Source 
ON-State Resistance 




5.0 


7.0 


Q 


V GS = -5V, l D = -250mA 


2.0 


3.5 


V GS = -10V, l D = -0.75A 


AR DS(ON) 


Change in R DS(0 n) with Temperature 






1.7 


%/°C 


V GS = -10V, l D = -0.75A 


G FS 


Forward Transconductance 


300 


360 




mu 


V DS = -25V, l D = -0.75A 


C ISS 


Input Capacitance 




80 


125 


PF 


V GS = 0, V DS = -25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




40 


70 


C HSS 


Reverse Transfer Capacitance 




10 


25 


*d(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = -25V, 
l D = -1 .OA, 
Rgen = 25£2 


tr 


Rise Time 






15 


'd(OFF) 


Turn-OFF Delay Time 






20 


t, 


Fall Time 






15 


v SD 


Diode Forward Voltage Drop 






-1.8 


V 


V GS = 0, l SD = -1.0A 




Reverse Recovery Time 




300 




ns 


V GS = 0, l SD = -1.0A 



Notes: 

1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300ps pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




TP25A 



Typical Performance Curves 

Output Characteristics 































































































V 


GS = 


-10V 






I 


< 
































-8V 




















-6V 




i 
















-4V 




C4- 














-3V 





-10 -20 -30 -40 

VQS(VOltS) 



Saturation Characteristics 



8 



§ -2 



















































































































Vg 


5 = -1 










































-8V 




















-6V 




















-4V 




















-3V 























0-2-4-6-8 -10 

V DS (volts) 



Transconductance vs. Drain Current 



Power Dissipation vs. Ambient Temperature 



w 0.2 
CD 







= -25 


V 




















T A = 


-55° 




































T 


* = 2! 


"C 




























V 

\ 






B T 




?5°C 


\ 




i 

\ 




\ 


V 










\ 

\ 




\ 






\ 

\ 












\ 

\ 




\ 

\ 
















\ 

— V 




\ 


\ 














\ 






\ 

\ 





0.5 1.0 1.5 2.0 2.5 

l D (amperes) 



a 1.0 
S 















TO-24; 


AA 











































































































25 50 75 100 125 150 
T C (°C) 



Maximum Rated Safe Operating Area 



Thermal Response Characteristics 



-0.01 







h 
























— TC 


-24 


3A 






Ised 


























































\ 

\ 


\ 








ZTC 






1 


c 










-243A 


C) 




































































































> 


< 





























































































































































-1.0 -10 

V DS (volts) 































TO-243A/ 


^ / 






P D =0.55W / 
-T c - 25°C -J- 










































0.001 



0.01 0.1 1 

tp (seconds) 



7-81 



TP25A 



Typical Performance Curves 

BV DSS Variation with Temperature 




Transfer Characteristics 



CD 

o. 
E 
a 























3 = " 


















































T A = 


-55° 




































25° 


























' 1 

> 


















15C 














f 































-2-4-6-8-1 

V GS (volts) 

) 

Capacitance vs. Drain-to-Source Voltage 



o 
a. 

o 




On-Resistance vs. Drain Current 



o 

CO 
Q 
DC 































Vg 


3 = ". 


iV 












































V( 


3S = 


-10V 































































































































-0.8 -1.6 -2.4 -3.2 -4.0 

l D (amperes) 
V (th) and R D s Variation with Temperature 



CO 

o 
> 



0.4 























Rds 


(ON) < 
mA 


S -10\ 


/, -0.7 


5A 






V(« 


„®-i 



















































































































.N 

1.2 1 
o 

0.8 g. 
CO 

o 

0.4 



100 



150 



T.PC) 



Gate Drive Dynamic Characteristics 



>° 











1 An r- 
















1 
















v D 


s = - 


1 U V 










































- v D 


s = - 


40V 
































































71 


pF 























































1.0 



Q G (nanocoulombs) 



7-82 



TP25C 

Low Threshold 



MM 
MM 



P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV DSS / 
BV DGS 


R DS(ON) 

(max) 


V GS(th) 

(max) 


"3 S 
11 


Order Number / Package 


TO-243AA* 


DICE* 


-160V 


12£2 


-2.4V 


-0.75A 




TP2516ND 


-200V 


12H 


-2.4V 


-0.75A 


TP2520N8 


TP2520ND 



* Same as SOT-89. 

t MIL visual screening available. 



Features 

□ Low threshold — 2.4V max. 

□ High input impedance 

□ Low input capacitance — 125 pF max. 

□ Fast switching speeds 

□ Low on resistance 

p Free from secondary breakdown 

□ Low input and output leakage 
Complementary N- and P-channel devices 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Applications 

□ Logic level interface - ideal for TTL and CMOS 

□ Solid state relays 

□ Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



Package Options 



BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 




7-83 



TP25C 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 






'dr* 


'drm 








@ T A = 25°C 


CAV 


°C/W 






TO-243AA 


-0.57 


-2.0 


1.6W 


15 


78t 


-0.57A 


-2.0A 



* l D (continuous) is limited by max rated fj. 

t Mounted on FR5 board, 25mm x 25mm x 1 .57mm. Significant P D increase possible on ceramic substrate. 

Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BVq55 


Drain-to-Source 


TP2520 


-200 






V 


V GS = 0. Id = "2mA 


Breakdown Voltage 


TP2516 


-160 


^GS(th) 


Gate Threshold Voltage 


-1.0 




-2.4 


V 


V GS = V DS , l D = -1mA 




Change in V GS(th| with Temperature 






4.5 


mW°C 


v gs = V DS . I D = -1mA 


Iqss 


Gate Body Leakage 






-100 


nA 


V GS = ±20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






-10 


uA 


V R q = 0, V nq = Max Rating 


-1.0 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


know 


ON-State Drain Current 


-0.25 


-0.7 




A 


V GS = -4.5V, V DS = -25V 


-0.75 


-2.1 




V GS = -10V,V DS = -25V 


^DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




10 


15 


a 


V GS = -4.5V, l D = -100mA 


8.0 


12 


V GS = -10V, l D = -200mA 


AR DS(ON) 


Change in R DS (on) witn Temperature 






1.7 


%/°c 


V GS = -10V, l D = -200mA 




Forward Transconductance 


100 


250 






V DS = -25V, l D = -200mA 


C ISS 


Input Capacitance 




75 


125 


PF 


V GS = 0, V DS = -25V 
f = 1 MHz 


C OSS 


Common Source Output Capacitance 




20 


85 


Crss 


Reverse Transfer Capacitance 




10 


35 


td(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = -25V, 
l D = -0.75A, 
Rgeim = 25£5 


t, 


Rise Time 






15 


l d(OFF) 


Turn-OFF Delay Time 






20 


t. 


Fall Time 






15 


V SD 


Diode Forward Voltage Drop 






-1.8 


V 


v gs = 0. !sd = -°' 5A 


trr 


Reverse Recovery Time 




300 




ns 


V GS = 0, l SD = -0.5A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300ns pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




7-84 



TP25C 



Typical Performance Curves 

Output Characteristics 



$ -1.5 























































-8V 




























































-6V 


























































-4V 




















-3V 













































-10 -20 -30 -40 -50 

V DS (volts) 



Saturation Characteristics 



$ -1.2 







































































V 


GS = 


-10 
























-OV 




















-6V 


























































-4V 


















-3V 





-2 -4 -6 -e' 
V DS (volts) 



Transconductance vs. Drain Current 



Power Dissipation vs. Ambient Temperature 



1.0 



<o 0.4 























V 


DS - 


-25 






























































T A 


= -5£ 


>°C 




































T. = 25°C 


* x 


\ 








/ '<■» 




T A = 


= 12 


5°C 


> 




\ > 




















^ > 

























-0.4 -0.8 -1.2 -1.6 -2.0 

l D (amperes) 







































TO-2' 


t3A/N 



















































































25 50 75 100 125 150 

T C (°C) 



Maximum Rated Safe Operating Area 



Thermal Response Characteristics 



Cl 

E 
a 























H-+- 






















■a 


= z 


































TO 


-24 


Si 


A 




pul. 


;ed 


) 
























— V 


























































\ 
































i 
































V 




































TO- 


24 


3A 


<\ 


( 


DC) 









































































-10 -100 

Vos (volts) 



-1000 



CD 

rr 
« 
e 



.H 0.8 



0.6 




0.001 





























TO 


= 243AA 






P D = 0.55W 
t. - 9s°r. 






■ u 







































0.01 0.1 1 

tp (seconds) 



7-85 



Typical Performance Curves 

BV DSS Variation with Temperature 




Transfer Characteristics 



Cl 

E 
9 













/ * 

/ I / 


v DS = -: 


>5V 












i ^ 
/ 

/ 












T A = 


= -55 


°Ci 


/ 4 

-25° 
£4 


> 


t 














/ y 


C ^ 
/ 
















' t 
/ 


/ 

/ 
















// 

ft 


/ 

/ 


125 
















V 


















//* 


/ 


















ft 

































-2 -4 -6 -8 -11 

V GS (volts) 
Capacitance vs. Drain-to-Source Voltage 



o 





f = 1MHz 




















C| SS 














Cqss 



-10 -20 -30 -40 

V DS (volts) 



On-Resistance vs. Drain Current 



E 30 



o 

m 20 
D? 





















I 


























V 


GS - 


-4.5 


V 






































































































iov- 


/ 













































) -0.5 -1.0 -1.5 -2.0 -2.5 

l D (amperes) 
V (th) and R DS Variation with Temperature 



| 

C 

£ 

^ 0.9 





































R 


DS(ON 


@ -■ 


ov, - 


0.2A 






















@ -1 














TlA 







































































-50 



50 
T; (°C) 



100 150 



Gate Drive Dynamic Characteristics 



;> -4 



































0V- 




























































= -4C 


)V 


































20( 


)pF 




























73r 


)F 


















I 

















0.5 1.0 1.5 2.0 

Q G (nanocoulombs) 



7-86 



(ff) Supertexinc. 



TP25D 

Low Threshold 




P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV DGS 


R DS(ON) 

(max) 


V GS(th) 

(max) 


=» o 


Order Number / Package 


TO-92 


TO-243AA* 


DICE* 


-350V 


25£J 


-2.4V 


-0.4A 


TP2535N3 




TP2535ND 


-400V 


25ii 


-2.4V 


-0.4A 


TP2540N3 


TP2540N8 


TP2540ND 



Same as SOT-89. 
1 MIL visual screening available. 



Features 

□ Low threshold — 2.4V max. 

□ High input impedance 

□ Low input capacitance — 125 pF max. 

□ Fast switching speeds 

□ Low on resistance 

Free from secondary breakdown 

□ Low input and output leakage 

□ Complementary N- and P-channel devices 



Applications 



□ Logic level interface - ideal for TTL and CMOS 

□ Solid state relays 
Battery operated systems 

L I Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 

Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


+ 20V 


Operating and Storage Temperature 


-55°CtO+150°C 


Soldering Temperature* 


300°C 


* Distance of 1.6 mm from case for 10 seconds. 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) transis- 
tors utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Package Options 




TO-243AA 
(SOT-89) 



Note: See Package Outline section for discrete pinouts. 



7-87 



TP25D 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 
@ T c = 25°C 







1 * 


I 


TO-92 


-0.3A 


-0.6A 


1W 


125 


170 


-0.3A 


-0.6A 


TO-243AA 


-0.4A 


-1.2A 




15 


78* 


-0.4A 


-1.2A 



* l D (continuous) is limited by max rated T.. 

f Mounted on FR5 Board, 25mm x 25mm x 1 .57mm. Signficant P Q increase possible on ceramic substrate. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


TP2540 


-400 






w 
V 


V GS= °> >D = -2mA 


TP2535 


-350 


V GS(th) 


Gate Threshold Voltage 


-1.0 




-2.4 


V 


v gs = V DS' l D = -1mA 


AV GS (th) 


Change in V GS(th) with Temperature 






4.8 


mV/°C 


v gs = v ds. I D = -1mA 


'gss 


Gate Body Leakage 






-100 


nA 


V GS = ±20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






-10 


HA 


V GS = 0, V DS = Max Rating 




mA 


v gs = 0. v ds = 8 Max Rating 
T A = 125°C 


t(ON) 


ON-State Drain Current 


-0.2 


-0.3 




A 


V GS = -4.5V, V DS = -25V 


-0.4 


-1.1 




V GS = -10V, V DS = -25V 


RdS(ON) 


Static Drain-to-Source 
ON-State Resistance 




20 


30 


& 


V GS = -4.5V, l D = -100mA 


19 


25 


V GS = -10V, l D = -100mA 


AR DS(ON) 


Change in R ds(0 n) with Temperature 






0.75 


%/°C 


V GS = -10V, l D = -100mA 




Forward Transconductance 


100 


175 




mU 


V DS = -25V, l D = -100mA 


Ciss 


Input Capacitance 




60 


125 


PF 


V GS = 0, V DS = -25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




20 


70 


CrsS 


Reverse Transfer Capacitance 




10 


25 


'd(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = -25V 
l D = -100mA 
R GEN = 25£2 


tr 


Rise Time 






10 


l d(OFF) 


Turn-OFF Delay Time 






20 


», 


Fall Time 






13 


V S D 


Diode Forward Voltage Drop 






-1.8 


V 


V GS = 0, l SD = -100mA 


trr 


Reverse Recovery Time 




300 




ns 


v gs = °. l S D = - 1 00 mA 



Notes: 

1. All D C. parameters 100% tested at 25"C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




7-88 



TP25D 



Typical Performance Curves 

Output Characteristics 



Q. 

E 
to 

























































5 = " 




















10V 




















-8V 








































-6V 








































-4V 

























-10 -20 -30 -40 -50 

V DS (volts) 
Transconductance vs. Drain Current 

























V 


DS = 


-25 


/ 




















































































r Ta 


= -DO 

=±= 


















25°C 
i 


















12 


5°C 













































-0.4 -0.8 -1.2 -1.6 -2.0 

l D (amperes) 



CD 

a> 
a. 
E 
as, 

a 















\ 




U 


-H- 


















I 
























S 


•T 


cj 




TUIS 


ea 




T 
T 


0-2 


43; 


A 
( 


It 
. 


ulse 


i) 






> 


■\ — 










A =25 

r -r - 










\ 






















V- 










S 




















\ 






























-92 
DC 




> 






























> 


i 






























\ 

\ 








































TO-243AA (DC) > 












\ 








T A = 25°C 





















































































Saturation Characteristics 



£ 
o 

5. 
E 

CO -0.4 





































Vgs 


















— 


= -10V 




















8V 
6V! 























































































































I 

CO 
E 
o 



CD 



E 
o 
t— 



0-2-4-6-8-10 

V DS (volts) 
Power Dissipation vs. Case Temperature 



TO-243AA 










< 'a = 


25°CJ) 











































































































25 50 75 100 125 150 

T C (°C) 

Thermal Response Characteristics 





































I U-<i4JMM 
Pn = 0.55W 






n 


C = 25°C 





































-10 -100 -1000 

V DS (volts) 



0.001 0.01 0.1 1 

tp (seconds) 



TP25D 



Typical Performance Curves 

BV DSS Variation with Temperature 




Transfer Characteristics 




Capacitance vs. Drain-to-Source Voltage 



2 

IB 

8 
o 





f = 1MHz 




















C ISS 














c oss 



-10 -20 -30 

V DS (volts) 



-40 



On-Resistance vs. Drain Current 



J 60 

o 



□ 

























v G . 




t.5V 




























































) 










































s = 


-10V 





























































D -0.4 -0.8 -1.2 -1.6 -2.0 

Id (amperes) 
V (th ) and R DS Variation with Temperature 



v 0.9 





























@ -10 


V, -0. 


A — 










S(ON) 










































































- v (th 


@ "1 


mA 



































I 

o 



50 100 150 

TjfC) 

Gate Drive Dynamic Characteristics 



§ 





























V[ 


)S = 


- 10' 


























































'ds 


= -A 


ov 




























f IS 


10 pF 
































60| 


)F 





































0.4 0.8 1.2 1.6 2.0 

Q G (nanocoulombs) 



7-90 



TP25L 



Low Threshold 



m 



P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Preliminary 



Ordering Information 



BV DSS / 


R DS(ON) 




'd(ON) 


Order Number / Package 


BVdgs 


(max) 


(max) 


(min) 


TO-243AA* 


DICE* 


-20V 


2.on 


-2.4V 


-2.0A 


TP2502N8 


TP2502ND 



* Same as SOT-89. 

t MIL visual screening available. 



Features 

□ Low threshold — -2.4V max. 

□ High input impedance 

□ Low input capacitance — 1 25 pF max. 

□ Fast switching speeds 

□ Low on resistance 

□ Free from secondary breakdown 

□ Low input and output leakage 

d Complementary N- and P-channel devices 

Applications 

□ Logic level interface - ideal for TTL and CMOS 

□ Solid state relays 

□ Battery operated systems 

□ Photo voltaic drive 

□ Analog switches 

□ General purpose line driver 

□ Telecom switches 

Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance ot 1 .6 mm from case for 1 seconds. 



Low Threshold DMOS Technology 

These low threshold enhancement-mode (normally-off) power 
transistors utilize a vertical DMOS structure and Supertex's well- 
proven silicon-gate manufacturing process. This combination 
produces devices with the power handling capabilities of bipolar 
transistors and with the high input impedance and positive tem- 
perature coefficient inherent in MOS devices. Characteristic of all 
MOS structures, these devices are free from thermal runaway and 
thermally induced secondary breakdown. 

Supertex Vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where very low threshold 
voltage, high breakdown voltage, high input impedance, low input 
capacitance, and fast switching speeds are desired. 



Package Options 











TO-243AA 




(SOT-89) 




Note: See Package Outline section for discr< 


ite pinouts. 



7-91 



TP25L 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 






■dr 


•drm 








@ T A = 25°C 


c/w 


°c/w 






TO-243AA 


-1.2A 


-3.3A 


1.6W* 


15 


78* 


-1.2A 


-3.3A 



* l D (continuous) is limited by max rated T } . 

t Mounted on FR5 board. 25mm x 25mm x 1 .57mm. Significant P D increase possible on ceramic substrate. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Tvd 


Max 


Unit 


Conditions 


B^DSS 


Drain-to-Source 
Breakdown Voltage 


-20 






V 


V^-o = In = -2mA 

GS ' D t " lrl 


V GS(th) 


Gate Threshold Voltage 


-1.0 




-2.4 


V 


v gs = v ds. i D =-1mA 


AV GS(th) 


Change in V GS(th) with Temperature 




3.0 


4.5 


mV/°C 


V GS = V DS' 'd= - 1mA 


'gss 


Gate Body Leakage 






-100 


nA 


V es = ± 20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






-10 


uA 


V GS = 0, V DS = Max Rating 


-1.0 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


-0.4 


-0.7 




A 


V GS = -5V, V DS = -15V 


-2.0 


-3.3 




V GS = -10V, V DS = -15V 


RdS(ON) 


Static Drain-to-Source 
ON-State Resistance 




2.0 


3.5 


n 


V GS = -5V, l D = -250mA 


1.5 


2.0 


V GS = -10V, l D = -1A 


AR DS(ON) 


Change in R DS(0 n) with Temperature 




0.75 


1.2 


%/°c 


V GS = -10V, l D = -1A 


Gfs 


Forward Transconductance 


0.3 


0.65 




u 


V DS = -15V, l D = -1A 


C| SS 


Input Capacitance 






125 


PF 


V GS = 0, V DS = -20V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 






70 


Crss 


Reverse Transfer Capacitance 






25 


td(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = -20V, 
l D = -1.0A, 
R GEN = 25fl 


t r 


Rise Time 






11 


l d(OFF) 


Turn-OFF Delay Time 






15 


& 


Fall Time 






12 


V SD 


Diode Forward Voltage Drop 




-1.3 


-2.0 


V 


V GS = 0, l SD = -1.5A 


trr 


Reverse Recovery Time 




300 




ns 


V GS = 0, l SD = -1.5A 



Notes: 

1 . All D C parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




Alphanumeric index and Ordering Information 


mm 


Corporate Profile 


wm 


Applications Notes 


mm 


Quality Assurance and Handling Procedures 


mm 


Process Flow 


mm 


Selector Guides and Cross Reference 




N- and P-Channel Low Threshold MOSFETs 


M 


DMOS N-Channel Discretes 




DMOS P-Channel Discretes 


wm 


DMOS Arrays and Special Functions 




High Voltage Driver/Interface ICs 




High Voltage Analog Switches and Multiplexers 


. > m 


High Voltage Power Supply ICs 


mm 


CMOS Consumer/Industrial Products 




Surface Mount Packages and Lead Bend Options 




Package Outlines 


nm 


Die Specifications 


wm 


Representatives/Distributors 





Chapter 8 - DMOS N-Channel Discretes 

2N6659 35V, 1.8 ohms 8-1 

2N6660/2N6661 60V, 3 ohms; 90V, 4 ohms 8-3 

2N7000 60V, 5 ohms 8-5 

2N7007 240V, 45 ohms 8-9 

2N7008 60V, 7.5 ohms 8-11 

DN25D 350, 400V, 25 ohms 8-13 

LND1E 500V, 1 Kohm 8-15 

VN01A 40, 60, 90V; 3 ohms 8-19 

VN01 C 1 60, 200V; 1 ohms 8-23 

VN03D 350, 400V; 2.5 ohms 8-27 

VN03E 450, 500V; 4 ohms 8-31 

VN03F 550, 600V; 6 ohms 8-35 

VN0300 30V, 1 .2 ohms 8-39 

VN05D 350, 400V; 35 ohms 8-41 

VN05E 450, 500V; 60 ohms 8-45 

VN06D 350, 400V; 1 ohms 8-49 

VN06E 450, 500V; 1 6 ohms 8-53 

VN06F 550, 600V; 20 ohms 8-57 

VN0606/VN061 60V; 3, 5 ohms 8-61 

VN0808 80V, 4 ohms 8-63 

VN10K 60V, 5 ohms 8-65 

VN 1 1 A 60, 1 00V; 0.7 ohms 8-69 

VN12A 40, 60, 100V; 0.3 ohms 8-73 

VN1206A/N1210 120V; 6, 10 ohms 8-77 

VN13A 40, 60, 1 00V; 8 ohms 8-79 

VN1706A/N1710 170V; 6, 10 ohms 8-83 

VN201 0L 200V, 1 ohms 8-85 

VN21 A 60, 1 00V; 4 ohms 8-87 

VN22A 60, 1 00V; 0.35 ohms 8-91 

VN22C 200, 240V, 1 .25 ohms 8-95 

VN2222 60V, 7.5 ohms 8-99 

VN2406A/N241 240V; 6, 1 ohms 8-1 01 

VN351 5L/VN401 2L 350, 400V; 1 5, 1 2 ohms 8-1 03 



2N6659 



N-Channel Enhancement-Mode 
Vertical DMOS FET 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


Rds<on) 
(max) 


il 


Order Number / Package 


TO-39 


35V 


1.8£2 


1.5A 


2N6659 



High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 



Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C, ss and fast switching speeds 

□ Excellent thermal stability 
T< Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

L I Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1.6 mm from case for 10 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




8-1 



2N6659 



* l D (continuous) is limited by max rated Tj. 

■ 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source Breakdown Voltage 


35 






V 


l D =10|iA, V GS = 


^GSfth) 


Gate Threshold Voltage 


0.8 




2.0 


V 


V GS = v ds. I D = 1m A 


'gss 


Gate Body Leakage 






100 


nA 


V QS = ±15V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = Max Rating 


500 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


1.5 






A 


V GS = 10V, V DS = 10V 


^DS(ON) 


Static Drain-to-Source ON-State Resistance 






5 


a 


V GS = 5V, l D = 0.3A 






1.8 


V GS = 10V, l D = 1A 


G FS 


Forward Transconductance 


170 






mO 


V DS = 10V, l D = 0.5A 


Ciss 


Input Capacitance 






50 


PF 


V GS = 0, V DS = 24V 
f= 1 MHz 


c oss 


Common Source Output Capacitance 






40 


Crss 


Reverse Transfer Capacitance 






10 


'(ON) 


Turn-ON Time 






10 


ns 


V DD = 25V, l D = 1A 
Rgen = 25£2 


'(OFF) 


Turn-OFF Time 






10 


V SD 


Diode Forward Voltage Drop 




1.2 


1.8 


V 


l SD = 1 .4A, V GS = 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




2N6660 
2N6661 



MM 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


R DS(ON) 

(max) 


II 


Order Number / Package 


TO-39 


60V 


3.0£i 


1.5A 


2N6660 


90V 


4.0O 


1.5A 


2N6661 



High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C, ss and fast switching speeds 

□ Excellent thermal stability 
p Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


Distance of 1 .6 mm from case for 10 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




8-3 



2N6660/2N6661 



Thermal Characteristics 



Package 


l (continuous)* 


l D (pulsed) 


Power Dissipation 


9c 


% 


■dr 


'drh 








@ T c = 25°C 


°C/W 


°c/w 






2N6660 


1.1A 


3A 


6.25W 


20 


125 


1.1A 


3.0A 


2N6661 


0.9A 


3A 


6.25W 


20 


125 


0.9A 


3.0A 



* l D (continuous) is limited by max rated Tj, 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


2N6660 


60 






V 


V =01= 10uA 

GS * D 


2N6661 


90 


^GS(th) 


Gate Threshold Voltage 


0.8 




2.0 


V 


v os = v os. l D =1mA 




Change in V GS(th) with Temperature 




-3.8 


-5.5 


mV/°C 


V GS = V DS , l D =1mA 


!qss 


Gate Body Leakage 






100 


nA 


V GS = ±20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = Max Rating 


500 


V GS = 0, V DS = 0.8 Max Rating, 
T A = 125°C 


'D(ON) 


ON-State Drain Current 


1 .5 








V GS - ,u > V DS - luv 


^DS(ON) 


Static Drain-to-Source 
ON-State Resistance 


All 






5.0 


a 


V GS = 5V, l D = 0.3A 


2N6660 






3.0 


V GS = 10V, l = 1A 


2N6661 






4.0 


V GS = 10V, l D = 1A 


G FS 


Forward Transconductance 


170 






ml! 


V DS =25V, l D = 0.5A 




Input Capacitance 






50 


PF 


V GS = 0, V DS = 24V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 






40 


Crss 


Reverse Transfer Capacitance 






10 


'(ON) 


Turn-ON Time 






10 


ns 


V DD = 25V, 

l D = 1A, R eEN = 25£i 


'(OFF) 


Turn-OFFTime 






10 


V SD 


Diode Forward Voltage Drop 




1.2 




V 


V GS = 0, l SD = 1A 


'rr 


Reverse Recovery Time 




350 




ns 


V GS = 0, l SD = 1A 



Notes: 



1 : All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 
2: All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




8-4 



2N7000 



N-Channel Enhancement-Mode 
Vertical DMOS FET 



Ordering Information 



BV DSS / 


"dS(ON) 

(max) 


'd(ON) 

(min) 


Order Number / Package 


TO-92 


60V 


5£l 


75mA 


2N7000 



Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C| SS and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a ver- 
tical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 



Absolute Maximum Ratings 



Drain-to-Source Voltage 


BV DSS 


Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±40V 


Operating and Storage Temperature 


-55°C to+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Package Options 




8-5 



i 500mA i 



l„ (continuous) is limited by max rated TV 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 

1 HI U 1 1 1 L. Id 


Min 


Tvn 


Max 


Unit 


Conditions 


BV neo 

DV DSS 


Drain-to-Source Breakdown Voltage 


60 






V 


L = 10uA V^-o = 

iq — i unn t V GS v 


^GS(th) 


Gate Threshold Voltage 


0.8 




3.0 


V 


V^c - Vnr lr^ = 1 mA 

V GS V DS' D IMn 


'gss 


Gate Body Leakage 






10 


nA 


V^<- = +15V Vr,c - 
GS 1 DS 


'dss 


Zero Gate Voltage Drain Current 






1 


uA 


V GS = 0, V DS = 48V 


1 


mA 


V GS = 0, V DS = 48V 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


75 






mA 


V GS = 4.5V, V DS = 10V 


R DS(ON) 


Static Drain-to-Source ON-State Resistance 






5.3 


a 


V GS = 4.5V, l D = 75mA 


R DS(ON) 


Static Drain-to-Source ON-State Resistance 






5 


a 


V GS = 10V, l D = 0.5A 


G FS 


Forward Transconductance 


100 






mU 


V DS = 10V, l D = 0.2A 


C|SS 


Input Capacitance 






60 


PF 


V GS = 0V, V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 






25 


Crss 


Reverse Transfer Capacitance 






5 


'(ON) 


Turn-ON Time 






10 


ns 


V DD = 15V, l D = 0.5A, 
R GEN = 25£2 


'(OFF) 


Turn-OFF Time 






10 


V SD j Diode Forward Voltage Drop 




0.85 V l SD = 0.2A, V GS = 



Notes: 

1. AII D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 



10V 



INPUT 



10%-, 


/ ' 


C 90% 




"(ON) 




. '(OFF! 




<<i(ON) t, 


V>FF) 


If 






^90° 


10%-\ 
90% > 


r 7 


■10% 



PULSE 
GENERATOR 





D.U.T. 



i 1 



8-6 



2N7000 



Typical Performance Curves 

Output Characteristics 



CD 
Q. 

E 













— \ 


'gs- 


10V 

















































































































































































10 20 30 40 50 

V DS (volts) 



Saturation Characteristics 



? 15 

9 
a. 

1 1.0 



2 



4 6 

V DS (volts) 

















J 






















=10V 




















8V! 


























































6V 
















































































4V . 







































Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



£ 
5 

3- 

S2 o.4 

CD 























1 


^DS 


= 25 


















































































<-" 



























" Ia 


— 25°C 
























i 






































> 





















0.2 0.4 0.6 0.8 1.0 

l D (amperes) 



1 

□ 1.0 
Q_ 























































































TO-92 





































25 50 75 100 125 150 

T C (°C) 



Maximum Rated Safe Operating Area 



Thermal Response Characteristics 



0.001 





















-TO-92 (pulse 
I I I 














s 




J) 
















TO 


92 


DC 


) 



























































































































































































1.0 10 

V DS (volts) 































































<r TO 


-92 






PD 


= 0.4W 
= 25°C 






Tc 



0.001 0.01 0.1 1 

t p (seconds) 



8-7 



Typical Performance Curves 



2N7000 




2N7007 



N-Channel Enhancement-Mode 
Vertical DMOS FET 



Ordering Information 



BV DSS / 
BV DGS 


R DS(ON) 

(max) 


'd<on) 
(min) 


Order Number / Package 


TO-92 


240V 


45n 


150mA 


2N7007 



Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C, ss and fast switching speeds 

□ Excellent thermal stability 
P Integral Source-Drain diode 

C High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±40V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertax's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 



TO-92 



Note 1 : See Package Outline section for discrete pinouts. 



8-9 



2N7007 



Thermal Characteristics 



Package 


l D (continuous)' 


l D (pulsed) 


Power Dissipation 












@ T c = 25°C 


cm 


cm 


TO-92 


65mA 


260mA 


400mW 


312.5 


40 



l D (continuous) is limited by max rated Tj. 



Electrical Characteristics (@ 25°c unless otherwise specified) 





P a ra motor 


Min 


Typ 


Max 


Unit 


f*nnriitinn« 


BV DSS 


Drain-to-Source Breakdown Voltage 


240 






V 


i i r»r>. • a \/ n 
! D = 100uA, V GS = 


V GS(th) 


oaic i [ircbiiuiu voiictyt; 






2 5 


V 


Vqs = V DS , l D = 250uA 


'gss 


Gate Body Leakage 






10 


nA 


V GS = ±20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






100 


. 


V GS = 0. V DS = 1 20V 


4 

1 


UA 


V GS = 0, V DS = 120V 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


50 






mA 


V GS = 4.5V, V DS = 20V 


150 






V GS = 10V, V DS = 20V 


^dsion) 


Static Drain-to-Source ON-State Resistance 






45 


Q 


V GS = 4.5V, l D = 20mA 






45 


V GS = 10V, l D = 50mA 


Gfs 


Forward Transconductance 


30 






mU 


V DS = 10V, l D = 50mA 




Input Capacitance 






30 


PF 


V GS = 0, V DS = 25V 
f = 1 MHz 


c oss 


Common Source Output Capacitance 






15 


Crss 


Reverse Transfer Capacitance 






10 


'(ON) 


Turn-ON Time 






30 


ns 


V DD = 60V, l D = 50 mA, 
R GEN = 25fi 


'(OFF) 


Turn-OFF Time 






20 


v SD 


Diode Forward Voltage Drop 






1.2 


V 


l SD = 65mA, V GS = 



Notes: 

1 . Alt D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300u.s pulse, 2% duty cycle.) 

2. AH A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 



V, 




ait 



2N7008 



1 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV DSS / 
BV DGS 


"dS(ON) 

(max) 


11 


Order Number / Package 


TO-92 


60V 


7.5£2 


500mA 


2N7008 



Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C| SS and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

Z Complementary N- and P-channel devices 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±40V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 



of 1.6 mm from c 



s for 10 



Package Options 



TO-92 



Note 1 : See Package Outline section for discrete pinouts. 



8-11 



2N7008 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 












@ T c = 25°C 


=c/w 


cm 


TO-92 


150mA 


1A 


400mW 


312.5 


40 



* l D (continuous) is limited by max rated Tj. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Ciimhnl 




Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source Breakdown Voltage 


60 






V 


l D = -10uA, V GS = 


V GS(th) 


Gate Threshold Voltage 


1 




2.5 


V 


v gs = v ds. 'd = 250uA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±30V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






1 


HA 


V GS = 0. V DS = 50V 


500 


■ i A 

UA 


V GS = °< V DS 50V 

T A = 125°C 


'd(ON) 


ON-State Drain Current 


500 






mA 


V GS = 10V, V DS >2V DS(0N) 


^DS(ON) 


Static Drain-to-Source ON-State Resistance 






7.5 


n 


V G s = 5V . Id = 50mA 


7.5 


V GS = 10V, l D = 500mA 


G FS 


Forward Transconductance 


80 






mtJ 


V DS = 10V, l D = 0.2A 


G ISS 


Input Capacitance 






50 


pF 


V qs = 0V . V ds = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 






25 


Crss 


Reverse Transfer Capacitance 






5 


t(ON) 


Turn-ON Time 






20 


ns 


Vqq = 30V, l D =200 mA, 
R GEN = 25£2 


'(OFF) 


Turn-OFF Time 






20 


V SD 


Diode Forward Voltage Drop 






1.5 


V 


l SD = 150mA, V GS = 



Notes: 

1 . All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300ms pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




8-12 



DN25D 

Low Threshold 



m 



Preliminary 



N-Channel Depletion-Mode 
Vertical DMOS FETs 



Ordering Information 



BV DSX / 
BV DGX 


"ds<on) 
(max) 


'dss 
(min) 


Order Number / Package 


TO-39 


TO-92 


TO-220 


TO-243AA* 


DIE 


350V 


25£2 


150mA 


DN2535N2 


DN2535N3 


DN2535N5 




DN2535ND 


400V 


25Q 


150mA 


DN2540N2 


DN2540N3 


DN2540N5 


DN2540N8 


DN2540ND 



' Same as SOT-89. 



Features 

□ High input impedance 

□ Low input capacitance 

□ Fast switching speeds 

□ Low on resistance 

□ Free from secondary breakdown 

□ Low input and output leakage 



Applications 

□ Normally-on switches 

□ Solid state relays 

□ Converters 

□ Linear amplifiers 

□ Constant current sources 

□ Power supply circuits 

□ Telecom 



Absolute Maximum Ratings 



Drain-to-Source Voltage 


BV DSX 


Drain-to-Gate Voltage 


BV DGX 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Advanced DMOS Technology 

These low threshold depletion-mode (normally-on) transistors 
utilize an advanced vertical DMOS structure and Supertex's well- 
proven silicon-gate manufacturing process. This combination pro- 
duces devices with the power handling capabilities of bipolar 
transistors and with the high input impedance and positive tem- 
perature coefficient inherent in MOS devices. Characteristic of all 
MOS structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 



TO-39 



TO-92 




TO-243AA 
(SOT-89) 



TO-220 



Note 1: See Package Outline section for discrete pinouts. 



8-13 



DN25D 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 

@ T c = 25°C 


9c 

c/w 


C/W 


■dr 


'drm 


TO-39 


300mA 


500mA 


3.5W 


35 


125 


300mA 


500mA 


TO-92 


120mA 


500mA 


LOW 


125 


120 


170mA 


500mA 


TO-220 


500mA 


500mA 


15.0W 


8.3 


70 


500mA 


500mA 


TO-243AA 


300mA 


500mA 




15 


78+ 


300mA 


500mA 



* l D (continuous) is limited by max rated T ( . 

T Mounted on FR5 board, 25mm x 25mm x 1 .57mm. Significant P increase possible on ceramic substrate. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSX 


Drain-to-Source 
Breakdown Voltage 


DN2540 


400 






V 


V GS = -3.5V, l D = 100uA 


DN2535 


350 


VgS(OFF) 


Gate-to-Source OFF Voltage 


-1.0 




-5.0 


V 


V DS = 25V, l D = 10uA 


A ^GS(OFF) 


Change in V GS(0FF) with Temperature 






4.5 


mV/°C 


V DS = 25V, l D =10uA 


'gss 


Gate Body Leakage Current 






100 


nA 


V GS = ±20V, V DS = 


'd(OFF) 


Drain-to-Source Leakage Current 

■ 






10 


uA 


V GS = -10V, V DS = Max Rating 






1 


mA 


V GS = -10V, V DS = 0.8 Max Rating 

I A — I £D \j 


'DSS 


Saturated Drain-to-Source Current 


150 






mA 


V^o - OV V™ - 25V 


RdS(ON) 


Static Drain-to-Source 
ON-State Resistance 




17 


25 


n 


V GS = 0V, l D = 120mA 


AR DS(ON) 


Change in R ds(0 n) with Temperature 






1.1 


%/°C 


V GS = 0V, l D = 120mA 


G FS 


Forward Transconductance 




325 




m!5 


l D = 100mA, V DS = 10V 


Ciss 


Input Capacitance 




200 


300 


PF 


V GS = -10V, V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




12 


30 


Crss 


Reverse Transfer Capacitance 




1 


5 


•d(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = 25V, 
l D = 150mA, 
^GEN ' 25Q 


t, 


Rise Time 






15 


'd(OFF) 




Turn-OFF Delay Time 






15 


If 


Fall Time 






20 


V SD 


Diode Forward Voltage Drop 






1.8 


V 


V GS = -10V, l SD = 120mA 


trr 


Reverse Recovery Time 




800 




ns 


V GS = -10V, l SD = 1A 



Notes: 

1 . All D.C. parameters 100% tested at 2S°C unless otherwise staled. (Pulse test: 3O0jis pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




(fi) Super tex inc. 



LND1E 



/JPJn N-Channel Depletion-Mode 
v9-V MOSFET 



Ordering Information 



BV DSX / 


"DS(ON) 


'd(0N) 


Order Number / Package 


BV DGX 


(max) 


(mln) 


TO-92 


TO-243AA* 


Die 


500V 


1.0K£i 


1.0mA 


LND150N3 


LND150N8 


LND150ND 



' Same as SOT-89 



Features 

□ ESD gate protection 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Excellent thermal stability 

□ Integral source-drain diode 

High input impedance and low C| SS 



Advanced DMOS Technology 

The LND1 is a high voltage N-channel depletion mode (normally- 

on) transistor utilizing Supertax's lateral DMOS technology. The K* 

gate is ESD protected. 

The LND1 is ideal for high voltage applications in the areas of 
normally-on switches, precision constant current sources, voltage 
ramp generation and amplification. 



Applications 

□ Solid state relays 

□ Normally-on switches 

□ Converters 

fl Power supply circuits 

□ Constant current sources 

□ Input protection circuits 



Package Options 



Absolute Maximum Ratings 



Drain-to-Source Voltage 


BV DSX 


Drain-to-Gate Voltage 


BV DGX 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 10 seconds. 



TO-243AA 
(SOT-89) 



TO-92 



Note 1: See Package Outline section for discrete pinouts. 



8-15 



LND1E 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 

@T C = 25°C 


% 
"CM 


6 ,. 
°C/W 




'drm 


TO-92 


30mA 


30mA 


LOW 


125 


170 


30mA 


30mA 


TO-243AA 


30mA 


30mA 




31 


105t 


30mA 


30mA 



* l D (continuous) is limited by max rated T r 

t Mounted on FR5 Board, 25mm x 25mm x 1 .57mm. Significant P D increase possible on ceramic substrate. 



Electrical Characteristics <@ 25°C unless otherwise specified) 



Symbol 


Parameter 


Min 


Tvd 


Max 


Unit 


Conditions 




Drain-to-Source Breakdown Voltage 


500 






V 


V GS = -10V, l D = 1.0mA 


V G o/f>FR 


Gate-to-Source OFF Voltage 


-1.0 




-3.0 


V 


V DS = 25V, l D = 100nA 




Change in V GS(OFF) with Temperature 






5.0 


mV/°C 


V DS = 25V, l D = 100nA 


^GSS 


Gate Body Leakage Current 






100 


nA 


V GS = ±20V, V DS = 




Drain-to-Source Leakage Current 






100 


nA 


V GS = -10V, V DS = 450V 






100 


uA 


V GS = -10V, V DS = 0.8V max rating 
T A =125°C 


'dss 


Saturated Drain-to-Source Current 


1.0 




3.0 


mA 


V GS = 0, V DS = 25V 


^DS(ON) 


Static Drain-to-Source ON-State Resistance 




850 


1K 


Ll 


V GS = 0, l D = 0.5mA 


Ar ^DS(ON) 


Change in RDS(ON) with Temperature 






1.2 


%/°C 


V GS = 0, l D = 0.5mA 




Forward Transconductance 


1.0 


2.0 




mU 


V GS = 0, l D = 1.0mA 


C|SS 


Input Capacitance 




7.5 


10.0 


PF 


V GS = -10V, V DS = 25V 
f = 1 MHz 


Coss 


Output Capacitance 




2.0 


3.5 


Crss 


Reverse Transfer Capacitance 




0.5 


1.0 


'd(ON) 


Turn-ON Delay Time 




0.09 




us 


V DD = 25V, l D = 1.0mA, 
Rgen = 25il 


tr 


Rise Time 




0.45 




'd(OFF) 


Turn-OFF Delay Time 




0.1 




tf 


Fall Time 




1.3 






Diode Forward Voltage Drop 






0.9 


V 


V GS = -10V, l SD = 1.0mA 


trr 


Reverse Recovery Time 




200 




ns 


V GS = -10V, l SD = 1.0mA 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. AII A.C. parameters sample tested. 




8-16 



LND1E 



Typical Performance Curves 

Output Characteristics 























■ 










\ 


'gs = 


1.0> 


/ 




























































n fiv 


















OV 


























































0.5V 
















-1.0V 



250 

V DS (volts) 



E 

1 3 



Saturation Characteristics 













i 


'gs 


- 1 ( 

- 1 ,1 


IV, 


















































n sv 


















ov 




















































0.5V 














-1.0V 



2 3 

V DS (volts) 



Transconductance vs. Drain Current 



Power Dissipation vs. Ambient Temperature 



* 



I I I 

V„„ = 400V 






























= -5 


5°C 
















T A 




































_ T. 


= SI 


















■ A ■ w 
















T A = 125°C 































































2 4 6 8 10 

l D (milliamps) 
Maximum Rated Safe Operating Area 
















to-; 


>43AA 








































































TO-92 



































25 50 75 100 125 150 

T A (°C) 

Thermal Response Characteristics 



^ o.e 

1 
o 



i 























































TO-92 








T c = 25°C 



















0.001 0.01 0.1 1.0 10 

tp (seconds) 



8-17 



Typical Performance Curves 




8-18 



VN01A 



N-Channel Enhancement-Mode 
Vertical DMOS FET 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


"ds<on) 
(max) 


Ji 


Order Number / Package 


TO-39 


TO-52 


TO-92 


TO-220 


Quad P-DIP 


Quad C-DIP* 


DICE+ 


40V 


3£2 


2.0A 


VN0104N2 


VN0104N9 


VN0104N3 


VN0104N5 


VN0104N6 


VN0104N7 


VN0104ND 


60V 


3£2 


2.0A 


VN0106N2 


VN0106N9 


VN0106N3 


VN0106N5 


VN0106N6 


VN0106N7 


VN0106ND 


90V 


3U 


2. OA 


VN0109N2 


VN0109N9 


VN0109N3 


VN0109N5 






VN0109ND 



* 14 pin side brazed ceramic DIP 
t MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 
y Low power drive requirement 

□ Ease of paralleling 

□ Low C, ss and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°CtO+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 





TO-39 



TO-52 




TO-92 




TO-220 



14-LeadDIP 



Note 1 : See package outline section for discrete pinout. 
Note 2: See array section for quad pinout. 



8-19 



VN01A 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 

@ T c = 25°C 


°c/w 


C/W 


'dr* 


'drm 


TO-39 


0.8A 


2.5A 


3.5W 


125 


35 


0.8A 


2.5A 


TO-52 


0.5A 


2.0A 


LOW 


170 


125 


0.5A 


2.0A 


TO-92 


0.5A 


2.0A 


LOW 


170 


125 


0.5A 


2.0A 


TO-220 


1.5A 


2.5A 


15.0W 


70 


8 


1.5A 


2.5A 


Plastic DIP 
Ceramic DIP 


See DMOS Arrays & Special Functions section 



' l D (continuous) is limited by max rated T. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VN0109 


90 






V 


V GS = 0, l D =1mA 


VN0106 


60 


VN0104 


40 


V GS(th) 


Gate Threshold Voltage 


0.8 




2.4 


V 


v gs = v ds. I D = 1mA 


AV GS(th) 


Change in V GS(th) with Temperature 




■■3.8 


-5.5 


mV/'C 


v gs = v ds. I D = 1mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ± 20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






1 


UA 


V GS = 0, V DS = Max Rating 


100 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


1 

'D(ON) 




ON-State Drain Current 


U.O 


I .U 




A 


V GS = 6V ' V DS = " V 


2.0 


2.5 




V GS = 10V, V DS = 25V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




3.0 


5 


n 


V G s = 5V . Id = 250mA 


2.5 


3 


V GS = 10V, l D = 1A 


AR DS(ON) 


Change in R ds(0 n) with Temperature 




0.70 


1 


%/°c 


V GS = 10V, l D = 1A 


Gfs 


Forward Transconductance 


300 


450 




mU 


V DS = 25V, l D = 0.5A 


Ciss 


Input Capacitance 




45 


65 


pF 


V GS = 0. V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




20 


25 


Crss 


Reverse Transfer Capacitance 




5 


8 


'd(ON) 


Turn-ON Delay Time 




3 


5 


ns 


V DD = 25V 
l D = 1A 
R GEN = 25Q 


tr 


Rise Time 




5 


8 


'd(OFF) 


Turn-OFF Delay Time 




6 


9 


t, 


Fall Time 




5 


8 


V SD 


Diode Forward Voltage Drop 




1.2 


1.8 


V 


v GS = o, l SD =10A 


trr 


Reverse Recovery Time 




400 




ns 


V GS = 0, l SD =1.0A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




VN01A 

Typical Performance Curves 





8-21 



VN01A 



Typical Performance Curves 

BV DSS Variation with Temperature 




100 150 



Transfer Characteristics 



£ 1.5 

I 

D. 

E 
«J 



I I I 
V DS = 25V 










1 / 
/ 










r A = 


-55° 






f 1 


f J 










c— 




/ A 
1/ 


2E 


■c 














/ i 




























































■ — 1 


25° C 



































































2 4 6 8 1C 

V GS (volts) 
Capacitance vs. Drain-to-Source Voltage 







f = 


1MHz 
























Coss 








Crss 



10 20 30 

V DS (volts) 



On-Resistance vs. Drain Current 



4.0 



J. 3.0 
o 



o 

S 20 
en 

















/ 










iS = 


5V 








r 

1 — 


















7 




















/ 




= 10 














y 















































































































D 0.5 1.0 1.5 2.0 2.5 

l D (amperes) 
V (lh) and R DS Variation with Temperature 



1.6 
1.4 

I 

~m 12 
o 

CO 

>° 

0.8 











































S@ 1 


0V, 1 


OA > 
























h) @ 


1mA 




3S@ 


5V, 0. 


1A — 













































































1.3 ra 
o 



-50 50 100 150 

Tj(°C) 

Gate Drive Dynamic Characteristics 



2 6 































V 


DS 


= 10V 
























40\ 


1 






















































B0p 




































































/ 40 pF 

r i i 

















0.2 0.4 0.6 0.8 1.0 

Q G (nanocoulombs) 



8-22 



VN01C 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


"ds<on) 
(max) 


"3 S 


Order Number / Package 


TO-39 


TO-92 


TO-220 


Dice* 


160V 


10iJ 


0.4A 


VN0116N2 


VN0116N3 


VN0116N5 


VN0116ND 


200V 


ion 


0.4A 


VN0120N2 


VN0120N3 


VN0120N5 


VN0120ND 



T MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C| SS and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV D gs 


Gate-to-Source Voltage 


+ 20V 


Operating and Storage Temperature 


-55°CtO+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertax's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




1:9 



8-23 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 






■ * 
'dr 


'drm 








@ T c = 25°C 


°c/w 


°c/w 






TO-39 


350mA 


1.0A 


3.5W 


125 


35 


350mA 


1.0A 


TO-92 


250mA 


0.9A 


LOW 


170 


125 


250mA 


0.9A 


TO-220 


700mA 


1.2A 


15.0W 


70 


8.3 


700mA 


1.2A 



* l D (continuous) is limited by max rated Tj. 

Electrical Characteristics (@ 25 c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


b Vdss 


Drain-to-Source 
Breakdown Voltage 


VN0120 


200 






y 


V GS ~ U ' 'd ~ 


VN0116 


160 


^GS(th) 


Gate Threshold Voltage 


1 




3 


V 


v gs = V DS , l D = 1mA 


AV G S(th) 


Change in V GS(th ) with Temperature 




-5.1 


-6.0 


mV/°C 


V GS =V DS , l D = 1mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = Max Rating 






1 


mA 


v gs = °. v ds = 8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


0.3 


0.6 




A 


V GS = 5V, V DS = 25V 


0.4 


0.9 




V GS =10V, V DS = 25V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




10 


15 


a 


V GS = 5V, l D = 100mA 




8 


10 


V GS = 10V, l D = 100mA 


AR DS(th) 


Change in R DS( th) with Temperature 




1.0 


1.2 


%/°c 


V GS = 10V, l D = 500mA 


G FS 


Forward Transconductance 


100 


200 






V DS = 25V, l D = 250mA 


Ciss 


Input Capacitance 




40 


55 


pF 


V GS = 0, V DS = 25V 
f = 1 MHz 


C-oss 


Common Source Output Capacitance 




20 


30 


Crss 


Reverse Transfer Capacitance 




5 


8 


'd(ON) 


Turn-ON Delay Time 




3 


5 


ns 


V DD = 25V, 
l D = 1A, 

R GEN = 25£1 


t, 


Rise Time 




5 


8 


td(OFF) 


Turn-OFF Delay Time 




6 


9 


tf 


Fall Time 




5 


8 


V SD 


Diode Forward Voltage Drop 




1.2 


1.8 


V 


V GS = 0, l SD = 1-0A 




Reverse Recovery Time 




400 




ns 


V GS = 0, l SD =1.0A 



Notes: 

1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse. 2% duty cycle.) 

2. All A.C. parameters sample tested. 




8-24 



Typical Performance Curves 

Output Characteristics 



8 12 



2. 
E 
a 




10 20 30 40 50 

V DS (voits) 
Transconductance vs. Drain Current 



£ 0.4 
O 







= 25 


V 








i 

= -55°C 


















25° C 










9 


























-15 


0°C 














































t 















































































0.2 0.4 0.6 0.8 1.0 

l D (amperes) 
Maximum Rated Safe Operating Area 



0.01 



0.001 



i~ r t r 








ir^ i i - 


TO 


22C 


(D 


C) 








T 


0-39 (pul 








































\ 








































































\ 







































































































































10 100 

V DS (volts) 



1000 



VN01C 



Saturation Characteristics 



1.0 



8 
■ 

CL 

<0 0.4 






























































V GS 


=10V 

8V ' 
6V ' 







































































































































V DS (volts) 
Power Dissipation vs. Case Temperature 



1 

Q 10 
0- 







































TO-22( 
















































TO-39 


















\ 








TO-92 













25 60 75 100 125 150 

T C (°C) 

Thermal Response Characteristics 



rr o.6 
■ 

o 
c 



15 

1 
I 



0.2 



_ TO-220 
P D =15 








W ^ 






~ T C = 25° 


C 










d 






















/ TC 


)-39 






/ P D =3.5W 






T C 


= 25°C 













0.001 



0.01 0.1 

tp (seconds) 



8-25 



Typical Performance Curves 



VN01C 




8-26 



VN03D 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BVoss/ 
BVdgs 


^DS<ON) 

(max) 


ll 


Order Number / Package 


TO-3 


TO-39 


TO-220 


Dice* 


350V 


2.5Q 


3A 


VN0335N1 


VN0335N2 


VN0335N5 


VN0335ND 


400V 


2.5U 


3A 


VN0340N1 


VN0340N2 


VN0340N5 


VN0340ND 



' MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 



Features 

□ Free from secondary breakdown 

□ Low power drive requirement 
Ease of paralleling 

□ Low C| SS and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 
t ] Amplifiers 

C I Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 10 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



IB 



Package Options 





TO-220 




TO-3 



Note: See package outline section for discrete pinout. 



8-27 



VN03D 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 

@ T c = 25°C 


°c/w 


3c 

C/W 


■dr 


'dRM 


TO-3 


3.5A 


8A 


100W 


30 


1.25 


3.5A 


8.0A 


TO-39 


1.0A 


7A 


6W 


125 


20.8 


1.0A 


7.0A 


TO-220 


2.1A 


8A 


50W 


40 


2.5 


2.1A 


8.0A 



* l D (continuous) is limited by max rated T,. 



Electrical Characteristics (@ 25 c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VN0340 


400 






V 


V GS = 0, l D =10mA 


VN0335 


350 


^GS(th) 


Gate Threshold Voltage 


2 




4 


V 


V GS =V DS ,l D = 10mA 


AV GS(tti) 


Change in V GS(th) with Temperature 




-4.8 


-6.0 


mV/°C 


V G s = v DS.lD = 1 r TiA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






100 


uA 


Vgs = °' ^os = Max Rating 






2.0 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 1 25°C 


— : 

'd(ON) 


ON-State Drain Current 




5.0 




A 


V™ - 5V V™ - 25V 
V GS Qv i V DS £3V 


3.0 


6.0 




V rs = 10V, V n » = 25V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 








a 


V GS = 5V, l D = 0.5A 




1.8 


2.5 


V GS =10V, l D =1A 


ARDS(th) 


Change in R DS(ttl ) with Temperature 




1 


2 


%/°c 


V GS = 10V, l D = 1A 


G FS 


Forward Transconductance 


1 


1.25 




u 


V DS = 25V, l D = 1A 


C|SS 


Input Capacitance 




550 


650 


PF 


V GS = 0, V 0S = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




75 


125 


^RSS 


Reverse Transfer Capacitance 




25 


50 


'd(ON) 


Turn-ON Delay Time 




12 


20 


ns 


V DD = 25V, 
l D =1A, 
R GEN = 10Q 


tr 


Rise Time 




12 


20 


l d(OFF) 


Turn-OFF Delay Time 




65 


100 


tf 


Fall Time 




20 


30 


v SD 


Diode Forward Voltage Drop 




1.1 


1.5 


V 


V GS = 0, l SD =1A 


trr 


Reverse Recovery Time 




450 




ns 


V GS = 0, l SD = 1A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300u.s pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




8-28 



Typical Performance Curves 



Output Characteristics 



Saturation Characteristics 



Q. 

E 

<0 





















































v G 


S = 10V 

























































































































































































10 20 30 40 50 

V DS (volts) 



3.0 

p 





















































V G 


S = 


ov 
















■ 


— - 










J 






■5V 










j 
















■4V 









































































































2 4 6 

V DS (volts) 



Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



CD 




2 3 4 

l D (amperes) 



a 40 
Q- 



TO-3 
















































TO-2! 

















































TO-3S 

























25 50 75 100 125 150 

T C (°C) 



Maximum Rated Safe Operating Area 



Thermal Response Characteristics 



a. 
E 

(0 




0.01 



10 100 

V DS (volts) 




0.01 

'p (seconds) 



Typical Performance Curves 

BV DSS Variation with Temperature 




Transfer Characteristics 



2 1.5 
CD 



0.5 







; =25V 






h 










-v D 


















T A =-5 


5°C 


, 






























































/ n 


!5°C 























































































2 4 6 

V GS (volts) 



10 



Capacitance vs. Drain-to-Source Voltage 



1 
a. 

O 



I f = 1 


<AHz 












Ciss 










t 














C ss 



10 20 

V DS (volts) 



30 40 



VN03D 

On-Resistance vs. Drain Current 



E 12 



o 

CO 

o 
CC 































s = 


>V - 




































































































































i 


v G s 


= 1i 


V 































































2 4 6 8 1( 

l D (amperes) 
V(th) and R D s Variation with Temperature 



? 12 

N 

n 

2 1.0 



C3 

> 













































§ 10V 


, 1A 






v (th) 


@ 10r 


IlA 











































































































o 
to 

0.5 ,£ 



50 

TjPC) 



100 150 



Gate Drive Dynamic Characteristics 





























v D s 


= 10 


/ y 






















160 


OpF 






















































^DS 


= 40 


V 
















































00 


F 
















M I 

















8 12 16 20 

Q G (nanocoulombs) 



8-30 



VN03E 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


(max) 


'd(ON) 

(min) 


Order Number / Package 


TO-3 


TO-39 


TO-220 


Dice 1 


450V 


4Q 


2A 


VN0345N1 


VN0345N2 


VN0345N5 


VN0345ND 


500V 


4£2 


2A 


VN0350N1 


VN0350N2 


VN0350N5 


VN0350ND 



' MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

Free from secondary breakdown 

□ Low power drive requirement 
Ease of paralleling 

□ Low C, ss and fast switching speeds 

□ Excellent thermal stability 

J Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 
Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV DSS 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1.6 mm from case for 10 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



IB 



Package Options 




8-31 



Thermal Characteristics 



Package 


l D (continuous)* 


I D (pulsed) 


Power Dissipation 
© T c = 25X 


% 

°c/w 


c/w 


'dr 


'drm 


TO-3 


2.5A 


5.0A 


100W 


30 


1.25 


2.5A 


5.0A 


TO-39 


0.35A 


4.5A 


6W 


125 


20.8 


0.35A 


4.5A 


TO-220 


1.5A 


5. OA 


50W 


40 


2.5 


1.5A 


5.0A 


* l D (continuous) is limil 


ed by max rated Tj. 















Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VN0350 


500 






V 


V GS = 0, l D =10mA 


VN0345 


450 


V GS(th) 


Gate Threshold Voltage 


2 




4 


V 


V gs = v ds. I D = 10mA 




Change in V GS(th) with Temperature 




-7.0 


-9.0 


mV/°C 


v gs = v os. !o = 1 0mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






100 


uA 


V GS = 0, V DS = Max Rating 






2.0 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 1 25°C 


'd(ON) 


ON-State Drain Current 




2.6 




A 


V GS = 5V, V DS = 25V 


c.. U 


D.O 




Vqs- 1UV > V DS - " V 


^DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




3.5 




a. 


V GS = 5V, l D = 0.5A 




2.8 


4.0 


V GS = 10V, l D = 0.5A 


A ^DS(th) 


Change in R DS ( t h) with Temperature 




1 


1.5 


%/°c 


V GS = 10V, l D = 0.5A 


Gfs 


Forward Transconductance 


500 


1000 




mU 


V os = 25V, l D = 0.5A 


Ciss 


Input Capacitance 




550 


650 


PF 


V GS = 0,V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




90 


125 


Crss 


Reverse Transfer Capacitance 




15 


50 


'd(ON) 


Turn-ON Delay Time 




8 


15 


ns 


V DD = 25V, 
l D = 1A, 
R GEN = 10£i 


t, 


Rise Time 




8 


15 


'd(OFF) 


Turn-OFF Delay Time 




65 


100 


t, 


Fall Time 




15 


25 


V SD 


Diode Forward Voltage Drop 




1.3 


1.8 


V 


V GS = 0, l SD = 1.0A 


t„ 


Reverse Recovery Time 




450 




ns 


V GS = 0, l SD = 0.5A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300ms pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




8-32 



Typical Performance Curves 

Output Characteristics 



































s = 


ov 


















„ 




■ 






























i 














I 




t 


































1 






















2k 
































V 







10 20 30 40 50 

V DS (volts) 
Transconductance vs. Drain Current 



I I 






— • 


" A =-55°C — 




S = 




















' — 


1 1 
T A = 25°C 


























m 














T 


\ = 

















































































































12 3 4 

l D (amperes) 
Maximum Rated Safe Operating Area 





I III 








































--l-tt 
























_TO-3 (DC) 




































s 




\i 










TO 


22f 


(0 





































































































-TO 


39 


DC 












) 

























































































































































10 100 

V DS (volts) 



1000 



VN03E 



Saturation Characteristics 



E 
I 























































-V G 


s = 


ov 


















•8V 




































'5V - 




























































































3V 





2 4 6 8 10 

V DS (volts) 
Power Dissipation vs. Case Temperature 



1 

Q 40 
Q- 



TO-3 
















































TO-2J 





























































i u-jy 











25 50 75 100 125 150 

T C (°C) 

Thermal Response Characteristics 




0.001 0.01 



0.1 

tp (seconds) 



8-33 



Typical Performance Curves 

BV DSS Variation with Temperature 




100 150 



Transfer Characteristics 



2! 

£ 1.5 

01 

1 

_Q 1.0 

























t>V 












/ 










T 


I 

A = -55°C 




















/ 25 


°C 


7 




































.12 


5°C 





















































































2 4 6 8 10 

V GS (volts) 
Capacitance vs. Drain-to-Source Voltage 



3 
o 



^^f = 1 


i/IHz 












C ISS 






















"RSS 


Coss 











10 20 30 40 

V DS (volts) 



VN03E 

On-Resistance vs. Drain Current 



CO 4 































5 =5 


V 






















































































-v 


3S = 


10V 















































































2 4 6 

l D (amperes) 



V( t h) and R DS Variation with Temperature 



ra i.o 
o 

£ 0.8 

I 

0.6 





I I I I i 

RPSION)® 10V, 0.5A /. 








I I 

































Rds 


(ONI)"* 


$ 10V 


1A 



































































































1.0 ^ 

o 

o 
to 

0.5 



50 100 

Tj(°C) 

Gate Drive Dynamic Characteristics 



C5 

> 









v DS 


= 10V 








































'v,^ = 


40V 


































600 


pF 






































































00 p 


F 
















f 



















0.5 1.0 1.5 2.0 

Q G (nanocoulombs) 



8-34 



VN03F 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


R DS(ON) 

(max) 


l[)(ON) 

(min) 


Order Number / Package 


BV DGS 


TO-3 


TO-220 


Dice* 


550V 


6n 


1.5A 


VN0355N1 


VN0355N5 


VN0355ND 


600V 


6H 


1.5A 


VN0360N1 


VN0360N5 


VN0360ND 



t MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process Flows 
and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C, ss and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 



Applications 



□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 




TO-3 



TO-220 



Note: See package outline section for discrete pinout. 



8-35 



VN03F 



Thermal Characteris 



ICS 



Package 


I D (continuous)* 


l D (pulsed) 


Power Dissipation 

@ T c = 25°C 


°C/W 


°c/w 


■dr 


'drm 


TO-3 


2.5A 


6A 


100W 


2.5 


1.25 


2.5A 


6.0A 


TO-220 


1.5A 


6A 


50W 


30 


2.5 


1.5A 


6.0A 



' l D (continuous) is limited by max rated T|. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VN0360 


600 






V 


V GS = 0, l =10mA 


VN0355 


550 


V G S(th) 


Gate Threshold Voltage 


2 




4 


V 


V G s = V DS . l D = 10mA 


AV G S(th) 


Change in V GS(th) with Temperature 




-4.8 


-6.0 


mV/°C 


V G s = V DS . l D = 10mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = +20V, V DS = 


loss 


Zero Gate Voltage Drain Current 






100 


HA 


V GS = 0, V DS = Max Rating 






2.0 


mA 


V GS = 0, V cs = 0.8 Max Rating 
T A = 125°C 


1 

'D(ON) 


ON-State Drain Current 




I 




A 


\/ _ C\/ W _ OCX/ 








V GS _ luv - V DS ~ d0W 


■■DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




4.5 




a 


V^.-- 5V U - 5A 




4.0 


6.0 


V GS = 10V, l D = 0.5A 


AR DS(th) 


Change in R DS ( t h) witn Temperature 




1 


2 


%/°c 


V GS = 10V, l D = 0.5A 


Gfs 


Forward Transconductance 


0.5 


0.6 




u 


V DS = 25V, l D = 0.5A 


Ciss 


Input Capacitance 




550 


650 


pF 


V GS = 0, V DS = 25V 
f=1 MHz 


C ss 


Common Source Output Capacitance 




75 


125 


Crss 


Reverse Transfer Capacitance 




25 


50 


'd(ON) 


Turn-ON Delay Time 




8 


15 


ns 


V DD = 25V, 
l D = 0.5A, 

R GEN = ion 


t, 


Rise Time 




8 


15 


'd(OFF) 


Turn-OFF Delay Time 




65 


100 




Fall Time 




12 


25 


v SD 


Diode Forward Voltage Drop 




1.1 


1.5 


V 


V GS = 0, l SD = 0.5A 


trr 


Reverse Recovery Time 




450 




ns 


V GS = 0, l SD = 0.5A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300ms pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 

10V . 

INPUT / 

ov io%y 



90% 



*d(OFF) l F 



0V 





D.U.T. 



8-36 



VN03F 



Typical Performance Curves 

Output Characteristics 



































v G s = iov 





































































































































































6V 



10 20 30 40 50 

V DS (volts) 
Transconductance vs. Drain Current 



ffi 0.4 
C5 





I I 


















S =' 




















L 




























T A = -55°C 














I I I 
T A =25°C 




i 














J-. 














T 


A = 


50° 

































































0.5 1.0 1.5 2.0 2.5 

l D (amperes) 
Maximum Rated Safe Operating Area 



10 































































T 


0-2 


20 


P 


J 


sed) 












\ 























> 






TO-3 (DC) 

— MM 








I 






s 


s 












— TO-220 (DC 






i 








































































\ 



























































































































































































































10 100 

V DS (volts) 



Saturation Characteristics 



9> 



§ 0.4 













I I \ J 
Vr« = iov LM. 










































8V 




















DV 
















\ 




4V 




























































3V 











































D 1.0 2.0 3.0 4.0 5.0 

V DS (volts) 
Power Dissipation vs. Case Temperature 



§ 
5. 

D 40 
0- 



TO-3 
















































TO-2S 










































































25 50 75 100 125 150 

T C (°C) 

Thermal Response Characteristics 



.— 0.8 



0C 

o 
I— 





















































yTn.? 








r p d =ioow 






T c = 


25° C 













0.001 0.01 0.1 1.0 

tp (seconds) 



8-37 




8-38 



VN0300 



1 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


^DSION) 

(max) 


If 


Order Number / Package 


BV TCS 


TO-39 


TO-92 


30V 


1.20 


1.0A 


VN0300B 


VN0300L 



High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process Flows 
and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C| SS and fast switching speeds 

□ Excellent thermal stability 
LJ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 
Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 



Drain-to-Source Voltage 


BV DSS 


Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


+ 30V 


Operating and Storage Temperature 


-55°CtO+150°C 


Soldering Temperature* 


300°C 


• Distance of 1 .6 mm from case for 1 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




8-39 



VN0300 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 
@ T c = 25°C 


ia 
C/W 


% 

c/w 


TO-39 


1.51 A 


3A 


5W 


170 


20 


TO-92 


0.64A 


3A 


2W 


156 


40 



' l D (continuous) is limited by max rated Tj. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



oymDOl 


Parameter 


nil in 

Mm 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source Breakdown Voltage 


30 






V 


V GS = 0, l D =10uA 


V GS(th) 


Gate Threshold Voltage 


0.8 




2.5 


V 


V GS = v ds> l D = 1mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±30V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = Max Rating 


500 


Vqs = 0. v ds = 30V 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


1 






A 


V GS = 0.1V. V DS >2V DS(ON) 


RdS(ON) 


Static Drain-to-Source ON-State Resostance 






3.3 





V GS = 5V, l D = 0.3A 










1.2 


V GS = 10V, l D = 1A 


G FS 


Forward Transconductance 


200 






mU 


V DS = 10V, l D = 0.5A 




Input Capacitance 






190 


pF 


V GS = 0V, V DS = 20V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 






110 


Crss 


Reverse Transfer Capacitance 






50 


'(ON) 


Turn-ON Time 






30 


ns 


V DD = 25V, l D = 1.0A 

R GEN = 25£i 


'(OFF) 


Turn-OFF Time 






30 


V SD 


Diode Forward Voltage Drop 




0.9 




V 


l SD = 0.63A, V GS = 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 








VN05D 

Supertevc inc. 



■ 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BVdcs 


(max) 


If 


Order Number / Package 


TO-39 


TO-92 


Dicet 


350V 


35fi 


250mA 


VN0535N2 


VN0535N3 


VN0535ND 


400V 


35£1 


250mA 


VN0540N2 


VN0540N3 


VN0540ND 



T MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C| SS and fast switching speeds 

□ Excellent thermal stability 
T! Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 



Absolute Maximum Ratings 




Drain-to-Source Voltage 




BV DSS 


Drain-to-Gate Voltage 




BV DGS 


Gate-to-Source Voltage 




±20V 


Operating and Storage Temperature 


-55°C t 


D+150°C 


Soldering Temperature* 




300°C 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 



TO-39 



TO-92 



Note: See package outline section for discrete pinout. 



• Distance of 1 .6 mm from case for 1 seconds. 



8-41 



VN05D 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 






■dr 


'drm 








@ T c = 25°C 


C/VJ 


°c/w 






TO-39 


250mA 


500mA 


6.0W 


125 


20.8 


250mA 


500mA 


TO-92 


100mA 


400mA 


LOW 


170 


125 


100mA 


400mA 



* l D (continuous) is limited by max rated Tj, 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VN0540 


400 






v 


V„„ - D L - 1mA 

V GS — u > 'D — 


VN0535 


350 


V GS(th) 


Gate Threshold Voltage 


2 




4 


V 


v gs = v ds . Id = 1 mA 


AV G S(th) 


Change in V GS(th) with Temperature 




-3.5 


-4.5 


mV/°C 


V G s = V D s. I D = 1mA 


'gss 


Gate Body Leakage 






100 


nA 


V es = ±20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 







10 


uA 


V G s = °. v ds = Max Rating 






500 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 




300 




mA 


V GS = 5V, V DS = 25V 


250 


340 




V GS =10V, V DS = 25V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




30 




n 


V GS = 5V, l D = 20mA 




25 


35 


V GS = 10V, l D = 0.1A 


AR DS(th) 


Change in R DS(th) with Temperature 




0.9 


1.5 


%/°c 


V GS = 10V, l D = 0.1A 


G FS 


Forward Transconductance 


100 


180 




mu 


V DS = 25V, l D = 0.1 A 


C ISS 


Input Capacitance 




45 


55 


PF 


' 

V GS = 0, V DS = 25V 
f = 1 MHz 


C OSS 


Common Source Output Capacitance 




8 


10 


CrsS 


Reverse Transfer Capacitance 




2 


5 


'd(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = 25V, l D = 250mA 
R GEN = 25£2 


«, 


Rise Time 






10 


'd(OFF) 


Turn-OFF Delay Time 






10 


tf 


Fall Time 






10 


V SD 


Diode Forward Voltage Drop 




0.8 




V 


V GS = 0, l SD = 0.5A 


trr 


Reverse Recovery Time 




400 




ns 


V GS = 0, l SD = 0.5A 



Notes: 

1 . All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300ns pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




R-4P 



VN05D 



Typical Performance Curves 

Output Characteristics 



































s = 


ov 
















































































4V 




























































3V 



























10 20 30 40 50 

V DS (volts) 



Saturation Characteristics 



p 



I 0.10 



































5=1 


















OV " 




5V 
4V 


































































































3V. 









































4 6 

V DS (volts) 



8 10 



Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



<£ 0.16 







I 


















S =' 
















































T 


A = ' 


55°( 






































r A = 


25° ( 










f 










< 










T, 




25° C 













































0.4 0.8 1.2 1.6 2.0 

l D (amperes) 



I 

.f 4 






































TO-3! 




























































TO-92 













25 50 75 100 125 150 
T C (°C) 



Maximum Rated Safe Operating Area 



Thermal Response Characteristics 



Q- 

E 

CO 



I [ III I 


— r 


- 






TO-39 (Dulsed) _ 































■ 


- 




















TO-39 (C 

I I I 


c 


) 


\ 


\ 
















" TO-92 (DC 


























> 



































































































































































































































































10 100 

V DS (volts) 



! 





I 

I TO-39 






P D =6.0W 






1 


"C = 25°C 








































T( 


)-92 






< Pi 


! =1.0W _ 
= 25°C — 






Tc 



0.001 0.01 0.1 1 

t p (seconds) 



8-43 



VN05D 



Typical Performance Curves 

BV DSS Variation with Temperature 




100 150 



T, (°C) 



Transfer Characteristics 




Capacitance vs. Drain-to-Source Voltage 



I 



f = 1 


l\ Hz 












Ciss 












— Crss — 




c oss 



10 20 30 

V DS (volts) 



40 



On-Resistance vs. Drain Current 



E 
o 



o 

2 40 

rr 















1 
















= 5V 
















\ 














































3=1 


OV 









































































































0.1 0.2 0.3 0.4 0.5 

l D (amperes) 
V (th) and R D s Variation with Temperature 



o 1.0 



:? o.6 























D - 


fft 


10V, 


0.1A 






\ 


'(th) @ 


I 






1mA 













































































































1.4 "g 



O 

0.6 ,£> 



-50 



100 150 



Tj(°C) 



Gate Drive Dynamic Characteristics 















I I 
































- 10£ 


pF- 




40* 


/ 
















r i 

12 pF 




















































































50 


nF 


















I 

















0.2 0.4 0.6 0.8 1.0 

Q G (nanocoulombs) 



8-44 



VN05E 



km 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 

BV DGS 


"ds<on) 
(max) 


If 


Order Number / Package 


TO-39 


TO-92 


Dice* 


450V 


6on 


150mA 


VN0545N2 


VN0545N3 


VN0545ND 


500V 


60£2 


150mA 


VN0550N2 


VN0550N3 


VN0550ND 



T MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C| SS and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 



Drain-to-Gate Voltage 


BVdgs 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 



* Distance of 1.6 mm from case for 10 seconds. 




8-45 



TO-39 


100mA 


300mA 


6.0W 


125 


20 


100mA 


300mA 


TO-92 


50mA 


250mA 


LOW 


170 


125 


50mA 


250mA 



* l D (continuous) is limited by max rated Tj. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VN0550 


500 






V 


V =0V, I = 1mA 

G5 D 


VN0545 


450 


V GS(th) 


Gate Threshold Voltage 


2 




4 


V 


V GS = V DS , l D = 1 mA 


AV GS(tri) 


Change in V GS(th) with Temperature 




-3.8 


-5.0 


mV/°C 


V GS = V DS , l D = 1 mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±20V, V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0V, V DS = Max Rating 






1000 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 1 25°C 


'D(ON) 


ON-State Drain Current 




-\ f\r\ 
l UU 




mA 


V GS = 5V, V DS = 25V 




350 




V GS= lOV, V DS = d5V 


^DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




45 




Q 


V GS = 5V, l D = 50mA 




40 


60 


V GS = 10V, l D = 50mA 


AR DS(th) 


Change in R D s(tn) with Temperature 




1 


1 .7 


%/°C 


V GS = 10V, l D = 50mA 


G FS 


Forward Transconductance 


50 


100 






V DS = 25V, l D = 50mA 


C|SS 


Input Capacitance 




45 


55 




V GS = 0, V DS = 25V 
f = 1 MHz 


°oss 


Common Source Output Capacitance 




8 


1 U 


Crss 


Reverse Transfer Capacitance 




2 


5 


l d(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = 25V, 
l D = 150mA, 
R GEN = 25£2 


tr 


Rise Time 






15 


'd(OFF) 


Turn-OFF Delay Time 






10 


t, 


Fall Time 






10 


V SD 


Diode Forward Voltage Drop 




0.8 




V 


V GS = 0V, l SD = 0.5A 


trr 


Reverse Recovery Time 




300 




ns 


V GS = 0V, l SD = 0.5A 



Notes: 

1 . Al! D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




8-46 



Typical Performance Curves 



VN05E 



Output Characteristics 



Saturation Characteristics 



I 
E 

CO 











1 1 1 

Vrs=10V_ 


8V 




































■6V- 













































































































































10 20 30 40 50 

V DS (volts) 
Transconductance vs. Drain Current 



0.40 



E 

5. 

£ 0.16 
O 





I I 


















S ' 
















































i 


A = 


-55° 


C 










. — 
























T 


A = 


25° C 
















2 




_L 


















25° C 




i 









































0.1 0.2 0.3 0.4 0.5 

l D (amperes) 



V 015 
9 



a 0.10 























































3 = 10V 































































































































































8V 
6V 



2 4 6 8 10 

V DS (volts) 
Power Dissipation vs. Case Temperature 



i 



4 







































TO-3S 




























































TO-9J 

— 








: 





25 50 75 100 125 150 

T C (°C) 



Maximum Rated Safe Operating Area 



Thermal Response Characteristics 



I 

CO 



0.001 





























jr 


-3a 


fn 


ulsad 




















li- 


















TO-3S 


lt 


)C) 
























































\ 










TC 


-9: 


(t 


)C) 


































\ 







































































































10 100 

V DS (volts) 



1000 



1 



£ 0.8 
CO 





1 

TO-39 






P D = 6W 






1 


C = 25°C 
































/ T 


D-92 _ 






/ P 


D = 1W 






' T 


« =25°C 











0.001 0.01 0.1 1 

tp (seconds) 



8-47 



Typical Performance Curves 

BV DSS Variation with Temperature 



2 1.0 




100 150 



Tj (=C) 
Transfer Characteristics 



Q- 

E 

CO 







I I 


1! 


/ 

t 










V DS = 25V 

I I 
















T A =-55°C 






25° 


C 














ii 
1.'* 




















Ii' 


50° 


















> 


















h 









































































2 4 6 8 1( 

V GS (volts) 
Capacitance vs. Drain-to-Source Voltage 



o 



f = 1 








i — 






















Coss 


V 






Crss 



10 20 30 

V DS (volts) 



VN05E 

On-Resistance vs. Drain Current 



4 60 

o 

I 40 

























Vgs 


= 5V 
















































SS 5 


10V 
















V 





































































































3 0.1 0.2 0.3 0.4 0.5 

l D (amperes) 
V( t h) and Ftps Variation with Temperature 



i 



CO 

4? 0.8 























3S(ON 


} @ 1C 


V, 50 


TlA 


























@ 1 n 


lA 









































































































o 

<z> 

0.6 £ 



50 

TjCC) 



100 150 



Gate Drive Dynamic Characteristics 



£ 6 

o 



CO 













I I I 

Vr,c = 10V 
















5 pF 


















1( 




























































r v'ds = 


40V 












11 


2pF 
































5 


OpF 

































0.2 0.4 0.6 0.8 1.0 

Q G (nanocoulombs) 



8-48 







VN06D 



N-Channei Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


"dS(ON) 

(max) 


'd(ON) 

(min) 


Order Number / Package 


TO-39 


TO-92 


TO-220 


Dice* 


350V 


10£2 


0.75A 


VN0635N2 


VN0635N3 


VN0635N5 


VN0635ND 


400V 


1012 


0.75A 


VN0640N2 


VN0640N3 


VN0640N5 


VN0640ND 



t MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C, ss and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




TO-92 




TO-220 



Note: See package outline section for discrete pinout. 



8-49 



TO-39 


0.6A 


Z.Z»\ 


ov» 


14*? 


t- 1 






TO-92 


0.25A 


1.5A 


1W 


170 


125 


0.25A 


1.5A 


TO-220 


1.6A 


2.5A 


45W 


70 


2.7 


1.6A 


2.5A 



* l D (continuous) is limited by max rated Tj. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 


VN0635 


350 






V 


V GS = 0V, l D = 2mA 




Breakdown Voltage 


VN0640 


400 






V Q s ( th) 


Gate Threshold Voltage 


2 




4 


V 


V GS = V DS , l D = 2mA 




Change in V GS(th) with Temperature 






-4.0 


mV/°C 


V GS = V DS , l D = 2mA 




Gate Body Leakage 






100 


nA 


V GS = =20V, V DS = 0V 


Idss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = Max Rating 












1 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 






0.6 




A 


V GS = 5V, V DS = 25V 








0.75 








V GS =10V, V DS = 25V 


^DS(ON) 


Static Drain-to-Source 






8 




12 


V GS =5V, l D = 100mA 




ON-State Resistance 






8 


10 


V GS = 10V, l D = 500mA 


A ^DS(th) 


Change in R DS(th) with Temperature 






0.75 


%/°C 


V GS = 10V, l D = 500mA 


G FS 


Forward Transconductance 


100 


160 




mU 


V DS = 25V, l D = 500mA 




Input Capacitance 




105 


130 




V GS = 0V, V DS = 25V 
f = 1 MHz 


c oss 


Common Source Output Capacitance 




25 


75 


PF 


Crss 


Reverse Transfer Capacitance 






10 


20 






td(ON) 


Turn-ON Delay Time 






10 






V 


Rise Time 






10 


ns 


V DD = 25V, 
l D = 0.5A, 
Rgen = 25£J 


'd(OFF) 


Turn-OFF Delay Time 






20 


tf 


Fall Time 






10 




V SD 


Diode Forward Voltage Drop 






1.8 


V 


V GS = 0V, l SD = 0.5A 


<rr 


Reverse Recovery Time 




300 




ns 


V GS = 0V, l SD = 0.5A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




8-50 



VN06D 



Typical Performance Curves 

Output Characteristics 



$ 0.75 















• 


'es = 


10V 





















































































































































































10 20 30 40 50 

V DS (volts) 
Transconductance vs. Drain Current 



£ 16 
CD 





V DS = 25V 




























Ta =-5! 


>°C 


































Ta 


= 2! 


>°C 
























































Ta = 


= 15C 


"C 





























































0.2 0.4 0.6 0.8 

l D (amperes) 
Maximum Rated Safe Operating Area 



0.01 









































































9 (pu 


set" 
























)- 












































































1 1 1 








s 
















m-3Q tnr.\ 












s 




































































































TO-92 (DC) 



















































































































10 100 

V DS (volts) 



Saturation Characteristics 

8V 



a 0.3 









V GS 


= 10V / 
























• 6V 
_ 5y 





































































































































































2 4 6 8 1C 

V DS (volts) 
Power Dissipation vs. Case Temperature 



I 
S 



TO-2 


20 






























































































TO-3 


9 










TO-92 











25 50 75 100 125 150 

T C (°C) 

Thermal Response Characteristics 



0.8 

to 
1 
o 





















TO-220 








P D =45W t 
























/ TO 


39 








= 6W 






Tc 


= 25°C 











0.001 0.01 0.1 1 10 

tp (seconds) 



8-51 



VN06D 



Typical Performance Curves 

BV DSS Variation with Temperature 




Transfer Characteristics 



<0 

2 1.5 

3 

CL 

E 

3- 

_Q 1.0 























5 -* 


t>v 
































































T 


A = 


55° ( 






















25° 


























































15CTC 








I 







2 4 6 8 10 

V GS (volts) 

Capacitance vs. Drain-to-Source Voltage 



o 







f = 1MHz 










C| SS 






















Coss 






Crss 



10 20 30 

V DS (volts) 



On-Resistance vs. Drain Current 



o 

S 8 
rr 



























-v G 


s = 


>V - 






s = 


ov 

































































































































































0.4 0.8 1.2 1.6 2.0 

l D (amperes) 
V(, h) and R DS Variation with Temperature 



"S 1.0 
E 



i. 08 
5> 
o 
> 



0.6 

































/ 












1 10V 


0.5A* 






v (th) 


@ 2mA 
























































































I 








I I 



1.5 jjj 



1.0 o 
D? 

0.5 



-50 



50 

Tj(°C) 



100 150 



Gate Drive Dynamic Characteristics 



CO 





























Vds 


= 10 












































Vd: 


j = 4 


OV 
































/ 1 


— 

80 p 




F 






















































10C 


PF 





































0.5 1.0 1.5 2.0 2.5 

Q e (nanocoulombs) 



VN06E 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


Rds<on) 
(max) 


'd(ON) 

(min) 


Order Number / Package 


BV DGS 


TO-39 


TO-92 


TO-220 


Dicet 


450V 


16Q 


0.5A 


VN0645N2 


VN0645N3 


VN0645N5 


VN0645ND 


500V 


16£i 


0.5A 


VN0650N2 


VN0650N3 


VN0650N5 


VN0650ND 



MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C| SS and fast switching speeds 

□ Excellent thermal stability 
Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 
I Amplifiers 

□ Switches 

□ Power supply circuits 

I Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 
Drain-to-Gate Voltage 



BV n 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 



Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 






8-53 




TO-92 


0.2A 


1.0A 


1W 


170 


125 


U.ZA 


1 .UA 


TO-220 


1.0A 


1.5A 


45W 


70 


2.7 


1.0A 


1.5A 



* l D (continuous) is limited by max rated T,. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 




Drain-to-Source 
Breakdown Voltage 


VN0645 


450 






V 


V GS = 0V, l D =2mA 


VN0650 


500 


^GS(th) 


Gate Threshold Voltage 


2 




4 


V 


Vro = Vno , In = 2mA 




Change in Vqs^j with Temperature 






-4.5 


mV/°C 


V GS =V DS , l D = 2mA 


, ' 


Gate Body Leakage 






100 


nA 


V r o = ±20V, V n o = 0V 


DSS 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0V, V DS = Max Rating 






1 


mA 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 




0.8 




A 


V GS = 5V, V DS = 25V 


0.5 


1.1 




V GS =10V, V DS = 25V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




12 




d 


V G s=5V, l D = 100mA 




11 


16 


V GS = 10V, l D = 400mA 


A ^DS(th) 


Change in R DS(th) with Temperature 






0.75 


%/°c 


V GS = 10V, l D = 400mA 




Forward Transconductance 


100 






m!! 


V DS = 25V, l D = 400mA 


C ISS 


Input Capacitance 




120 


130 


pF 


V GS = 0V, V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




20 


75 


Crss 


Reverse Transfer Capacitance 




10 


20 


'd(ON) 


Tum-ON Delay Time 






10 


ns 


V DD = 25V, 
l D = 0.5A, 
R GEN = 25£2 


t, 


Rise Time 






10 


'd(OFF) 


Turn-OFF Delay Time 






20 


tf 


Fall Time 






10 


V SD 


Diode Forward Voltage Drop 






1.8 


V 


V GS = 0V, l SD = 0.4A 


trr 


Reverse Recovery Time 




300 




ns 


V GS = 0V, \ so = 0.4A 



Notes: 

1 . All D.C. parameters 1 00% tested at 2S°C unless otherwise stated. (Pulse test: 300ms pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




8-54 



VN06E 

Typical Performance Curves 



Output Characteristics 



Saturation Characteristics 



1.0 

CO 













































































5 =6 


/to 1 


OV 






























I 





























































































































10 20 30 40 50 

V DS (volts) 



E 

CO 



4 6 

V DS (volts) 

























































3=6 


/to 1 


OV 






































■ 4V 









































































































8 10 



Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



™ 0.12 
C5 





V DS = 25V 










-55° 


C~ 














t a = 


















25° C 
















r T A = 














/ 




150' 


C " 






















S 




































& 


















> 





















0.2 0.4 0.6 0.8 1.0 

I D (amperes) 



i 



TO-22 

































































































TO-39 










TO-92 











25 50 75 100 125 150 

T C (°C) 



Maximum Rated Safe Operating Area 



Thermal Response Characteristics 























































_ TO- 


VX fnn 




J) 


















"Till 












— > 


S 




















M 






TO-220 (DC) 


















1 1 1 
















%- 
4 




TO-39 


DC 


) 






















DC 


























1 



































































































10 100 

V DS (volts) 



^ 0.8 

CO 

E 
o 



























TO 


-220 






P D =45W j 








= 25°C / 










X TO-3 


9 




r J( Pd = 6W 






T C = 


25° C 


-Sn 









0.001 0.01 0.1 1 10 

tp (seconds) 



8-55 



Typical Performance Curves 




VN06F 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


Rds<on) 
(max) 


'd(ON) 

(min) 


Order Number / Package 


BV DGS 


TO-39 


TO-92 


TO-220 


Dice+ 


550V 


20a 


0.25A 


VN0655N2 


VN0655N3 


VN0655N5 


VN0655ND 


600V 


20£2 


0.25A 


VN0660N2 


VN0660N3 


VN0660N5 


VN0660ND 



^MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process Flows 
and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C, ss and fast switching speeds 

□ Excellent thermal stability 
7 Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV DSS 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°C tO+150°C 


Soldering Temperature* 


300°C 


* Distance of 1.6 mm from case for 10 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 



TO-39 



TO-92 




TO-220 



Note: See package outline section for discrete pinout. 



8-57 



TO-39 


0.35A 


1.0A 


6W 


125 


21 


0.35A 


1.0A 


TO-92 


0.15A 


0.5A 


1W 


170 


125 


0.1 5A 


0.5A 


TO-220 


0.75A 


1.5A 


45W 


70 


5 


0.75A 


1.5A 



* l (continuous) is limited by max rated Tj. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VN0655 


550 






V 


y =01 = 2mA 


VN0660 


600 


^GS(th) 


Gate Threshold Voltage 


2 




4 


V 


V GS = V DS . I D = 2mA 




Change in V GS(th , with Temperature 






-4.5 


mV/°C 


V es = V DS , l D = 2mA 


GSS 


Gate Body Leakage 




100 


nA 


V es = ±20V, V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = Max Rating 






1 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 




0.8 




A 


V GS = 5V, V DS = 25V 


0.25 


1.0 




V GS =10V, V DS = 25V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




17 




a 


V GS =5V, l D = 100mA 




16 


20 


V GS = 10V, l D = 100mA 


A RDS(ttl) 


Change in R D s(th) witn Temperature 






0.75 


%/°c 


V GS = 10V, l D = 100mA 


Gfs 


Forward Transconductance 


50 


75 






V DS = 25V. I = 100mA 


Ciss 


Input Capacitance 




85 


130 


PF 


V GS = 0,V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




25 


75 


Crss 


Reverse Transfer Capacitance 




10 


20 


*d(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = 25V, 
l D = 0.25A 
R GEN = 25H 


t, 


Rise Time 






10 


'd(OFF) 


Turn-OFF Delay Time 






20 


t, 


Fall Time 






13 


v SD 


Diode Forward Voltage Drop 






1.8 


V 


V GS = 0, l SD = 100mA 


Irr 


Reverse Recovery Time 




300 




ns 


V GS = 0, l SD = 100mA 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 



INPUT 



OUTPUT 




8*58 



VN06F 



Typical Performance Curves 

Output Characteristics 



& 
E 

to 









































































s= 6 


V to ' 


















ov ■ 












































































































































1 



10 20 30 40 50 

V DS (volts) 
Transconductance vs. Drain Current 



£ 0.04 
CD 

































Ta 


















= -55°C 












































lA 


= 25 


































t a 


= 15 


rc 






















































5V 

































0.5 

l D (amperes) 
Maximum Rated Safe Operating Area 



a. 
E 
<o 



























































































































. TO 


22C 


ID 


Is 


e 


d) . 




















ill 






















TO-220 (D 


0) 






























































TO-39 (DC) 






















I I 
' TO-92 (DC 


' 


s 














































s 
































\ 






















































S 










s 







100 



Saturation Characteristics 



<B 0.5 
Q. 

E 
to 



















































Vgs 


= 6Vto 10V 



































































































































































4V 



3V 



8 12 

V DS (volts) 



16 20 



Power Dissipation vs. Case Temperature 



CO 

~Q 20 
Q- 



TO-2! 


■0 






























































































TO-39 










TO-92 











25 50 75 100 125 150 
T C (°C) 

Thermal Response Characteristics 



^ 0.8 

CO 

I 
o 



CO 

I o, 















































/ TO- 


39 








= 6W 






Tc = 


= 25°C~ 




















0.001 0.01 0.1 

tp (seconds) 



8-59 



Typical Performance Curves 



VN06F 




8-60 



VN0606 
VN0610 



2fia 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV DSS / 

BV DGS 


RdS(ON) 

(max) 


li 


Order Number / Package 


TO-92 


60V 


3£2 


1.5A 


VN0606L 


60V 


5£2 


0.75A 


VN0610LL 



Features 

Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C| SS and fast switching speeds 

□ Excellent thermal stability 
L Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±30V 


Operating and Storage Temperature 


-55°CtO+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 10 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




8-61 



VN0606/VN0610 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 

@ T c = 25°C 


% 

c/w 


°c/w 


TO-92 


0.31A 


1A 


1W 


156 


51 



l D (continuous) is limited by max rated T. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VN0610 


60 






V 


V GS = 0, l D = 100uA 


VN0606 


60 






V GS = 0. l D = 10uA 


V GS(th) 


Gate Threshold Voltage 


VN0610 


0.8 




2.5 


V 


V G s = v ds> l D = 1 mA 


VN0606 


0.8 




2.0 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±30V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = 50V 






500 


V GS = 0, V DS = 50V, 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


VN0610 


0.75 






A 


V GS = 10,V DS = 10V 




VN0606 


1.5 






V GS = 10,V DS =10V 


R DS(ON) 


Static Drain-to-Source 


VN0610 






7.5 


a 


V GS = 5V, l D = 0.2A 


ON-State Resistance 


VN0610 






5.0 


V GS = 10V, l D = 0.5A 




VN0606 






3.0 


V GS = 10V, l D =1A 


G FS 


Forward Transconductance 


170 






mU 


V DS = 10V, l D = 0.5A 


Ciss 


Input Capacitance 






50 


pF 


V GS = 0, V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 






25 


Crss 


Reverse Transfer Capacitance 






5 


'(ON) 


Turn-ON Time 






10 


ns 


Vpp = 25V, l D = 0.6A, 
R GEN = 25fi 


'(OFF) 


Turn-OFF Time 






10 


v SD 


Diode Forward 
Voltage Drop 


VN0610 




1.2 




V 


V GS = 0, l SD = 0.47A 


VN0606 




0.85 




V GS = 0, l SD = 0.47A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300jis pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




8-62 



VN0808 



1 



Ordering Information 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 





p 

™DS<ON) 

(max) 


'd(ON) 

(min) 


Order Number / Package 


TO-92 


80V 


4£2 


1.5A 


VN0808L 



Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C| SS and fast switching speeds 

□ Excellent thermal stability 
P Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±30V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


30CTC 


• Distance of 1 .6 mm from case for f seconds. 



Package Options 




8-63 



VN0808 



Thermal Characteristics 



Package 


l D (continuous)' 


I D (pulsed) 


Power Dissipation 

@ T c = 25°C 


■cm 


CM 


TO-92 

b- — 


.26A 




2.0A 


1W 


125 


26.4 
' 



Electrical Characteristics (@ 25°C unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source Breakdown Voltage 


80 






V 


l D = 10uA, V GS = 


V GS(th) 


Gate Threshold Voltage 


0.8 




2.0 


V 


v gs = v ds. I D = 1mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±15V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


HA 


V GS = 0, V DS = 80V 


500 


V es = 0, V DS = 0.8 x Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


1.5 






A 


V GS = 10V, V DS =10V 


^DS(ON) 


Static Drain-to-Source ON-State Resistance 






4 


£2 


V GS = 10V, l D = 1A 


Gfs 


Forward Transconductance 


170 






mO 


V DS = 10V, l D = 0.5A 


C ISS 


Input Capacitance 






50 


PF 


V GS = 0V, V DS = 25V 
f=1 MHz 


Coss 


Common Source Output Capacitance 






40 


Crss 


Reverse Transfer Capacitance 






10 


'(ON) 


Turn-ON Time 






10 


ns 


V DD = 25V, l D = 1A 
Rgen = 25iJ 


'(OFF) 


Turn-OFF Time 






10 


V SD 


Diode Forward Voltage Drop 




0.85 




V 


l SD = 0.35A, V GS = 



totes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300ms pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 

Vdd 




8-64 



VN10K 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


RdS(ON) 

(max) 


'd(ON) 

(min) 


Order Number / Package 


TO-52 


TO-92 


60V 


5Q 


0.75A 


VN10KN9 


VN10KN3 



High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 



Features 

□ Free from secondary breakdown 

□ TTL/CMOS compatibility 

□ Low input capacitance 

□ Fast switching speeds 

□ Reliable TO-92 package compatible with auto-insertion 

□ Complements VP01A P-channel devices 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Applications 

C Inductive load driver 

□ Display driver 

□ Line driver 

□ Analog switch 

□ Alternative to VN0106N3 



Package Options 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±30V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 




8-65 



















TO-52 


0.3A 


1.0A 


LOW 


170 


125 


1.5A 


1.0A 


TO-92 


0.3A 


1.0A 


LOW 


170 


125 


1.5A 


1.0A 



Notes: 

1 . I D (continuous) is limited by max rated "Fj. 

2. VN0106N3 can be used if an l D (continuous) of 0.5 is needed. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source VN10K 
Breakdown Voltage 


60 






V 


V GS = 0V, l D = 100uA 


V G s ( th) 


Gate Threshold Voltage 


0.8 




2.5 


V 


V r ,,,= Vr,,, lr,= 1mA 




Change in V GS(th) with Temperature 




-3.8 




mV/°C 


V GS = v ds- I D = 1mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = 15V, V DS = 0V 




Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0V, V DS = 48V 


500 


uA 


V GS = 0V, V DS = 48V,T A 125°C 


. 

D(ON) 


ON-State Drain Current 


0.75 






A 


V GS = 10V, V DS = 10V 


^DS(ON) 


Static Drain-to-Source 
ON-State Resistance 






7.5 


Ji 


Vac = 5V U = 2A 






5.0 


£2 


V GS = 10V, l D = 0.5A 


A f DS(th) 


Change in R DS(th) with Temperature 




0.7 




%/°C 


V GS = 10V, l D = 500mA, 




Forward Transconductance 


100 






mU 


V DS = 10V, l D = 500mA 


Ciss 


Input Capacitance 




48 


60 


pF 


V DS = 25V, 
f = 1 MHz 


'-'OSS 


Common Source Output Capacitance 




16 


25 


C RSS 


Reverse Transfer Capacitance 




2 


5 


'(ON) 


Turn-ON Time 






10 


ns 


V DD = 15V, l D = 0.6A, 
Rgen = 25Q 


'(OFF) 


Turn-OFF Time 






10 


v SD 


Diode Forward Voltage Drop 




0.8 




V 


V GS = 0V, l SD = 0.5A 


t,r 


Reverse Recovery Time 




160 




ns 


V GS = 0, Igp = 0.5A 



1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300ms pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




8-66 



VN10K 



Typical Performance Curves 



Output Characteristics 





III 


^ 1 






_. 


■ — 








1 


^4 
ii/ 


> 








s = 


ov 






n 

If 


v— 
t 












■6V. 






in 

w 


t 

i — 






































\ 




































































I I 









10 20 30 40 

V DS (volts) 



Transconductance vs. Drain Current 



200 
» 150 







































































































































v D 

30( 


S =1"V 
>HS, 2% 
y Cycle 
















Du 
















Pu 


se Test 

























200 400 600 800 1000 

l D (mA) 

Maximum Rated Safe Operating Area 



1.0 



0.1 























































































































































































































































































1 \J- 








1 











































































































































































1 10 100 1000 

V DS (volts) 

8-67 



Saturation Characteristics 



td 0.4 



o 



I I I 

Vgs = 10V 






V 


•7V 
















t 












8V 




*t 




















t 




















* 




















































/J 


f 























































2 4 6 8 

V DS (volts) 



Power Dissipation vs. Case Temperature 



















































TO-92 


TO-52 







































































25 50 75 100 125 150 

T C (°C) 
Switching Waveform 




10 20 30 40 50 

t - Time(ns) 



Typical Performance Curves 



VN10K 




Transfer Characteristics 



Output Conductance vs Drain Current 




ZZ V DS =25V 
80us, 1% 
DUTY CYCLE 
PULSE TEST 



Q 

a 



REDUCTION 
DUE TO 
HEATING 




8-68 



VN11A 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BVogs 


R DS(ON) 

(max) 


Ji 


Order Number / Package 


TO-39 


TO-220 


Dicet 


60V 


0.7J2 


8.0A 


VN1106N2 


VN1106N5 


VN1106ND 


100V 


0.7£J 


8.0A 


VN1110N2 


VN1110N5 


VN1110ND 



"■"MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C, ss and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°C to+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



IB 



Package Options 



TO-39 




TO-220 



Note: See package outline section for discrete pinout. 



TO-39 


2.5A 


DA 


DW 


125 


20.8 


2.5A 


DA 


TO-220 


7.0A 


18A 


45W 


70 


2.7 


7.0A 


18A 



' l D (continuous) is limited by max rated Tj. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to- Source 
Breakdown Voltage 


VN1110 


100 






V 


V GS = 0V, l D = 5mA 


VN1106 


60 


V GS(th) 


Gate Threshold Voltage 


0.8 




2.4 


V 


V G s= V ds . l D = 2mA 




Change in V GS ^ h j with Temperature 




-4 


-6 


mV/°C 


V GS = V DS , l D = 2mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±20V, V DS = 0V 


^DSS 


Zero Gate Voltage Drain Current 






50 


uA 


V GS = 0V, V DS = Max Rating 


1 


mA 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 125°C 


!d(ON) 


ON-State Drain Current 


3 


5 




A 

A 


V GS = 5V, V DS = 25V 


8 


18 


V GS =10V, V DS = 25V 


^DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




0.7 


1.0 


a 


V GS =5V, l D = 3A 




0.4 


0.7 


V GS = 10V. I D = 5A 


A ^DS(th) 


Change in R DS (th) witn Temperature 




0.3 


0.8 


%/°c 


V GS = 10V, l D = 5A 


Gfs 


Forward Transconductance 


1 


2 




u 


V DS = 25V, l D = 3A 


C| SS 


Input Capacitance 




240 


350 


PF 


V GS = 0V, V DS = 25V, 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




150 


200 


Crss 


Reverse Transfer Capacitance 




16 


25 


•d(ON) 


Turn-ON Delay Time 




10 


45 


ns 


V DD = 25V, 
l D = 3A, 
R GEN = 10£J 


t, 


Rise Time 




5 


14 


'd(OFF) 


Turn-OFF Delay Time 




35 


45 


tf 


Fall Time 




20 


35 


V SD 


Diode Forward Voltage Drop 




1.2 


1.6 


V 


V GS = 0V, l SD = 1A 


t,r 


Reverse Recovery Time 




300 




ns 


V GS = 0V, l SD = 1A 



Notes: 

1 . All D,C. parameters 1 00% tested at 25 n C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 



10V 



INPUT 



OUTPUT 




PULSE 
GENERATOR 





o OUTPUT 



D.U.T 



8-70 



Typical Performance Curves 

Output Characteristics 



16 



0) 



4 

















I i I 






































y 


















































































.5V. 





















































10 20 30 40 

V DS (volts) 



Transconductance vs. Drain Current 



2.0 



0.5 







v D s = 


25\ 








T A = 


-55 X 






























, 


Ta = 


25° 


C 












T A = 




150 


i 

°c 

















































































































4 8 12 16 20 



l D (amperes) 
Maximum Rated Safe Operating Area 



0.1 































































TC 








s 






















)-220 ( 


ed) 






















3: 






















\ 


\ 






























TO-220 (DC) 
































































\ 




















s 


k 










TO 


39 


(DC 


) 
















































































S 































































































0.1 1.0 10 100 



V DS (volts) 

8-71 



Saturation Characteristics 



20 



16 







































S=1 


ov 






















■ 8V 









































































































































































2 4 6 8 10 



V DS (volts) 



Power Dissipation vs. Case Temperature 



100 























































-TO-22 












o 


































-TO-39 































25 50 75 100 125 150 



T C (°C) 

Thermal Response Characteristics 




0.001 0.01 0.1 1.0 



t p (seconds) 



VN11A 



Typical Performance Curves 

BVqss Variation with Temperature 




Transfer Characteristics 



£ 12 
to 
o. 
E 

D 8 





















vd. 


5 »* 


bV 














































-55° 


C J 






















* 






















°c 


















15GPC 































































2 4 6 8 1! 

V GS (volts) 
Capacitance vs. Drain-to-Source Voltage 



a. 
O 



L f=1l 


lf»2 












Ciss 








c oss _ 








Crss 



On-Resistance vs. Drain Current 



2 1.0 
rr 



o 

































V 


GS = 


= 5V 
































































V G £ 


= 1 


DV 













































































































4 8 12 16 20 

l D (amperes) 
Vjid) and Rqs Variation with Temperature 



1 its 
o 

CO 

> 









































Rds 


(ON) c 


S 10V 


5A 








S 2m/ 









































































































i 

E 



i.o 6 

CO 
Q 

rr 

0.6 



50 100 

TifC) 

Gate Drive Dynamic Characteristics 



CD 
> 





















































V D 


S = 


ov 
















4f 


OpF / 








































r 480p 


1 
















/DS = 40V 
































































220 pF 

I 

















10 20 30 

V DS (volts) 



1 2 3 4 5 

Q G (nanocoulombs) 



VN12A 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


Rds<on) 
(max) 


If 


Order Number / Package 


BV DGS 


TO-39 


TO-220 


Dice* 


40V 


0.3Q 


20A 


VN1204N2 


VN1204N5 


VN1204ND 


60V 


0.3£2 


20A 


VN1206N2 


VN1206N5 


VN1206ND 


100V 


0.3O 


20A 


VN1210N2 


VN1210N5 


VN1210ND 



' MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C, ss and fast switching speeds 
D Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1.6 mm from case for 10 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




8-73 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 
@ T c = 25°C 


3a 

c/w 


3c 

c/w 


1 * 

'DR 


'dRM 


TO-39 


3.5A 


15A 


6.5W 


125 


20 


3.5A 


15A 


TO-220 


9A 


35A 


45W 


70 


2.75 


9A 


35A 



* l D (continuous) is limited by max rated fj, 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VN1210 


100 






V 


V GS = 0, l D = 10mA 


VN1206 


60 


VN1204 


40 


^GS(th) 


Gate Threshold Voltage 


0.8 




2.4 


V 


V G s = V DS , l D = 10mA 




Change in V GS(th) with Temperature 




-4.3 


-5.5 


mV/°C 


V GS = V DS , l D = 10mA 


'gss 


Gate Body Leakage 




1 


100 


nA 


V GS = ±20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






100 


^A 


V GS = 0, V DS = Max Rating 


10 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 1 25°C 


'D(ON) 


ON-State Drain Current 


5 


12 




A 


V GS = 5V, V DS = 25V 


20 


36 


V„„ - 1 0V V„„ - ?5V 

V GS — ,uv - v DS -,iov 


n DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




0.22 


0.45 


a 


V GS — ov > 'D — ^ n 


0.2 


0.3 


V GS = 10V, l D = 10A 


AR DS(ON) 


Change in R ds(0 n) witn Temperature 




0.85 


1.2 


%/°c 


V GS = 10V, l D = 10A 


Gfs 


Forward Transconductance 


4.0 






u 


V DS = 25V, l D = 5A 


Ciss 


Input Capacitance 




700 


850 


pF 


V GS = 0, V DS = 25V 
f = 1 MHz 


c oss 


Common Source Output Capacitance 




300 


350 


Crss 


Reverse Transfer Capacitance 




45 


75 


'd(ON) 


Turn-ON Delay Time 




8 


20 


ns 


V DD = 25V 
l D = 5A 
^GEN = 10£2 


t, 


Rise Time 




8 


30 


•d(OFF) 


Turn-OFF Delay Time 




70 


90 


t( 


Fall Time 




40 


60 


V S D 


Diode Forward Voltage Drop 




1.2 


1.4 


V 


V GS = 0, l SD = 10A 


trr 


Reverse Recovery Time 




500 




ns 


v gs = 0. I SD = 1A 



Notes: 

1. All D.C. parameters 100% tested at 25"C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




8-74 



Typical Performance Curves 



Output Characteristics 



Saturation Characteristics 





V 


1 

rac = 10V 




















































































































































































































3V 







10 20 30 40 50 

V DS (volts) 



? 15 
g> 

S 

a. 

a 10 



o 
o 



















«8V 








\ 


GS 


= 10V , 
























■6V 













































































































































2 4 6 8 

V DS (volts) 



Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



« 4 





















V D 


S =• 




























i 


A = 


-55" 


















































T"A = 


25° 


















































T 


1=' 


25" ( 













































5 10 15 

Id (amperes) 



1 

Q 
CL 



















































_TO-22 


n 












































-TO-3S 























25 50 75 100 125 150 
T C (°C) 



Maximum Rated Safe Operating Area 



Thermal Response Characteristics 



Q 





























































































— 1 


■o-; 


20 


(F 


u 


sod) 
































* 






















































TO-39 (DC) ^ 









































































































































































































1.0 10 

V DS (volts) 



100 



a 
E 
o 





TO-220 






P D =45W 






T C = 


25° C 








































/ TO-3 


t 






f P D =6.25W 






T c =25°C 



0.001 0.01 0.1 1 . 10 

tp (seconds) 



8-75 



Typical Performance Curves 

BV D ss Variation with Temperature 




100 150 



Transfer Characteristics 



£ 15 

a> 

Q. 

E 

nj_ 

Q 1.0 







5 = 25V 

^— 


































T A =-5 














































25° C 


















^1 























































































2 4 6 

V GS (volts) 



8 10 



Capacitance vs. Drain-to-Source Voltage 



to 

8 500 

a. 
O 



L t = 1 














Ciss 








s 






Coss 














Crss 









10 20 30 40 

V DS (volts) 



VN12A 



On-Resistance vs. Drain Current 



z 
o 

S 08 

































- V 


GS = 


5V 




































































v G 


s = 


10V 

























































































































10 20 30 40 50 

I D (amperes) 
V(, h) and R D s Variation with Temperature 



to 1.1 

E 
o 



1 0.9 

in 

o 

> 



0.7 

























R DS{C 


)N) @ 


10V, 


I0A 






V(th)« 


1 












y mil 


r\ 











































































































1.2 ™ 



0.8 o 
to 
o 



0.4 



-50 50 100 150 

Tj(°C) 

Gate Drive Dynamic Characteristics 



w 6 

o 







































































V 


DS = 
60 p 


10V 
















—12 




















F-y 




3 = « 


ov 




























1, 


)00r. 


F 




























590 pl- 

1 1 















2 4 6 8 10 

Q G (nanocoulombs) 



8-76 



VN1206 
VN1210 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


^DS(ON) 

(max) 


'd(ON) 

(min) 


Order Number / Package 


TO-39 


TO-92 


TO-220 


120V 




1.0A 


VN1206B 


VN1206L 


VN1206D 


120V 


10Q 


1.0A 




VN1210L 





High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 



Features 

E Free from secondary breakdown 
Low power drive requirement 
Ease of paralleling 
Low C, ss and fast switching speeds 
Excellent thermal stability 

□ Integral Source-Drain diode 

High input impedance and high gain 
Complementary N- and P-channel devices 

Applications 

□ Motor control 
U Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±30V 


Operating and Storage Temperature 


-55°C to+150°C 


Soldering Temperature* 


300°C 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertax's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




of 1 .6 mm from c 



3 for 10 



8-77 



VN1206/VN1210 



Thermal Characterisi 


tics 


Package 


l D (continuous)' 


l (pulsed) 


Power Dissipation 

@ T c = 25°C 


"C/W 


°c/w 


TO-39 


0.59A 


2.5A 


5W 


170 


25 


TO-92 


0.1 8A 


2.0A 


0.8W 


156 


21.3 


TO-220 


1.19A 


2.5A 


20W 


80 


6.25 



* l D (continuous) is limited by max rated Tj. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source Breakdown Voltage 


120 






V 


V GS = 0, l D = 100uA 


^GS(th) 


Gate Threshold Voltage 


0.8 




2.0 


V 


V GS = V DS. I D = 1mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±15V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = Max Rating 


500 


V GS = 0, V DS = Max Rating 
T A = 1 25°C 


'd(ON) 


ON-State Drain Current 


1.0 






A 


V GS =10V, V DS = 10V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 


ALL 






10 


n 


V GS = 2.5V, l D = 0.1A 


VN1206 






6 


V GS = 10V, l D = 0.5A 


VN1210 






10 


V GS = 10V, l D = 0.5A 


Gfs 


Forward Transconductance 


300 






m" 


V DS = 10V, l D = 0.5A 


Ciss 


Input Capacitance 






125 


PF 


V GS = 0V, V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 






50 


Crss 


Reverse Transfer Capacitance 






20 


tr 


Rise Time 






8 


ns 


V DD = 60V, l c = 0.4A 
Rgen = 25£1 


'd(ON) 


Turn-ON Delay Time 






8 


t, 


Fall Time 






12 


'd(OFF) 


Turn-OFF Delay Time 






18 


V SD 


Diode Forward Voltage Drop 


VN1210 




1.2 




V 


l SD = 0.12A, V GS = 


VN1206 




1.2 




V 


l SD = 0.25A, V GS = 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300ns pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 



ov 



10%, 


/ • 


^90% 




'(ON) 




'(OFF) 




l d(ON) 'r 




'd(OFF) V 








'90° 


io%it. 

90% ^ 




■-10% 





o OUTPUT 



D.U.T. 



8-78 



^ Supertexinc. 



VN13A 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


"dS(ON) 

(max) 


'd(ON) 

(min) 


Order Number / Package 


TO-39 


TO-92 


40V 


8Q 


0.5A 


VN1304N2 


VN1304N3 


60V 


an 


0.5A 


VN1306N2 


VN1306N3 


100V 


an 


0.5A 


VN1310N2 


VN1310N3 



High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C| SS and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 



Absolute Maximum Ratim 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


+ 20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




8-79 



VN13A 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 


% 


3c 


■dr 


'dhm 








@ T c = 25°C 


c/w 


°C/W 






TO-39 


0.4A 


1.4A 


3.0W 


125 


41.5 


0.4A 


1.4A 


TO-92 


0.25A 


1.3A 


LOW 


170 


125 


0.25A 


1.3A 



* Ip (continuous) is limited by max rated Tj, 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV CSS 


Drain-to-Source 
Breakdown Voltage 


VN1310 


100 






V 


V GS = 0V, l D = 1mA 


VN1306 


60 


VN1304 


40 


V GS(th) 


Gate Threshold Voltage 


0.8 




2.4 


V 


V GS = V DS. I D = 1mA 


AV GS(th) 


Change in V GS(th) with Temperature 




-3.9 


-5.0 


mV/°C 


V G s = v ds. I D = 1mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±20V, V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






1 


uA 


V GS = 0V, V DS = Max Rating 


100 


uA 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 125°C 


!d(ON) 


ON-State Drain Current 


0.25 


0.6 




A 


V GS = 5V, V DS = 25V 


0.50 


1.4 


V GS = 10V, V DS = 25V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




5 


15 


a 


V GS = 5V, l D = 50mA 


5 


8 


V GS = 10V, l D = 500mA 


AR DS(ON) 


Change in R DS(0N) with Temperature 




0.8 


2 


%/°c 


V GS = 10V, l D = 500mA 


G FS 


Forward Transconductance 


120 






u 


V DS = 25V, l D = 500mA 


C ISS 


Input Capacitance 




27 


35 


PF 




V GS = 0V, V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




13 


15 


Crss 


Reverse Transfer Capacitance 




3 


5 


•d(ON) 


Turn-ON Delay Time 




2 


5 


ns 


V DD = 25V 
l D = 250mA 
R GEN = 25£2 


t, 


Rise Time 




2 


5 


•d(OFF) 


Turn-OFF Delay Time 




2 


6 


tf 


Fall Time 




2 


5 


V SD 


Diode Forward Voltage Drop 




1.0 


1.3 


V 


V GS = 0V, l SD = 1.0A 


trr 


Reverse Recovery Time 




350 


ns V GS = 0V, l so = 1 .OA 



Notes: 

1 . All D.C. parameters 1 00% tested at 25 C C unless otherwise stated. (Pufse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



V D0 




8-80 



Typical Performance Curves 



VN13A 



Output Characteristics 



Saturation Characteristics 

























































s = 


ov 














































ft 














?6V- 



















































































10 20 30 40 50 

V DS (volts) 



1 0.8 

























































V GS =10V 


























































.6Vi 































































































2 4 6 

V DS (volts) 



Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



£ 

3- 

E2 0.2 

o 







I 


















S =' 
















































T A = -55°C 
















T A = 25°C 










































T 


A = 125° 

■ 

































































0.4 0.8 1.2 1.6 2.0 

l D (amperes) 



I 
1 







































TO-3S 
















































TO-92 





































25 50 75 100 125 150 

T C (°C) 



Maximum Rated Safe Operating Area 



Thermal Response Characteristics 



o 
a. 
E 

CO 



































































































1 
























"0-39 (pu 


sed) 




















m 














1 


'O-S 


2 ( 


DC 










v- 

TO- 


39 


DC 


) 




















\ 


























\ 


























s 



























0.1 1.0 10 

V DS (volts) 



^ 0.8 

CO 

I 

o 



CO 

CD 

rr 

« 
E 

CD 





















































✓ TA.1 


o 






r P D =3.0W 






Tc = 


25° C 













0.001 0.01 



Typical Performance Curves 



VN13A 




8-82 



VN1706 
VN1710 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


f DS(ON) 

(max) 


If 


Order Number / Package 


TO-39 


TO-92 


TO-220 


170V 


6n 


1.0A 


VN1706B 


VN1706L 


VN1706D 


170V 


ion 


1.0A 




VN1710L 





High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C lss and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±30V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertax vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 



TO-39 



TO-92 




TO-220 



Note: See package outline section for discrete pinout. 



VN1706/VN1710 



Thermal CI 




Package 


l D (continuous)' 


1 D (pulsed) 


Power Dissipation 

© T c = 25°C 


3a 
"C/W 


x/w 


TO-39 


0.63A 


3.0A 


6.25W 


170 


20 


TO-92 


0.22A 


2.3A 


0.8W 


156 


21.3 


TO-220 


1.12A 


3.0A 


20W 


80 


6.25 



' l D (continuous) is limited by max rated Tj. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Sumhnl 


Parameter 


Min 


Tvn 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source Breakdown Voltage 


170 






y 


v„ - ov i - 100mA 


v GS(th) 


Gate Threshold Voltage 


8 




2 


V 


V GS = V DS. I D = 1mA 


I 

'gss 


Gate Body Leakage 






1 00 


nA 


V GS = 15V, V DS = 0V 


| 

'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0V, V DS = 120V 


500 


Vr-o = 0V Vno = 1 20V 

GS ' DS 

T A = 125°C 


'd(on) 


ON-State Drain Current 


1.0 






A 


V GS = 10V,V DS = 10V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 


ALL 






10 


Q 


V GS = 2.5V, l D = 0.1A 


VN1710 






10 


V GS = 10V, l D = 0.5A 


VN1706 






6 


V GS = 10V, l D = 0.5A 


Gfs 


Forward Transconductance 


300 






m!i 


V DS = 10V, l D = 0.5A 


C ISS 


Input Capacitance 






125 


pF 


V GS = 0V, V DS = 25V 
f = 1 MHz 


'-'OSS 


Common Source Output Capacitance 






50 


Crss 


Reverse Transfer Capacitance 






20 




Rise Time 








8 


ns 


V DD = 60V, l D = 0.1 A 
R GEN = 25H 


'd(ON) 


Turn-ON Delay Time 






8 


t. 


Fall Time 






9 


'd(OFF) 


Turn-OFF Delay Time 






13 




Diode Forward 
Voltage Drop 


VN1710 




1.2 




V 


l SD = 0.19A, V GS = 0V 


VN1706 




1.2 




V 


l SD = 1.4A, V GS = 0V 



1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300ns pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




8-84 



^ Supertex inc. 



VN2010L 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV DSS / 


"dS(ON) 

(max) 


V GS(th) 

(max) 


Order Number / Package 


TO-92 


200V 


10O 


2.0V 


VN2010L 



Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C, ss and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

□ Telecom switching 



Absolute Maximum Ratings 



Drain-to-Source Voltage 


BV DSS 


Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±30V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertax's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




8-85 



VN2010L 



Thermal Characteristics 



Package 


l (continuous)* 


l D (pulsed) 


Power Dissipation 






■dr 


'drm 








@ T c = 25°C 


°c/w 


C/W 






TO-92 


250mA 


1.0A 


1W 


170 


125 


250mA 


1.0A 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source Breakdown Voltage 


200 






V 


V GS = 0V, l D = 100uA 


V GS(th) 


Gate Threshold Voltage 


0.8 




2.0 


V 


v gs = v ds. I D = 1rnA 


'qss 


Gate Body Leakage 






10 


nA 


V GS = ±25V, V DS = 0V 


Idss 


Zero Gate Voltage Drain Current 






1.0 


uA 


V GS = 0V, V DS = 160V 


100 


V GS = 0V, V DS = 160V 
T A = 125°C 


^DS(ON) 


Static Drain-to-Source ON-State Resistance 






10 


n 


V GS = 4.5V, l D = 50mA 


'd(ON) 


ON-State Drain Current 


100 






mA 


V GS = 10V, V CS = 10V 


Gfs 


Forward Transconductance 


125 






mt5 


V DS =15V, l D = 0.1A 


Ciss 


Input Capacitance 






60 


pP 


V GS = 0V, V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 






30 


Crss 


Reverse Transfer Capacitance 






15 


'(ON) 


Turn-ON Time 






20 


ns 


V DD = 25V, l D = 0.1 A 
R GEN = 25D 


'(OFF) 


Turn-OFF Time 






30 


V SD | Diode Forward Voltage Drop 




1.8 


V 


V GS = 0V, l SD = 250mA 



Notes: 

1 . All D C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 



OUTPUT 



0V 



10% 7 


/ ' 


^90% 








'(OFF) 




l d(ON) l r 


'd(OFF) 


'f 








«%* 

90% > 


V 7 


■-to% 

c 




VN21A 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


"dS(ON) 

(max) 


Order Number / Package 


BV DGS 


TO-92 


20 Terminal Ceramic LCC 


Die^ 


60V 


4ii 


VN2106N3 


VN2106NF 


VN2106ND 


100V 


4n 


VN2110N3 


VN2110NF 


VN2110ND 



f MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Commercial and Military versions available 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Low C| SS and fast switching speeds 

□ High input impedance and high gain 

Applications 

□ Motor control □ Converters 

□ Amplifiers □ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Pin Configuration 

G„ NC D S, NC 



NC 

S 4 
D , 
NC 

e, 



17 16 15 14 




G 3 
NC 

D 3 
NC 



NC S, D 2 NC G, 

20-pin Ceramic LCC 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




TO-92 



Type "C" Leadless 
20 Terminal 
Ceramic Chip Carrier 



Note: See package outline section for discrete pinout. 



VN21A 



Thermal Characteristics 



Package 


l D (continuous)' 


l D (pulsed) 


Power Dissipation* 






W 


'drm 








@ T c = 25°C 


°c/w 


°c/w 






TO-92 


0.25A 


1.0A 


LOW 


170 


125 


0.25A 


1.0A 


20 Terminal LCC 


0.46A 


2.0A 


1.25W 


170 


100 


0.46A 


2.0A 



* l D (continuous) is limited by max rated T . 

* Total for package. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VN2110 


100 






V 


l D =1mA, V GS = 0V 


VN2106 


60 


V GS(lh) 


Gate Threshold Voltage 


0.8 




2.4 


V 


v gs = v ds. l D = 1mA 


AV GS(th) 


Change in V GS(th) with Temperature 




-3.8 


-5.5 


mV/°C 


l D = 1mA, V GS = V DS 


'gss 


Gate Body Leakage 




0.1 


100 


nA 


V GS = ±20V, V DS = 0V 


loss 


Zero Gate Voltage Drain Current 








1 


uA 


V GS = 0V, V DS = Max Rating 






100 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 1 25°C 




ON-State Drain Current 


0.15 


1.0 




A 


V GS = 5V, V DS = 25V 


1.0 


2.50 




V rt; = 10V, V n <; = 25V 




Static Drain-to-Source 
ON-State Resistance 




4.50 


6 


£i 


Vro = 5V, In = 75mA 




2 


4 


V GS = 10V, l D = 500mA 


AR DS(ON) 


Change in R DS( on) with Temperature 




0.70 


1.0 


%/°c 


l D = 500mA, V GS = 10V 




Forward Transconductance 


150 


400 




mU 


V DS = 25V, l D = 0.5A 


Ciss 


Input Capacitance 






50 


PF 


V gs = 0V . V cs = 25V 
f = 1 MHz 


c oss 


Common Source Output Capacitance 






25 


Crss 


Reverse Transfer Capacitance 






5 


'd(ON) 


Turn-ON Delay Time 




3 


5 


ns 


V DD = 25V 
l D = 1.0A 
Rqen = 25Q 


<r 


Rise Time 




5 


8 


^d(OFF) 


Turn-OFF Delay Time 




6 


9 


t, 


Fall Time 




5 


8 


V SD 


Diode Forward Voltage Drop 




1.2 


1.8 


V 


l SD = 1.0A, V GS = 0V 


trr 


Reverse Recovery Time 




400 




ns 


l SD = 1.0A, V GS = 0V 



1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse 

2. All A.C. parameters sample tested. 



test: 300u.s pulse, 2% duty cycle.) 



Switching Waveforms and Test Circuit 



10V 



INPUT 



OUTPUT 



0V 






c OUTPUT 



D.U.T. 



Performance Curves 

Output Characteristics 



CL 

E 

(0 





































V G 


























t 


















{ 








































■ mm 



























































10V 

9V 

8V 

7V 
6V 

5V 
4V 

3V 



10 20 30 40 50 

V DS (volts) 
Transconductance vs. Drain Current 



2 0.2 



























S =' 


>5V 














































= -5£ 


°C 


















— 25°C- 




































12E 


°C 



































































0.2 0.4 0.6 0.8 

l D (amperes) 
Maximum Rated Safe Operating Area 































































20 


Te 


mir 


a 


< 


Derari 


TiC 


,cc 




> 


jlsed 


) 








I i r:T r 

TO-92 (pulsed) 
1 — h— H-H 1 — 




*» 








— 20-Terminal Ceramic 












* 


» 


s. 
























TC 


-92 


(D 

















































































































































































Saturation Characteristics 



VN21A 



03 

I 

<0 0.8 



















V G 


3 — 






































































■ 














> 


















































































4 


I 


f 

















































10V 
9V 
8V 
7V 

6V 
5V 
4V 
3V 



2 4 6 8 1C 

V DS (volts) 
Power Dissipation vs. Case Temperature 



| 1.0 































Termins 
ramie L( 










20- 

i. Ce 


I 


















TO-9 





























































25 50 75 100 125 150 
T C (°C) 

Thermal Response Characteristics 



0.2 































































TC 


)-92 






Tc 


= 25°C _ 
= 1W — 






P D 



1 10 

V DS (volts) 



0.001 0.01 0.1 1.0 10 

tp (seconds) 



8-89 



Typical Performance Curves 

BV DSS Variation with Temperature 




100 150 



Transfer Characteristics 



0) 1 .2 

g 

Q. 

E 
a 





I I 
















VD! 


; »* 


av 












/ 

/ 












Ta 


= -5 




f / 


/ 


















/ 


✓ 

✓ 
















/ y 


✓ 

! 




































*\ 




5°C 





























































2 4 6 8 1( 

V GS (volts) 
Capacitance vs. Drain-to-Source Voltage 



o 





f= 1MHz 








„ C| S s 














^oss 
















_ Crss 















On-Resistance vs. Drain Current 



VN21A 



z 

o 

U) 4 
o 
rr 

























v 


3S = 


5V 












































' v GS = 


10V 




s 

























































































































0.5 1.0 1.5 2.0 2.5 

Id (amperes) 
v GS(th) and R DS(ON) Variation with Temperature 

2.0 




Gate Drive Dynamic Characteristics 



> 



























3=1 


OV 








































J 


)0 pF 




























































































f 


30 










V 


DS : 


= 40* 


r 























10 20 30 

V DS (volts) 



0.2 0.4 0.6 0.8 1.0 

Q G (nanocoulombs) 



8-90 



ft 



VN22A 

Supertex inc. 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV DSS / 


R DS(ON) 

(max) 


If 


Order Number / Package 




TO-92 


Dice+ 


60V 


0.35£2 


8A 


VN2206N3 


VN2206NID 


100V 


0.35n 


8A 


VN2210N3 


VN2210ND 



t MIL visual screening available 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C, ss and fast switching speeds 

□ Excellent thermal stability 

7~ Integral Source-Drain diode 

□ High input impedance and high gain 
Complementary N- and P-channel devices 



Applications 

□ Motor control 

□ Converters 
Amplifiers 

□ Switches 

□ Power supply circuits 



Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 



Absolute Maximum Ratings 



Drain-to-Source Voltage 


BV DSS 


Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


• Distance of 1.6 mm from case for 10 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a vertical 
DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inherent 
in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range of 
switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




VN22A 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 

® T c = 25°C 


°c/w 


°c/w 


I * 


'drm 


TO-92 


1.2A 


8.0A 


LOW 


170 


125 


1.2A 


8.0A 



* l D (continuous) is limited by max rated T r 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 




Drain-to-Source 
Breakdown Voltage 


VN2206 


60 






V 


V GS = 0V, l D = 10mA 


VN2210 


100 


^GS(th) 


Gate Threshold Voltage 


0.8 




2.4 


V 


V GS = V DS , l D = 10mA 


AV GS(trl ) 


Change in V GS(th) with Temperature 




-4.3 


-5.5 


mV/°C 


V QS = V DS , l D = 10mA 


'gss 


Gate Body Leakage 




1 


100 


nA 


V GS = +20V, V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






50 


uA 


V GS = 0V, V DS = Max Rating 


10 


mA 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


3 


4.5 




A 


V GS = 5V, V DS = 25V 


8 


17 


V GS =10V, V DS = 25V 


^DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




0.4 


0.5 


Q 


V GS = 5V, l D = 1A 


0.27 


0.35 


V GS =10V, l D = 4A 


A RdS(ON) 


Change in R C s(ON) wi,n Temperature 




0.85 


1.2 


°o/'C 


V GS =10V, l D = 4A 


G FS 


Forward Transconductance 


1.5 


2.0 




u 


V DS = 25V, l D = 2A 


C ISS 


Input Capacitance 




300 


500 


PF 


V GS = 0V, V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




125 


200 


Crss 


Reverse Transfer Capacitance 




50 


65 


•d(ON) 


Turn-ON Delay Time 




10 


15 


ns 


V DD = 25V 
l D = 2A 
R GEN = 10£2 


'r 


Rise Time 




10 


15 


'd(OFF) 


Turn-OFF Delay Time 




30 


50 


tf 


Fall Time 




30 


50 


V SD 


Diode Forward Voltage Drop 




1.0 


1.6 


V 


V GS = 0V, l SD = 4A 


trr 


Reverse Recovery Time 




500 




ns 


V GS = 0V, l SD = 1A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300(is pulse, 2% duty cycle.) 

2. AII A.C. parameters sample tested. 




VN22A 



Typical Performance Curves 

Output Characteristics 



CD 
CL 

E 

CO 



































v G s = 


ov 






















r 


















4 














8V 
























f 




















































6V 


























































4V 



























10 20 30 40 50 

V DS (volts) 
Transconductance vs. Drain Current 

























v D 


S =' 


>5V 














































TA = 


-55 


O— 


















































25°C 
I 


















150 


c 






i 


















t 









































0.8 1.6 2.4 3.2 4.0 

l (amperes) 
Maximum Rated Safe Operating Area 



2 

0> 
Q. 

E 

CO 



























TO-92 


pulsed) 


\ 

- -A 


































< 


► 












T 


3-9 


2 


E 


)C) 










\ 

\ 


N 






























\ 
































X 






























— * 


r 


► 

























































































































































1 10 

V DS (volts) 



Saturation Characteristics 



-5- 12 
m 



i 8 

















I 

V^o - 10V _ 


























































8V 




























































6V 








































4V 


















[3V_ 





2 4 6 8 1( 

V DS (volts) 
Power Dissipation vs. Case Temperature 



03 1.0 
3 































































TO-9 





























































25 50 75 100 125 150 

T C (°C) 

Thermal Response Characteristics 



I 
o 

CD 
O 

c 
3 
v> 

CO 
CD 
DC 

« 
I 



0.8 































































TC 


)-92 






Ta 


= 25°C 

= iw — 






Pd 



0.001 0.01 0.1 1 10 

tp (seconds) 



Typical Performance Curves 

BV DSS Variation with Temperature 



S 




Transfer Characteristics 













// 

/ , 


/ 

< 






VD. 


; 


5V 






/ 


/ 


















V~t 


/ 

t 












T A 


= -5! 






















ff * 


./ 


5°C 
















7 * 
' i 


















at 


V 


:150' 


C 














ft 



















































4 6 
V GS (volts) 



e 10 



Capacitance vs. Drain-to-Source Voltage 



o 
o 
a. 

O 





f= 1MHz 












Ciss 














Coss 








Crss 









10 20 30 

V DS (volts) 



40 



VN22A 

On-Resistance vs. Drain Current 



J 0.6 
o 





























; =5V 










































Vqs = 1°V 






) 














h 






































/ 



































































4 8 12 16 20 

l (amperes) 
VQS(th) an d Rds(ON) Variation with Temperature 



> 



0.7 



























3(ON) 


@ 10' 


/,4A 


























































































VGS(th) @ 10nA 







































16 ■§ 

76 
I 

1.2 O 

o 

CO 

0.8 a 



50 

T,(°C) 



100 150 



Gate Drive Dynamic Characteristics 



w 6 



>° 4 





















































v D 


s = 


ov 


































90C 


pF 










































/ v 


DS = 


40V 


























300 


pF 





































2 4 6 8 10 

Q G (nanocoulombs) 



8-94 



VN22C 




N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


R DS(ON) 

(max) 


If 


Order Number / Package 


TO-39 


TO-92 


Dicet 


200V 


1.25S2 


5.0A 


VN2220N2 


VN2220N3 


VN2220ND 


240V 


1.250 


5.0A 


VN2224N2 


VN2224N3 


VN2224ND 



MIL visual screening available 



High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C| SS and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 



Drain-to-Source Voltage 


BV DSS 


Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a ver- 
tical DMOS structure and Supertax's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range of 
switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Options 




* Distance of 1 .6 mm from case for 10 seconds. 



VN22C 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 






l * 
'dr 


'drm 








@ T c = 25°C 


c/w 


°c/w 






TO-39 


1.5A 


7.0A 


6.0W 


125 


21 


1.5A 


7.0A 


TO-92 


0.9A 


5.0A 


LOW 


170 


125 


0.9A 


5.0A 



r l D (continuous) is limited by max rated T 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VN2224 


240 






y 


V GS = 0V, l D = 5mA 


VN2220 


200 


^GS(tti) 


Gate Threshold Voltage 


1.0 




3 


V 


V GS = v ds. Id = 5mA 




Change in V GS(th) with Temperature 




-3.7 


-4.5 


mV/°C 


v gs = v ds. 'd = 5mA 


'gss 


Gate Body Leakage 




1 


100 


nA 


V GS = +20V. V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






50 


uA 


V GS = 0V, V DS = Max Rating 


5 


mA 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


2 






A 


V GS = 5V, V DS = 25V 


5 


10 


V GS = 10V, V DS = 25V 




RdS(ON) 


Static Drain-to-Source 
ON-State Resistance 




1.0 


1.5 


Q 


V GS = 5V, l D = 2A 


0.9 


1.25 


V es =10V, l D = 2A 


A ^DS(ON) 


Change in R DS(0N ) with Temperature 




1.0 


1.4 


%/°C 


V GS = 10V, l D = 2A 




Forward Transconductance 


1.0 


2.2 




u 


V DS = 25V, l D = 2A 


C ISS 


Input Capacitance 




300 


350 


pF 


V GS = 0V, V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




85 


150 


Crss 


Reverse Transfer Capacitance 




20 


35 


'd(ON) 


Turn-ON Delay Time 




6 


15 


ns 


V DD = 25V 
l D = 2A 
R GEN = 10O 


tr 


Rise Time 




16 


25 


'd(OFF) 


Turn-OFF Delay Time 




65 


90 


tf 


Fall Time 




30 


60 


V SD 


Diode Forward Voltage Drop 




0.8 


1.0 


V 


V GS = 0V, l SD = 100mA 


'rr 


Reverse Recovery Time 




500 




ns 


V GS = 0V, l SD = 1A 



Notes: 

1 .All D.C. parameters 1 00% tested at 25°C 
2. All A.C. parameters sample tested. 



(Pulse test: 300us pulse, 2% duty cycle.) 



Switching Waveforms and Test Circuit 



ov 10% 



OUTPUT 




PULSE 
GENERATOR 





VN22C 



Typical Performance Curves 

Output Characteristics 







! 


— 


■ 








V G 


3 = 


uv 












A 




















AT. 
if 


















-A 

4 


f~ 















































































































































































10 20 30 40 50 

V DS (volts) 
Transconductance vs. Drain Current 



CO 
LL 
O 





I I 

w mi 
















»D 


S - ' 


.JV 






































T 


^ = - 


55°C 








































\ 


\ — 


\ 














~ S 


/ 
\ 
— V 


\ 


\ 








— T. 








I 

V 


\ 


V 

\ 










T 


A = 1 


25°( 


; x 




\ 

v — 


r I I 






I 




\ 





Id (amperes) 
Maximum Rated Safe Operating Area 



0.001 





I-HH--K 


















J-3 


I 


Dulsec 


) 


> 






















-39 


(D< 




k 






















;_to 


3) 






























































3-9 


!( 




















T( 


XI) 

















































































































10 100 

V DS (volts) 



1000 



Saturation Characteristics 



I 
5 

Q. 

I 4 























































V G 


S = 


0^ 


,8V 


















,6V" 






















































































































■3V- 

























2 4 6 

V DS (volts) 



8 10 



Power Dissipation vs. Case Temperature 



Q 
0_ 







































TO 


39 


























































TO 


92 











25 50 75 100 125 150 

T C (°C) 

Thermal Response Characteristics 



N 0.8 

to 



I 0.2 

































































)-92 






T A 


= 25 °C 
= 1W — 






' Pd 



0.001 0.01 0.1 1 10 

tp (seconds) 



8-97 



Typical Performance Curves 

BV DSS Variation with Temperature 




T, (°C) 



Transfer Characteristics 



E 
a 







1 

; =25V 

1 




I i 
1 1 


# 














f 1 
/ t 














-55° 






25°C 


















1 
















ft 




25°C 
















ft 
1 
















gi 



































































V G S (VOIIS) 



Capacitance vs. Drain-to-Source Voltage 



o 
o 
a. 

O 





f = 1MHz 




Ciss 
























c oss 





Crss 



10 20 30 

V DS (volts) 



On-Resistance vs. Drain Current 



co 2 































- V 


3S = 


5V 
























































J 
























































— «■ » 






'gs 


= 10 


1/ _ 





































2 4 6 8 1C 

l D (amperes) 
V( t h) and R DS Variation with Temperature 



ffl 1.0 

I 

o 
c 

£ 0.8 
in 
a 
> 









































F 


DS @ 


10V, 


2A 






















































@ 5r 


nA 





























































50 
TiCC) 



100 150 



Gate Drive Dynamic Characteristics 



> 





























V 


DS = 


10V 






































Vr 


a 


40 V 
















733 pF 




































































iF 
















f I I 

















2 4 6 8 

Q G (nanocoulombs) 



VN2222 




Ordering Inform; 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



BV DSS / 
BV DGS 


RqS(ON) 

(max) 


'd(ON) 

(min) 


Order Number / Package 


TO-92 


60V 


7.5Q 


0.75A 


VN2222LL 



Features 

□ Free from secondary breakdown 

□ Low power drive requirement 
Z Ease of paralleling 

Z Low C| SS and fast switching speeds 

Z Excellent thermal stability 

Z Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Applications 

□ Motor control 

□ Converters 
Z Amplifiers 
Z Switches 

Z Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±30V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 




□ QQ 

o-yy 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 




3c 








@ T c = 25°C 


c/w 


°c/w 


TO-92 


0.23A 


1.0A 


0.8W 


156 


51 



* f D (continuous) is limited by max rated Tj. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source Breakdown Voltage 


60 






V 


V GS = 0V, l D =100uA 


^GS(th) 


Gate Threshold Voltage 


0.6 




2.5 


V 


v gs = v ds. I D = 1mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±20V, V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0V, V DS = Max Rating 


500 


V GS = 0V, V DS = 48V 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


0.75 






A 


V GS = 10V, V DS = 10V 


RdS(ON) 


Static Drain-to-Source ON-State Resistance 






7.5 


£2 


V GS = 5V, l D = 0.2A 






7.5 


n 


V GS = 10V, l D = 0.5A 


Gfs 


Forward Transconductance 


100 






mU 


V DS = 10V, l D = 0.5A 


C ISS 


Input Capacitance 






60 


PF 


V GS = 0V, V DS = 25 
f = 1 MHz 


Coss 


Common Source Output Capacitance 






25 


Crss 


Reverse Transfer Capacitance 






8 


t(ON) 


Turn-ON Time 


10 


ns 


V DD = 15V, l D = 0.6A 
R GEN = 25£i 


'(OFF) 


Turn-OFF Time 






10 


Vso 


Diode Forward Voltage Drop 




0.85 




V 


V GS = 0V, l so = 0.2A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300u.s pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




8-100 



VN2406 
VN2410 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BVdss/ 

BV DGS 


R DS(ON) 

(max) 


If 


Order Number / Package 


TO-39 


TO-92 


TO-220 


240V 


6a 


1.0A 


VN2406B 


VN2406L 


VN2406D 


240V 


10Q 


1.0A 




VN2410L 





High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C| SS and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 
Converters 
Amplifiers 

i Switches 
I I Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 



Absolute Maximum Ratings 


Drain-to-Source Voltage 


BV DSS 


Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


+ 30V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertax's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 



Distance of 1.6 mm from case for 10 seconds. 



TO-39 



TO-92 




TO-220 



Note: See package outline section for discrete pinouts. 



8-101 



VN2406/VN2410 



Thermal Characteristics 



Package 


l D (continuous)* 
@ T c = 25°C 


l D (pulsed)* 
c/w 


Power Dissipation 
°C/W 


% 


9c 


TO-39 


0.63A 


3.0A 


6.25W 


170 


20 


TO-92 


0.17A 


1.7A 


0.8W 


156 


21.3 


TO-220 


1.12A 


3.0A 


20W 


80 


6.25 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


240 






V 


V G s = 0. l D = °- 1mA 


V GS(th) 


Gate Threshold Voltage 


0.8 




2 


V 


V G s = V DS , l D = 10mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = 20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0, V DS = 120V 










500 


V GS = 0, V DS = 120V 
T A = 1 25°C 


'd(ON) 


ON-State Drain Current 


1.0 






A 


V^o = -10V V^= = 10V 

V G S <W, v Qg — ivv 


RdS(ON) 


Static Drain-to-Source 
ON-State Resistance 


All 






10 




V™ - 2 5V U - 1 A 


VN2410 






10 


V QS = 10V, l D = 0.5A 


VN2406 






6 


V GS = 10V, l D = 0.5A 


AR DS( on) 


Change in R DS (on) witn Temperature 




1.0 


1.4 


%/°c 


V GS = 10V, l D = 5A 


Gfs 


Forward Transconductance 


300 






mu 


V DS = 10V, l D = 0.5A 


Ciss 


Input Capacitance 






125 


PF 


V GS = 0, V DS = 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 






50 


C RSS 


Reverse Transfer Capacitance 






20 




Turn-ON Delay Time 






8 


ns 


V DD = 60V 
l D = 0.4A 
R GEN = 25£1 




Rise Time 






8 


'd(OFF) 


Turn-OFF Delay Time 






18 


tf 


Fall Time 






12 




Diode Forward Voltage Drop 


VN2410 




1.2 




V 


V GS = 0, l SD = 0.19A 


VN2406 




1.2 




V 


V GS = 0. 'sD = 0-8/\ 



Notes: 

1. All D.C. parameters 100% tested at 25°C unless otherwise slated. (Pulse test: 300ms pulse. 2% duty cycle.) 

2. All A.C. parameters sample tested. 




8-102 



VN3515L 
VN4012L 



1 



N-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 



BV DSS / 

BV DGS 


" DS<ON) 

(max) 


VGS(th) 

(max) 


If 


Order Number / Package 


TO-39 


TO-92 


350V 


15H 


1.8V 


0.1 5A 




VN3515L 


400V 


12Q 


1.8V 


0.1 5A 


VN4012B 


VN4012L 



Features 

Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C| SS and fast switching speeds 
Excellent thermal stability 
Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Applications 

Motor control 

□ Converters 

□ Amplifiers 

□ Telecom Switching 
Power supply circuits 

□ Drivers (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±30V 


Operating and Storage Temperature 


-55°C to+150°C 


Soldering Temperature* 


300°C 


" Distance of 1 .6 mm from case for 1 seconds. 



Package Options 




8-103 



VN3515L/VN4012L 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 






'dr* 


'drm 








@ T c = 25°C 


c/w 


°C/W 






VN3515L 


150mA 


600mA 


ivy 


156 


125 


150mA 


600mA 


VN4012B 


420mA 


1.3A 


5W 


125 




420mA 


1.3A 


VN4012L 


160mA 


650mA 


1W 


156 


125 


160mA 


650mA 



* l D (continuous) is limited by max rated T f . 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VN3515 


350 






V 


V GS = 0, l D = 100uA 


VN4012 


400 


^GS(th) 


Gate Threshold Voltage 


0.6 




1.8 


V 


v gs = v ds. I D = 1mA 


'gss 


Gate Body Leakage 






10 


nA 


V GS = ± 20V, V DS = 


'dss 


Zero Gate Voltage Drain Current 






1 


uA 


V GS = 0, V DS = Max Rating 


100 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 




0.15 


0.3 




A 


V DS = 10V, V GS = 4.5V 


p 

DS(ON) 


Static Drain-to-Source 
ON-State Resistance 


VN3515 




9.5 


15 


n 


V fiR = 4.5V, l n = 100mA 




17 


35 


V GS = 4.5V, l n = 1 00mA, TA = 1 25°C 


VIM4012 




9.5 


12 


V GS = 4.5V, l D = 100mA 




17 


30 


V GS = 4.5V, l D = 1 00mA, TA = 1 25°C 




Forward Transconductance 


125 


350 




mO 


V DS =15V, l D = 100mA 




Input Capacitance 






90 


PF 


V DS = 25V, V GS = 0V 
f=1MHz 


Coss 


Common Source Output Capacitance 






20 


Crss 


Reverse Transfer Capacitance 






5 


'd(ON) 


Turn-ON Delay Time 






20 


ns 


V CD = 25V 
l D = 100mA 
^GEN = 25H 


tr 


Rise Time 






20 


'd(OFF) 


Turn-OFF Delay Time 






65 


t. 


Fall Time 






65 


V SD 


Diode Forward Voltage Drop 






1.2 


V 


v gs = 0. i sd = 160mA 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300iis pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 

3. See TN06D data sheet for characteristic curves. 




8-104 



Alphanumeric Index and Ordering Information MM 
m*kmki iwki^'- Corporate Profile WM 

Applications Notes WtM 

Quality Assurance and Handling Procedures WiM 

Process Flow 

Selector Guides and Cross Reference 131 

N- and P-Channel Low Threshold MOSFETs Hi 

DMOS N-Channel Discretes §IM 

DMOS P-Channel Discretes Ifl 
DMOS Arrays and Special Functions 

High Voltage Driver/Interface ICs !!■ 

High Voltage Analog Switches and Multiplexers iKfl 

High Voltage Power Supply ICs iKfl 

CMOS Consumer/Industrial Products !&■ 

Surface Mount Packages and Lead Bend Options iM 

Package Outlines ii*M 

Die Specifications itM 

Representatives/Distributors \[lM 



Chapter 9 - DMOS P-Channel Discretes 

VP01A -40, -60, -90V; 8 ohms . 

VP01C -160, -200V; 25 ohms . 

VP03D -350, -400V; 6 ohms ... 

VP03E -450, -500V; 7.5 ohms 

VP0300 -30V, 2.5 ohms 

VP05D -350, -400V; 75 ohms . 

VP05E -450, -500V; 1 25 ohms 

VP06D -350, -400V; 25 ohms . 

VP06E -450, -500V; 30 ohms . 
VP0808/VP1 008 -80, -1 00V; 5 ohms 

VP11A -60, -100V; 2 ohms 

VP1 2A -40, -60, -1 00; 0.8 ohms 

VP13A -40, -60, -1 00V; 25 ohms 

VP21 A -40, -60, -1 00V; 1 2 ohms 

VP22A -40, -60, -100V, 0.9 ohms 



VP01A 




P-Channel Enhancement- 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


^DS(ON) 

(max) 


'd(ON) 

(min) 


Order Number / Package 


TO-39 


TO-52 


TO-92 


TO-220 


Quad P-D1P 


Quad C-DIP* 


DICEt 


-40V 


8£1 


-0.5A 


VP0104N2 


VP0104N9 


VP0104N3 


VP0104N5 


VP0104N6 


VP0104N7 


VP0104ND 


-60V 


8H 


-0.5A 


VP0106N2 


VP0106N9 


VP0106N3 


VP0106N5 


VP0106N6 


VP0106N7 


VP0106ND 


-90V 


an 


-0.5A 


VP0109N2 


VP0109N9 


VP0109N3 


VP0109N5 






VP0109ND 



* 14 pin side brazed ceramic DIP 
t MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C ISS and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 



Applications 



□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, memories, 
displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°CtO+150°C 


Soldering Temperature* 


300°C 


* Distance of 1.6 mm from case for 10 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




14-Lead DIP 




TO-220 



TO-39 



TO-52 



TO-92 



Note 1 : See package outline section for discrete pinouts. 
Note 2: See array section for quad pinouts. 



9-1 



VP01A 



Thermal Characteristics 



Package 


l D (continuous)* 


I D (pulsed) 

@ T c = 25°C 


Power Dissipation 
C/W 


cm 






'□RM 


TO-39 


-0.45A 


-1.0A 


3.5W 


125 


35 


-0.5A 


-1.0A 


TO-52 


-0.25A 


-1.0A 


LOW 


170 


125 


-0.25A 


-1.0A 


TO-92 


-0.25A 


-0.8A 


LOW 


170 


125 


-0.25A 


-0.8A 


TO-220 


-1.0A 


-1.2A 


15.0W 


70 


8.3 


-1.0A 


-1.2A 


Plastic DIP 


Refer to Arrays & Special Functions Section. 


Ceramic DIP 



* l D (continuous) is limited by max rated Tj, 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 


VP0109 


-90 












Breakdown Voltage 


VP0106 


-60 






V 


l D = -1.0mA, V GS = 0V 




VP0104 


-40 








V GS(th) 


Gate Threshold Voltage 


-1.5 




-3.5 


V 


V G s = V D s. l D = -10mA 


AV GS(th) 


Change in V GS(th) with Temperature 




5.8 


6.5 


mV/°C 


l D = -1.0mA, V GS =V 0S 


'gss 


Gate Body Leakage 




-1.0 


-100 


nA 


V GS = ±20V, V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






-10 


uA 


V GS = 0V, V DS = Max Rating 












-1 


mA 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 125°C 


'D(ON) 


ON-State Drain Current 




-u.io 






A 


V GS = " bV ' V DS = "" V 








-0.50 


-1.2 




V GS = -10V,V DS = -25V 


R DS(ON) 


Static Drain-to-Source 






11 


15 




V GS = -5V, l D = -0.1A 




ON-State Resistance 






6 


8 




V GS = -10V, l D = -0.5A 


AR DS(ON) 


Change in R D s(on) witn Temperature 




0.55 


1.0 


%/°C 


l D = -0.5A, V GS = -10V 


Gfs 


Forward Transconductance 


150 


190 




mU 


V DS = -25V, l D = -0.5A 


Ciss 


Input Capacitance 




45 


60 




V GS = 0V, V DS = -25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




22 


30 


PF 


C RSS 


Reverse Transfer Capacitance 




3 


8 




'dION) 


Turn-ON Delay Time 




4 


6 




V DD = -25V 
l D = -0.5A 
R GEN = 25Q 


tr 


Rise Time 




7 


10 




'd(OFF) 


Turn-OFF Delay Time 




3 


7 


ns 


ti 


Fall Time 




4 


10 




v SD 


Diode Forward Voltage Drop 




-1.2 


-2.0 


V 


l SD = -1.0A, V GS = 0V 


trr 


Reverse Recovery Time 




400 




ns 


l SD = -1.0A, V GS = 0V 



Notes: 

1 . All D.C. parameters 100% tested at 25°C unless otherwise stated. {Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




Typical Performance Curves 



Output Characteristics 



Saturation Characteristics 











































































v 




10V 












- 






































































i 

























































-20 -30 

V DS (volts) 



-1.0 



(0 -0.4 



-4 -6 

V DS (volts) 















v 


3S=" 


10V 























































































































































































































-10 



Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



« 100 



I I I 

_V DS =-25V_ 






T A = -55°C 
















I 

T A = 25°C _ 


















I I I 






i 










lA = 








If 





















































































































-0.2 



-0.4 -0.6 

l D (amperes) 



-0.8 



CO 

3 

Q 10 
0- 







































TO-22 





























































TO-39 










~TO-92 











25 SO 75 100 125 150 

T C (°C) 



Maximum Rated Safe Operating Area 



Thermal Response Characteristics 



i 



















































































































TO-220 (pulsed) 

hi rrrt-- 




























\ 










-J 












































TO-39(DC) 












s 








\ 


T( 




(D( 


3) 








N 


s 

























































































































































-1.0 -10 

V DS (volts) 



-100 



£ 0.8 

1 
o 

S 0.6 
CD 
Q 
C 
CO 

si? 

CO 0.4 
CD 

cc 
"5 



TO-220 
" P D = 15 
"T c =25" 








A/ 

C 








































TO-39 








P w = 3.5W 






T C =2 


5°C 











0.001 0.01 0.1 1 

t p (milliseconds) 



9-3 



VP01A 



Typical Performance Curves 

BV DSS Variation with Temperature 




100 150 



Transfer Characteristics 



| -0.6 













T A 


= -55°C \J / 


J 

/ 






> =- 


15V 




= 2 


5°C : 






/ 












/ 


























































T A = 


125° 


C _ 













































































-2 -4 -6 -8 -1 

V GS (volts) 
Capacitance vs. Drain-to-Source Voltage 



O 









f= 1MHz 
















Ciss 








- Coss — 








Crss 



-10 -20 -30 

V DS (volts) 



-40 



On-Resistance vs. Drain Current 



J 30 

g 
I 

























\ 


'gs 


= -5\ 


r 


















Vgs 


= -1 


OV " 













































































































































-0.3 -0.6 -0.9 -1.2 -1.5 

Id (amperes) 
V( th) and R D s Variation with Temperature 



> 























FtDS(ON)® -10V, -0.5A-, 


\ 






— I — I — I — I — 

RdS(ON)® -5V, 0.1A— \ 






















h)@" 


1.0mA 























































































50 
TjPC) 



100 150 



Gate Drive Dynamic Characteristics 





























Vos =- 


OV 




































70 p 


F > 




f v DS = 


-40\ 


































7C 


pF" 




















































45dF 

































0.2 0.4 0.6 0.8 1.0 

Q G (nanocoulombs) 



9-4 



VP01C 



1 



P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BVqqs 


"dS(ON) 

(max) 


If 


Order Number / Package 


TO-39 


TO-92 


TO-220 


DICE* 


-160V 


25£2 


-100mA 


VP0116N2 


VP0116N3 


VP0116N5 


VP0116ND 


-200V 


250 


-100mA 


VP0120N2 


VP0120N3 


VP0120N5 


VP0120ND 



^MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 
n Ease of paralleling 

□ Low C, sg and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, memories, 
displays, bipolar transistors, etc.) 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 



Absolute Maximum Ratings 


Drain-to-Source Voltage 


BV DSS 


Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 




TO-220 



TO-39 



TO-92 



Note: See package outline section for discrete pinouts. 



* Distance of 1 .6 mm from case for 10 seconds. 



It] 



9-5 



VP01C 



Thermal Characteristics 



Parkanp 


'd (continuous)* 




Power Dissipation 
@ T c = 25°C 


$. 

c/w 


c/w 


1 * 

OR 


'drm 


TO-39 


-0.2A 


-0.65A 


3.5W 


125 


35 


-0.2A 


-0.65A 


TO-92 


-0.1 A 


-0.35A 


LOW 


170 


125 


-0.1 A 


-0.35A 


TO-220 


-0.425A 


-1.0A 

' ' 


15.0W 


70 


8.3 


-0.425A 


-1.0A 


* l D (continuous) is limited by max rated Tj. 















Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


1 In it 

unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VP0120 


-200 






V 




I D = -1.0mA, V GS = 0V 


VP0116 


-loU 


^GS(th) 


Gate Threshold Voltage 


-1.5 




-3.5 


V 


V G s = V DS , l D = -1.0mA 


A V GS(th ) 


Change in V GS(m) with Temperature 




6.0 




mV/°C 


l D = -1.0mA, V GS =V DS 


'gss 


Gate Body Leakage 






-100 


nA 


V GS = ±20V, V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






-10 


uA 


V GS = 0V, V DS = Max Rating 


-1 


mA 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 1 25°C 


'd(ON) 


ON-State Drain Current 


-100 


-400 




mA 


V GS = -5V, V DS = -25V 


-350 


-750 


V GS = -10V, V DS = -25V 


^DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




25 


40 


Q 


V GS = -5V, l D = -50mA 


15 


25 


V GS = -10V, l D = -100mA 


a Rdsion) 


Change in R DS(0 n) witn Temperature 




0.6 




%/°C 


l D = -100mA, V GS = -10V 


G FS 


Forward Transconductance 


50 


70 




mU 


V DS = -25V, l D = -100mA 


C ISS 


Input Capacitance 




50 


60 


PF 


v gs = ov . V ds = - 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




10 


30 


Crss 


Reverse Transfer Capacitance 




5 


10 


'd(ON) 


Turn-ON Delay Time 




4 


10 


ns 


V DD = -25V 
l D = -350mA 

R GEN = 25£i 


t, 


Rise Time 




4 


10 


td(OFF) 


Turn-OFF Delay Time 




4 


10 


tf 


Fall Time 




4 


11 


v SD 


Diode Forward Voltage Drop 




-1.0 




V 


\ SD = -0.5A, V GS = 0V 


trr 


Reverse Recovery Time 




500 




ns 


l SD = -0.5A, V GS = 0V 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




Typical Performance Curves 





9-7 



VP01C 



Typical Performance Curves 

BV DSS Variation with Temperature 




100 150 



On-Resistance vs. Drain Current 



o 

eg 40 



























v G 


s = 


5V 


















































































* V 


GS = 


-10 


/ 



















































































-0.3 -0.6 -0.9 -1.2 -1.5 

Id (amperes) 



Transfer Characteristics 



V(, h) and R D s Variation with Temperature 



!S -0.6 

i 

CL 

e 

CO 



-0.2 



V DS = -25V 












4 

t 








T 


A = 


55°( 






4 


/ 














fy 




/ 

/ 










T A 


= 25 






' 4 
t 


! 
















f 4 


f 

! 


















/ 

./ 




















T A 


=125 


°c 





























































0-2-4-6-8 

V GS (volts) 



-10 



CO 

E 

S 1.0 



> 





I 


@ -1( 


IV, -1( 


)0mA- 










>S(ON 


















































-5V, -! 


)0mA 










"•dSCON) w 






















V 


(th)@ 


-1.0mA > 







































0.8 g 
03 
Q 
DC 

0.4 



50 
Tj(°C) 



100 150 



Capacitance vs. Drain-to-Source Voltage 



Gate Drive Dynamic Characteristics 



o 
o 
a. 

O 









f = 1MHz 














C ISS 














Crss 


C ss 



-10 -20 -30 

V DS (volts) 



j2 '6 

o 



> 

































Vds = 


-10V . 


































100 


PF / 






















'OS 


= -4 


JV- 


























10C 


PF 




























f 




50dF 
















I I 















0.2 0.4 0.6 0.8 1.0 

Q G (nanocoulombs) 



Q ft 
a O 



VP03D 




P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


RdS(ON) 

(max) 


'd(ON) 

(min) 


Order Number / Package 


TO-3 


TO-39 


TO-220 


DICE* 


-350V 


60 


-1.5A 


VP0335N1 


VP0335N2 


VP0335N5 


VP0335ND 


-400V 


6£J 


-1.5A 


VP0340N1 


VP0340N2 


VP0340N5 


VP0340ND 



"•"MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C lss and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 



Applications 



□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, memories, 
displays, bipolar transistors, etc.) 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto +150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 10 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




TO-3 




TO-39 



TO-220 



Note: See package outline section for discrete pinouts. 



VP03D 



Thermal Characteristics 



Package 


l D (continuous)* 


I D (pulsed) 


Power Dissipation 
@ T c = 25°C 


crw 


CAV 


I * 
■dr 


'drm 


TO-3 


-2.7A 


-5.0A 


100W 


1.25 


300 


-2.7A 


-5.0A 


TO-39 


-0.7A 


-5.0A 


6W 


20.8 


125 


-0.7A 


-5.0A 


TO-220 


-1.6A 



-5.0A 


50W 

' 


2.5 


40 


-1.6A 


-5.0A 



* l D (continuous) is limited by max rated Tj. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VP0340 


-400 






V 


V G s = 0V . I D = -10mA 


VP0335 


-350 


^GS(th) 


Gate Threshold Voltage 


-2.5 




-4.5 


V 


v gs = v ds. b = -1 0mA 


AVQS(th) 


Change in V GS „ M with Temperature 




4.8 


6.0 


mV/°C 


l D = -1.0mA, V es = V DS 


Iqss 


Gate Body Leakaqe 






-100 


nA 


V GS = ±20V, V DS = 0V 




Zero Gate Voltage Drain Current 

I 






-200 


uA 


V GS = 0V, V DS = Max Rating 




mA 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 125°C 


'□(ON) 


ON-State Drain Current 




-1.0 




A 


V GS = -5V, V DS = -25V 


-1.5 


-3.5 


V GS = -10V, V DS = -25V 




Static Drain-to-Source 
ON-State Resistance 




6 




£2 


V GS = -5V, l D = -50mA 


4.5 


6 


V GS = -10V, l D = -100mA 


A RdS(ON) 


Change in R DS(0 n) witn Temperature 




0.7 


1.2 


%/°C 


l D = -100mA, V GS = -10V 


Gfs 


Forward Transconductance 


0.5 


0.8 




15 


V DS = -25V, l D = -100mA 


Ciss 


Input Capacitance 




550 


700 


PF 


v gs = 0V . v ds = - 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




90 


120 


Crss 


Reverse Transfer Capacitance 




20 


50 


'd(ON) 


Turn-ON Delay Time 




25 


40 


ns 


V DD = -25V 
l D = -1A 
R G EN=10£i 


t, 


Rise Time 




25 


40 


'd(OFF) 


Turn-OFF Delay Time 




65 


110 


tf 


Fall Time 




20 


40 


V SD 


Diode Forward Voltage Drop 




-1.0 


-1.3 


V 


l SD = -0.5A, V GS = 0V 


trr 


Reverse Recovery Time 




500 




ns 


l SD = -0.5A, V GS = 0V 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




Typical Performance Curves 

Output Characteristics 













1 


1 

v G s= 


1 

= -10\ 






















-8V 






















































































-6V 












































































-4V 












1 







-10 -20 -30 -40 -50 

V DS (volts) 
Transconductance vs. Drain Current 























\ 




= -2£ 


V 
















































T A = 


-55 


•C- 




































£- 










T A = 


25° 


C 




\ 












T A = 


125 


°C 































































-0.5 -1.0 -1.5 -2.0 -2.5 

l D (amperes) 
Maximum Rated Safe Operating Area 



-0.01 



I I I 


le 






















_. TC"i_oon 






















■ - I- + -i f 


ed) - 
































T( 


)-3 


DC 


) 






















































s 


s 












- TO-220 (DC 


n 




K 
























T( 


1 1— f- 

3-39 (DC 














































s 





























































































































































































-10 -100 

V DS (volts) 



-1000 



Saturation Characteristics 



§ -0.8 



































1 




ov 
















-81 

























-6V 












































































































-4V 



















0-2-4-6-8 -11 

V DS (volts) 
Power Dissipation vs. Case Temperature 



5S 
I 

s 



TO-3 X 














































TO-2, 


>0 


























































1 











25 50 75 100 125 150 
T C (°C) 

Thermal Response Characteristics 



CD 




0.01 0.1 

tp (seconds) 



9-11 



Typical Performance Curves 

BV DSS Variation with Temperature 




On-Resistance vs. Drain Current 



o 



□ 
rr 



























v G s 


= -5V 
























5S = 


-10V 





















































































































































-1.5 -3.0 -4.5 -6.0 -7.5 

l D (amperes) 



Transfer Characteristics 



V(, h) and R DS Variation with Temperature 



8 -3.0 

I 

E 


















= -5! 




°C 












>5V 




= 2 


















T, 


5°C- 






4 

/ 


















/ 


/ — 
















4 








































Ta = 


25° 


C 































































-2-4-6-8-11 
V GS (volts) 

Capacitance vs. Drain-to-Source Voltage 



2 

•§ 500 









f = 1MHz 




Ciss 
















c oss 








Crss 







-10 -20 -30 

V DS (volts) 



> 





















































V (th) 


8 -10 


mA 














































^DSfC 
^DSfC 


N)@ 
N)@ 


5V, -( 
10V, 


).25A 
-0.5A 







































;o 50 100 150 

Tj(°C) 

Gate Drive Dynamic Characteristics 



-10 



> 



























Vds =- 


10V 










































Vds = 


-40V 






























M3 
































I 








































r i i 

















4 8 12 16 20 

Q G (nanocoulombs) 



9-12 



© 



VP03E 



P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


Rds<on) 
(max) 


If 


Order Number / Package 


TO-3 


TO-39 


TO-220 


DICE* 


-450V 


7.50 


-1A 


VP0345N1 


VP0345N2 


VP0345N5 


VP0345ND 


-500V 


7.5C1 


-1A 


VP0350N1 


VP0350N2 


VP0350N5 


VP0350ND 



* MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C ISS and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, memories, 
displays, bipolar transistors, etc.) 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


r 20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




TO-39 



Note: See package outline section for 



9-13 



VP03E 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 






'dr 


'drm 








@ T c = 25°C 


c/w 


C/W 






TO-3 


-1.5A 


-3.0A 


100W 


1.25 


30 


-1.5A 


-3.0A 


TO-39 


-0.4A 


-3.0A 


6W 


20.8 


125 


-0.4A 


-3.0A 


TO-220 


-1.0A 


-3.0A 


50W 


2.5 


40 


-1.0A 


-3.0A 



* l (continuous) is limited by max rated T. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


^^DSS 


Drain-to-Source 


VP0350 


-500 






V 


v gs=°. l D =-10mA 




Breakdown Voltage 


VP0345 


-450 






V G sth 


Gate Threshold Voltage 


-2.5 




-4.5 


V 


V r<! = V n =, In = -10mA 

IjO Uo' u 




Change in V GS(th) with Temperature 




4.8 


6.0 


mV/°C 


Vgs = V ds . Id = "10mA 


^GSS 


Gate Body Leakage 






-100 


nA 


V GS = +20V. V DS = 0V 




Zero Gate Voltage Drain Current 






-200 


uA 


Vr-o = 0V, V n <! = Max Ratinq 












-2 


mA 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 






-1.5 




A 


V GS = -5V, V DS = -25V 








-1.0 


-3.0 






V GS = -10V, V DS = -25V 


^DS(ON) 


Static Drain-to-Source 






6.0 






V GS = -5V, l D = -0.25A 




ON-State Resistance 






5.5 


7.5 


V GS = -10V, l D = -0.25A 


ARdS(ON) 


Change in R ds(0 n) with Temperature 




0.7 


1.2 


%/°c 


V GS = -10V, l o =-0.25A 




Forward Transconductance 


0.25 


0.45 




u 


V DS = -25V, l D = -0.5A 


C ISS 


Input Capacitance 




720 


800 






Coss 


Common Source Output Capacitance 




110 


130 


PF 


V gs = V . V DS = -25V 
f = 1 MHz 


Crss 


Reverse Transfer Capacitance 




20 


50 




'd(ON) 


Turn-ON Delay Time 




11 


30 






t, 


Rise Time 




11 


30 




V DD = -25V 
l D = -1A 

R GEN = ion 


'd(OFF) 


Turn-OFF Delay Time 




70 


100 


ns 


If 


Fall Time 




22 


30 




V SD 


Diode Forward Voltage Drop 




-1.0 


-1.3 


V 


V GS = OV, l SD = -0.25A 


»rr 


Reverse Recovery Time 




550 




ns 


V GS = 0V, l SD = -0.25A 



Notes: 

1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




VP03E 



Typical Performance Curves 

Output Characteristics 





































5S=- 


OV 








































-7V 




































-6V 




































-5V 




































-4V 





















-10 -20 -30 -40 -50 

V DS (volts) 



Saturation Characteristics 



I -0.8 



































V 


GS = 


10V 

















































































































































































-8V 
-6V 
-5V 



-4 -6 -8 

V DS (volts) 



-10 



Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



ffi 0.4 

o 



o 































25V 
















































-55 


C 














T A = 25° C 














T A = 150 


°c 






1 












— • 


p — 
























i 









































-0.5 -1.0 -1.5 -2.0 

l D (amperes) 



100 



1 



-TO-3 














































TO-2, 


?0 














































_TO-3S 























25 50 75 100 125 150 

T C (°C) 



Maximum Rated Safe Operating Area 



Thermal Response Characteristics 



-0.01 

































































TO- 


22C 


{ 





jlsed 

- 






















-I- H> 

TO-3 (DC) 










































I I I I 






TO-220 (D 
















+ 






C) 








































TO-39 IDC1 ^ 























































































































































































































-10 -100 

V DS (volts) 



^ 0.8 
(0 

E 



CC 

"3 
I 





0.001 





I 

TO-220 






P D =50W j 






T A =2 


5°C X 










































'0-39 






^ F 


'p = 6W 
"C=25°C- 






1 



0.01 0.1 

t p (seconds) 



9-15 



Typical Performance Curves 

BV DS s Variation with Temperature 




100 150 



Transfer Characteristics 



"q -20 























V 


DS = 


-25\ 


/ 


























■ 

— ti 
























V 




































* 4 
- ✓ 

e — 


> 
















* 

* 

































































-2 -4 -6 -8 -10 

V GS (volts) 
Capacitance vs. Drain-to-Source Voltage 



o 







f = 1MHz 








C ISS 
























Coss 






Crss 





On-Resistance vs. Drain Current 



20 



o, 
g 

co 8 
D 























v G 


s ■- 


5V 






^GS 


= -1 


JV 



































































































































































3 -1.0 -2.0 -3.0 -4.0 -5.0 

l D (amperes) 
V (th ) and Rpg Variation with Temperature 



1.1 

I 

a 1.0 

I 
o 

I 0.9 

CO 





I I I I 

Rrvwrwi® -10V. -0.25A > 






I I I 










~ V 


(th)W 


-lum 



























































































































50 100 

Tj(°C) 

Gate Drive Dynamic Characteristics 



1 



>° "4 





















































v D s 




ov 
































8 


00 pF y 






















v D 


s = - 


40V 














800 


pF 


















































00 p 


F 

















-10 -20 -30 -40 

V DS (volts) 



2 4 6 8 10 

Q G (nanocoulombs) 



9-16 



VP0300 




P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


"dS(ON) 


'd(ON) 


Order Number / Package 


BV DGS 


(max) 


(min) 


TO-39 


TO-92 


-30V 


2.5£2 


-1.5A 


VP0300B 


VP0300L 



High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C lss and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 
U Amplifiers 

□ Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, memories, 
displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±30V 


Operating and Storage Temperature 


-55°C tO+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 10 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertax's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 



II 



Package Options 




9-17 



VP0300 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 


9a 










T c = 25°C 


°CAV 


CAV 


TO-39 


-1.25A 


-3.0A 


6.25W 


125 


20 


TO-92 


-0.32A 


-0.87A 


LOW 


170 


41 



* l D (continuous) is limited by max rated T . 



Electri 


Cal Characteristics (@ 25°C unless otherwise specified) 


Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 




Drain-to-Source Breakdown Voltage 


-30 






V 


V GS = 0V, l D =-10nA 


^GS(th) 


Gate Threshold Voltage 


-1.0 


-1.8 


-4.5 


V 


V GS = V DS , l D = -1mA 


l G SS 


Gate Body Leakage 






-100 


nA 


V GS = ±30V, V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






-10 


uA 


V GS = 0V, V DS = -25V 


-500 


V GS = 0V, V DS = -25V 
T A = 125°C 


b(ON) 


ON-State Drain Current 


-1.5 


-1.7 




A 


V GS = -12V, V DS = -10V 


R DS(ON) 


Static Drain-to-SourceON-State Resistance 






2.5 


Q 


V GS = -12V, l D = -1A 


Gfs 


Forward Transconductance 


200 






mt5 


V DS = -10V, l D = -0.5A 


Ciss 


Input Capacitance 






150 


pF 


V GS = 0V, V DS = -15V 
f = 1MHz 


c oss 


Common Source Output Capacitance 






120 


c rss 


Reverse Transfer Capacitance 






60 


'(ON) 


Turn-ON Time 






30 


ns 


V DD = -25V, l D = -1A 
R G EN = 25ii 


'(OFF) 


Turn-OFF Time 






30 


V S D 


Diode Forward Voltage Drop 




-1.2 




V 


V GS = 0V, l SD = -1.5A 



Notes 

1. All D.C. parameters 1 00% tested at 25"C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




9-18 



VP05D 




P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


"ds<on) 
(max) 


'd(ON) 

(min) 


Order Number / Package 




TO-39 


TO-92 


DICE+ 


-350V 


75Q 


-200mA 


VP0535N2 


VP0535N3 


VP0535ND 


-400V 


750 


-200mA 


VP0540N2 


VP0540N3 


VP0540ND 



* MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C ISS and fast switching speeds 

□ Excellent thermal stability 

C Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

Motor control 

□ Converters 
i Amplifiers 

□ Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, memories, 
displays, bipolar transistors, etc.) 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching s 



Package Options 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV OGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 




9-19 



VP05D 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 








'drm 








@ T c = 25°C 


c/w 


-c/w 






TO-39 


-0.2A 


-0.5A 


3.5W 


35 


125 


-0.2A 


-0.5A 


TO-92 


-0.1 A 


-0.5A 


LOW 


125 


170 


-0.1 A 


-0.5A 



* l D (continuous) is limited by max rated T ( 



Electrical Characteristics 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 




BV„,-„ 

DV DSS 


Drain-to-Source 
Breakdown Voltage 


VP0540 


-400 






V 


V QS =0V, l D =-1mA 


VP0535 


-350 


v GS(th) 


Gate Threshold Voltage 


-2.5 




-4.5 


v 


V„,- - V„„ U - -1 mA 
V GS — V DS> 'D — '*' tn 


A VgS(»i) 


Change in V GS( , h) with Temperature 




3.5 


6.0 


mV/°C 


v gs = v ds. l D = -1mA 


1 

'GSS 


Gate Body Leakage 






-100 


nA 


V GS = ±20V, V DS = 0V 


1 

'dss 


Zero Gate Voltage Drain Current 






-10 


uA 


v qq — uv, "dS — ' Vlc *^ ndiiiiy 


-F;nn 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 




-80 




mA 


V GS = -5V, V DS = -25V 


-200 


-350 




V GS = -10V, V DS = -25V 


^DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




60 




£2 


V GS = -5V, l D = -10mA 


45 


75 


V GS = -10V, l D = -50mA 


AR DS(ON) 


Change in R DS (on) witn Temperature 




0.8 


1.5 


%/°C 


V GS = -10V, l D =-50mA 


G FS 


Forward Transconductance 


50 


70 




mU 


V DS = -25V, l D = -50mA 




Input Capacitance 




40 


60 


pF 


V GS = 0V, V DS = -25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




11 


20 


Crss 


Reverse Transfer Capacitance 




3 


5 


td(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = -25V 
l D = -200mA 
Rgen = 25H 


t, 


Rise Time 






10 


td(OFF) 


Turn-OFF Delay Time 






15 


tf 


Fall Time 






15 


V SD 


Diode Forward Voltage Drop 




-0.8 


-1.5 


V 


V GS = 0V, l SD = -0.1A 


trr 


Reverse Recovery Time 




200 




ns 


V GS = 0V, l SD = -0.1A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




Typical Performance Curves 

Output Characteristics 















V 


1 

3S="10V 




























































-8V 














































































-6V 




































-4V 







































-10 -20 -30 -40 -50 

V DS (volts) 



VP05D 

Saturation Characteristics 



co 
S? 

o -o.i 

Ct 
E 

CO 















V 


GS = 


10V 




























































-6V 


































































































































I 





-2 -4 -6 

V DS (volts) 



Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



E 

w 

Li- 
es 



v D s =■ 


25V 


























Ta = 


-55 


•c 
































Ta = 


25° 


C 


















































t a = 


150 


°C 



























































-0.15 

l D (amperes) 
Maximum Rated Safe Operating Area 



-0.1 

CO 

p 



1 1 1 — r-i 

~~ TO-39 (pulsed) 










































• - 


















V 






































TO- 


39(DC 






















1 1 ll\ 












































" t -c 




-* 









































































































































































































































-10 -100 -1000 

V DS (volts) 



























TO-3E 

































































































25 50 75 100 125 150 

T C (°C) 

Thermal Response Characteristics 



CO 

1 
o 

f t 

i 

g 0.4 

rr 
ro 
E 























































TO-39 








P D =3.5W 






T C =25 


C 











0.001 0.01 0.1 

tp (seconds) 



9-21 



Typical Performance Curves 



BV DSS Variation with Temperature On-Resistance vs. Drain Current 




V GS (volts) Tj(°C) 



Capacitance vs. Drain-to-Source Voltage Gate Drive Dynamic Characteristics 




V DS (volts) Q G (nanocoulombs) 



9-22 



VP05E 




P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


"dS(ON) 

(max) 


'd<on) 
(min) 


Order Number / Package 


BVdgs 


TO-39 


TO-92 


DICE+ 


-450V 


i25n 


-100mA 


VP0545N2 


VP0545N3 


VP0545ND 


-500V 


125£2 


-100mA 


VP0550N2 


VP0550N3 


VP0550ND 



* MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C lss and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 
Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, memories, 
displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°C to +1 50°C 


Soldering Temperature* 


300°C 


* Distance of 1.6 mm from case for 10 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



1!J 



Package Options 




9-23 



VP05E 



Thermal Characteristics 



Package 


l (continuous)* 


l D (pulsed) 


Power Dissipation 


9c 






'drm 








@ T c = 25°C 


cm 


CAW 






TO-39 


-125mA 


-0.25A 


3.5W 


35 


125 


-125mA 


-0.25A 


TO-92 


-70mA 


-0.25A 


1W 


125 


170 


-70mA 


-0.25A 



* l D (continuous) is limited by max rated T. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VP0550 


-500 






V 


V r o = 0V, l n = -1mA 


VP0545 


-450 


^GS(th) 


Gate Threshold Voltage 


-2.5 




-4.5 


V 


V GS = V DS. b = " 1 mA 


AV GS(th) 


Change in V GS(tfl) with Temperature 




3.5 


6 


mV/°C 


V G s = v ds. 'd -"-1mA 


'gss 


Gate Body Leakage 






-100 


nA 


V GS = ±20V, V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






-10 


uA 


V GS = 0V, V DS = Max Rating 


-1000 


V G s = 0V, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 




-90 




mA 


V GS = -5V, V DS = -25V 


-100 


-240 


V GS = -10V, V DS = -25V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




85 




a 


V GS = -5V, l D = -5mA 


80 


125 


"gs = -10V, l D = -10mA 


AR DS(ON) 


Change in R DS (on) with Temperature 




0.85 




%/°c 


V GS = -10V, l D = -10mA 


G FS 


Forward Transconductance 


25 


40 






V DS = -25V, l D = -10mA 


C|SS 


Input Capacitance 




40 


60 


PF 


V GS = 0V, V DS = -25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




10 


20 


Crss 


Reverse Transfer Capacitance 




3 


10 


'd(ON) 


Turn-ON Delay Time 




5 


10 


ns 


V DD = -25V 
l D = -100mA 
Rgen = 25i2 


V 


Rise Time 




8 


10 


'd(OFF) 


Turn-OFF Delay Time 




8 


15 


t, 


Fall Time 




5 


16 


V SD 


Diode Forward Voltage Drop 




-0.8 


-1.5 


V 


V GS = 0V, l SD = -0.1A 


V, 


Reverse Recovery Time 




200 




ns 


V GS = 0V, l SD = -0.1A 



Notes: 

1. All D.C. parameters 100% tested at 25^0 unless otherwise stated. (Pulse test: 300u.s pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




Typical Performance Curves 



Output Characteristics 



VP05E 



Saturation Characteristics 






9-25 



Typical Performance Curves 



BV DSS Variation with Temperature 



On-Resistance vs. Drain Current 



200 



o 

to 80 
Q 
DC 



V GS =-5V 



V GS =-10V 




9-26 



jfi) Supertexinc. 



VP06D 




P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV TCS 


R DS(ON) 

(max) 


'd(ON) 

(min) 


Order Number / Package 


TO-39 


TO-92 


TO-220 


DICE* 


-350V 


25fi 


-0.4A 


VP0635N2 


VP0635N3 


VP0635N5 


VP0635ND 


-400V 


25a 


-0.4A 


VP0640N2 


VP0640N3 


VP0640N5 


VP0640ND 



* MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 
Low power drive requirement 

C Ease of paralleling 

□ Low C ISS and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, memories, 
displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°C to+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertax's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




VP06D 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 

@ T c = 25°C 


3c 

c/w 


3a 
C/W 


1 * 

DR 


IqrM 


TO-92 


-0.30A 


-0.6A 


1W 


125 


170 


-0.30A 


-0.6A 


TO-39 


-0.40A 


-0.75A 


6W 


21 


125 


-0.40A 


-0.75A 


TO-220 


-0.40A 


-0.75A 


28W 


2.7 


70 


-0.40A 


-0.75A 



* 1 D (continuous) is limited by mAx rated T. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Cwmknl 

oy ihdoi 


Parameter 


Min 


Typ 


Mav 


1 In it 
(JIM I 




R\/ 

BV DSS 


Drain-to-Source 
Breakdown Voltage 


VP0640 


Ann 






V 


V GS = 0V, l D = -2mA 


VP0635 


-350 


v GS(th) 


Gate Threshold Voltage 


o 
-c. 




A 


V 


V GS = V DS , l D = "2mA 


AW 

flv GS(th) 


Change in V GS(th) with Temperature 






A Q 

4,o 


mV/°C 


V GS = V DS . b = "2mA 


'gss 


Gate Body Leakage 






-1UU 


r> A 


V GS = ±20v, V DS = UV 


1 

'dss 


Zero Gate Voltage Drain Current 






-1 


uA 


V GS = 0V, V DS = Max Rating 


-1 


mA 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 125°C 


In(ON) 


ON-State Drain Current 




-0.2 




A 


V GS = -5V, V DS = -25V 


-0.4 


-1.1 


V GS = -10V, V DS = -25V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




20 




a 


V GS = -5V, l D = -100mA 


19 


25 


V GS = -10V, l D = -100mA 


AR DS(ON) 


Change in R ds(c ,n) wi * n Temperature 






0.75 


%/°c 


V GS = -10V, l D = -100mA 


G FS 


Forward Transconductance 


100 






mU 


V DS = -25V, l D = -100mA 


C !SS 


Input Capacitance 




105 


145 


PF 


V GS = 0V, V DS = -25V 
t = 1 MHz 


C SS 


Common Source Output Capacitance 




30 


75 


Crss 


Reverse Transfer Capacitance 




10 


20 


tdfON) 


Turn-ON Delay Time 






10 


ns 


V DD = -25V 
l D = -400mA 
R G en = 250 


tr 


Rise Time 






10 


'd(OFF) 


Turn-OFF Delay Time 






20 


tf 


Fall Time 






10 


v SD 


Diode Forward Voltage Drop 






-1.8 


V 


V GS = 0V, l SD = -100mA 


tr, 


Reverse Recovery Time 




300 




ns 


V GS = 0V, l SD = -100mA 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300mu.s pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




9-28 



Typical Performance Curves 

Output Characteristics 



VP06D 



Saturation Characteristics 





9-29 



Typical Performance Curves 




VP06E 



1 



P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BVoss/ 


RoS<ON) 

(max) 


If 


Order Number / Package 


TO-39 


TO-92 


TO-220 


DICEt 


-450V 


30Q 


-0.2A 


VP0645N2 


VP0645N3 


VP0645N5 


VP0645ND 


-500V 


30Q 


-0.2A 


VP0650N2 


VP0650N3 


VP0650N5 


VP0650ND 



T MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C lss and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, memories, 
displays, bipolar transistors, etc.) 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 




TO-220 



TO-39 



TO-92 



Note: See package outline section for discrete pinouts. 



9-31 



VP06E 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 




3a 


I * 
■dr 


'drm 








@ T c = 25°C 


°c/w 


°c/w 






TO-92 


-0.1 A 


-0.3A 


1W 


125 


170 


-0.1 A 


-0.3A 


TO-39 


-0.25A 


-0.5A 


6W 


21 


125 


-0.25A 


-0.5A 


TO-220 


-0.25A 


-0.5A 


45W 


2.7 


70 


-0.25A 


-0.5A 



* l D (continuous) is limited by max rated TV. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Tvd 


Max 


Unit 


Conditions 


^^DSS 


Drain-to-Source 
Breakdown Voltage 


VP0650 


-500 






V 


V GS = 0V, l D = -2mA 


VP0645 


-450 


*GS(th) 


f^atp Thrp^hnlH Vnltanp 
vjciic I I If Col ivjivj v wi iciyc; 


-2 




-4 


V 


V GS = V DS . Id = "2mA 


A\/ 

AV GS(th) 


oiidnyfc) Hi v G s(th) wild i cm i ipfcM diuiy 






-4.8 


mV/°C 


v gs = v ds. b = " 2mA 


'gss 


i—ldlU DUUy l_iddr\dyti 






-100 


nA 


u„„ - +20V V„„ - OV 

v GS — v i v DS — " v 


'DSS 


Vprci fifltp Vnltanp Drain Cnrrpnt 






-10 


MA 


V GS = 0V, V DS = Max Rating 


-1 


mA 


V GS = 0V, V DS = 0.8 Max Rating 
T A =125°C 


'd(ON) 


ON-State Drain Current 




-200 




mA 


V GS = -5V, V DS = -25V 


-200 


-700 


V GS = -10V, V DS = -25V 


^DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




27 




Q 


V GS = -5V, l D = -100mA 


22 


30 


V GS = -10V, l D = -100mA 


A RdS(ON) 


Change in R DS (on) witn Temperature 






0.75 


%/°C 


V GS = -10V, l D = -100mA 


G FS 


Forward Transconductance 


50 


125 




mU 


V DS = -25V, l D = -100mA 


C|SS 


Input Capacitance 




95 


130 


PF 


V GS = 0V, V DS =- 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




50 


75 


C RSS 


Reverse Transfer Capacitance 




10 


20 


l d(ON) 


Turn-ON Delay Time 






10 


ns 


V DD = -25V 
l D = -200mA 
R GEN = 25ii 


t, 


Rise Time 






10 


l d(OFF) 


Turn-OFF Delay Time 






20 


t, 


Fall Time 






15 


V SD 


Diode Forward Voltage Drop 






-1.8 


V 


Vgs = 0V, l SD = -50mA 


i„ 


Reverse Recovery Time 




300 




ns 


V GS = 0V, l SD = -50mA 



Notes: 

1. All D.C. parameters 100% tested at25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 



INPUT 



OUTPUT 




Typical Performance Curves 

Output Characteristics 



Q. 

E 
to 























































v 




10V 








































-8V 




































-6V 






































-4V 



















-10 -20 -30 -40 -50 

V DS (volts) 
Transconductance vs. Drain Current 



E 

a 

























fos 


= -2£ 


V 




























T A = 


-55 


>C 
































T A = 25°C 
















T A = 


125 






















f 
















t 


f 





































-0.1 -0.2 -0.3 -0.4 -0.5 

l D (amperes) 
Maximum Rated Safe Operating Area 



-0.01 



-0.001 



I I I I I I 

TO-39 (Dulsedl 




1 




















3-; 


20 (D 
















T 


C) 










TO- 
U 


39 (D 


:> 














TO-92 (DC) 








































































- 



















































































































-10 -100 

V DS (volts) 



Saturation Characteristics 



VP06E 



£ 

I -0.2 



































v 




10V 








































-6V 












































































-4V 













































V DS (volts) 
Power Dissipation vs. Case Temperature 



i 
s 



TO-2: 


>0 






























































































TO-3E 












TO-92 











25 50 75 100 125 150 

T C (°C) 

Thermal Response Characteristics 



S 

CD 

rr 

I 



o 

0.001 





















'O-220 






P D =45W 






T C =25°C 




























"0-39 






S i 


5 D =6W 

C =25°C" 






i 



0.01 0.1 

tp (seconds) 



9-33 



Typical Performance Curves 

BV DSS Variation with Temperature 




Transfer Characteristics 



V D S = -25V 












































T A 


= -5! 


>°C 




/ 

/ 


















4 

t 


r 








T» 


= 2 


5°C 




/ 


/ 


✓ 
















— / 


/ 

✓ 




































^T 


F 


o°c 







































-2 -4 -6 -8 -1 

V GS (volts) 
Capacitance vs. Drain-to-Source Voltage 



o 
o 
3. 

o 









f= 1MHz 










V 




C|SS 

Coss 








Crss 





VP06E 

On-Resistance vs. Drain Current 



J 30 

.■• 
o 

co 20 



























v G s = - 


5V 
























10V 










4 
























/ 













































































































-0.2 -0.4 -0.6 -0.8 -1.0 

l D (amperes) 
V( th ) and R D s Variation with Temperature 



CO 

E 

O 1.0 



CO 

O 
> 







R 


I I 

->«,i™cn a -iov -o 1 a_ 




















V(th 


@ -2 


mA 



























































































































g 

CO 

D 



-50 50 100 150 

Tj(°C) 

Gate Drive Dynamic Characteristics 



m -6 

































ov 
























DS = 


-40 


/<— 














/ V 














OpF 




















































OpF 

























































-10 -20 -30 -40 

V DS (volts) 



0.5 1.0 1.5 2.0 2.5 

Qq (nanocoulombs) 



VP0808 
VP1008 




P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


(max) 


'd(ON) 

(min) 


Order Number / Package 


TO-39 


TO-92 


-80V 


5£i 


-1.1A 


VP0808B 


VP0808L 


-100V 


5Q 


-1.1A 


VP1008B 


VP1008L 



High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

! ] Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C ISS and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

I Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, memories, 
displays, bipolar transistors, etc.) 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV. GS 


Gate-to-Source Voltage 


±30V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1.6 mm from case for 10 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent In MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



IS] 



Package Options 




9-35 



VP0808/VP1008 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 


c/w 


9c 
C/W 


TO-39 


-0.88A 


-3A 


6.25W 


125 


20 


TO-92 


-0.28A 


-3A 


0.4W 


170 


125 



* l D (continuous) is limited by max rated T. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


^^DSS 


Drain-to-Source 
Breakdown Voltage 


VP1008 


-100 






V 


V r o=0V l n =-10uA 

Go ' D ^r*-' * 


VP8080 


-80 






^GS(th) 


Gate Threshold Voltage 


-1.0 




-4.5 


V 


v gs = v ds. I D = -1mA 


'gss 


Gate Body Leakage 






-100 


nA 


V GS = 30V, V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






-10 


uA 


V GS = 0V, V DS = Max Rating 


-500 


V GS = 0V, V DS = Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


-1.1 






A 


V GS = -10V, V DS = -15V 


^DS(ON) 


Static Drain-to-Source ON-State Resistance 






5 


n 


V GS = -10V, l D = -1A 


G FS 


Forward Transconductance 


200 






mU 


V DS = -10V, l D = -0.5A 


Ciss 


Input Capacitance 






150 


PF 


V GS = 0V, V DS = -25V 
f=1MHz 


c oss 


Common Source Output Capacitance 






60 


Crss 


Reverse Transfer Capacitance 






25 


'd(ON) 


Turn-ON Delay Time 






15 


ns 


V DD = -25V, l D = -0.5A 
Rgen = 25H 


t, 


Rise Time 






40 


l d(OFF) 


Turn-OFF Time 






30 


t, 


Fall Time 






30 


V S D 


Diode Forward Voltage Drop 


VP1008 




-1.2 




V 


V GS = 0V, l SD = -0.21A 


VP0808 




-1.2 




V QS = 0V, l SD = -0.9A 



Notes: 

1. All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




VP11A 



P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


p 

"DS(ON) 

(max) 


'd(ON) 

(min) 


Order Number / Package 


BV^s 


TO-39 


TO-220 


DICE* 


-60V 


2£2 


-5A 


VP1106N2 


VP1106N5 


VP1106ND 


-100V 


20 


-5A 


VP1110N2 


VP1110N5 


VP1110ND 



+ MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C lss and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, memories, 
displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°CtO+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



i!] 



Package Options 




TO-39 



TO-220 



Note: See package outline section for discrete pinouts. 



9-37 



VP11A 



Thermal Characteris 



ICS 



Package 


\ D (continuous)* 


l D (pulsed) 


Power Dissipation 

@T C =25°C 


cm 


c/w 


i * 
'dr 


•drm 


TO-39 


-1.5A 


-7A 


6W 


125 


20.8 


-1.5A 


-7A 


TO-220 


-4.0A 


-12A 


45W 


70 


2.78 


-4A 


-12A 



* l D (continuous) is limited by max rated T 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VP1110 


-100 






V 


l D = -5mA, V GS = 0V 


VP1106 


-60 


V GS(th) 


Gate Threshold Voltage 


-1.5 




-3.5 


V 


v gs = V DS . b = "5mA 


A V GS(th) 


Change in V GS(ttl) with Temperature 




4.0 




mV/°C 


l D = -5mA, V GS =V DS 


'gss 


Gate Body Leakage 






-100 


nA 


V GS = ±20V, V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






-50 


uA 


V GS = 0V, V DS = Max Rating 




-5 


mA 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 




-1 .0 






A 


V GS = -5V, V DS = -25V 


-5.0 


V GS = -10V, V DS = -25V 




Static Drain-to-Source 
ON-State Resistance 




1 .7 


5 


a 


V^e = -5V U = -0 5A 

v GS ov i 'D u,Jn 


1 .5 


2 


V^^--10V U - -? OA 
V GS - luv >'D — 




Change in R ds(0 n) with Temperature 




0.7 


1.0 


%/°C 


i D = -1.0A, V GS =-10V 


Gfs 


Forward Transconductance 


0.9 


1.3 




u 


V DS = -25V, l D = -2.0A 


C ISS 


Input Capacitance 




300 


350 


pF 


V GS = 0V, V DS = -25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




125 


150 


Crss 


Reverse Transfer Capacitance 




20 


35 


'd(ON) 


Turn-ON Delay Time 




35 


40 


ns 


V DD = -25V 
l D = -2.0A 

R G EN = 10£J 


t r 


Rise Time 




20 


30 


*d(OFF) 


Turn-OFF Delay Time 




40 


50 


t, 


Fall Time 




10 


20 


v SD 


Diode Forward Voltage Drop 




-1.4 


-2.5 


V 


l SD = -1.0A, V GS = 0V 


tr, 


Reverse Recovery Time 




400 




ns 


Isd = -1 OA, V GS = 0V 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300u.s pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 



ov 



t(HON) *r 



^d(OFF) 



90% 90% 



10% 



9-38 



PULSE 
GENERATOR 





Typical Performance Curves 

Output Characteristics 



I 
o 









































10V 
















































-8V 




























































-6V 






















































-4V 
































1 





-10 -20 -30 -40 -50 

V DS (volts) 
Transconductance vs. Drain Current 




V DS =-25V_ 



I I I I I 



T A =-55°C 



T A = 25°C 



T A = 150°C 



-1 -2 -3 -4 

l D (amperes) 
Maximum Rated Safe Operating Area 



2 

CD 
Q. 

E 

Q 



1 ML LI 111 _ 










TO-39 (pulsed) 






\ 

N 








TO-220 ( 














\ 




\ 
























I 




_ Tn-no mm 























































































































































































































































































































-1 -10 

V DS (volts) 



Saturation Characteristics 



a. -2 













Vgs 


= -10 
























-8V 


























































-6V 












































































-4V 









































V DS (volts) 
Power Dissipation vs. Case Temperature 



80 



1 

Q 40 
Q- 



















































-TO-2 












?o 


































- TO-39 












1 











25 50 75 100 125 150 
T C (°C) 

Thermal Response Characteristics 



^ 0.8 
E 



in 

a 0.4 
1 



















1 


0-220 






P D =45W 






1 


C = 25°C 


























■ 


"0-39 






1 


' D =6W 
- C =25°C- 






1 





0.001 



0.01 0.1 

tp (seconds) 



9-39 



VP11A 



Typical Performance Curves 

BV DSS Variation with Temperature 




I 3 
o 



g 

CO 2 
Q 

m 



On-Resistance vs. Drain Current 



















GS = 


-10 


\l \ 








" \ 


^GS 


= -5\ 




V 








j 



























































































































































-1 -2 -3 

l D (amperes) 



Transfer Characteristics 



V (th ) and R D s Variation with Temperature 



Q. 

E 

to 









I I I 
T A = -55° C J 




/ 




V 


DS = 




1 








/ 


















A 


* =2 


5°C 
























































Ta = 150 °C 
















































/ 




























I 



-2-4-6 

V GS (volts) 



-10 



a 1.0 
E 



S 0.9 
CO 

S 
> 



0.8 



50 
TiCC) 







I I I 

a -m\/ -pa 












in; — 










h)@- 


5mA 










































































































I 













1.0 « 



0.8 § 

CO 

rx° 

0.6 



100 150 



Capacitance vs. Drain-to-Source Voltage 



Gate Drive Dynamic Characteristics 




f = 1MHz 



Coss 
C RSS 



-10 -20 -30 

V DS (volts) 



m -6 
O 



CD 
> 

































_v 


DS = 


-10\ 


1 




















































Vde 


= -I 


tov- 














500p 












( 


F 










DpF 


















27 





































1 2 3 4 5 

Q G (nanocoulombs) 



9-40 



VP12A 




P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


"DS(ON) 

(max) 


'd(ON) 

(min) 


Order Number / Package 


BV DGS 


TO-39 


TO-220 


DICE+ 


-40V 


0.8il 


-6A 


VP1204N2 


VP1204N5 


VP1204ND 


-60V 


o.sa 


-6A 


VP1206N2 


VP1206N5 


VP1206ND 


-100V 


0.8S2 


-6A 


VP1210N2 


VP1210N5 


VP1210ND 



+ MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C lss and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, memories, 
displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 




Gate-to-Source Voltage 


+ 20V 


Operating and Storage Temperature 


-55°CtO+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertax's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



1!] 



Package Options 




VP12A 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 






■dr 


•drm 








@ T c = 25°C 


cm 


C/W 






TO-39 


-2.5A 


-11A 


6.5W 


125 


20 


-2.5A 


-11A 


TO-220 


-5.0A 


-14A 


45W 


70 


2.75 


-5A 


-14A 



* l D (continuous) is limited by max rated T. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Mln 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VP1210 


-100 






y 




I — -1 Hm A \/ — HV 


VP1206 


-60 


VP1204 


-40 


GS(th) 


dcilfc} 1 nitJbMUlU VUllctyt: 


-1.5 




-3.5 


V 


Vr-c = Vno In = "1 0mA 
GS DS' D — 


" v GS(th) 


Hhflnnp in V« . with Tpmnpratnrp 

v-'iiany c ill *QS(th) ' cin^jciaiuic 




4.7 


5.5 


mV/°C 


l D = -10mA, V GS = V DS 


'GSS 






-1 .0 


-100 


nA 


V GS = +20V, V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






-100 


uA 


V GS = 0V, V DS = Max Rating 


-10 


mA 


V GS = 0V, V DS = 0.8 Max Rating 
T A =125°C 


'd(ON) 


ON-State Drain Current 


-1.5 


-3.0 




A 


V GS = -5V, V DS = -25V 


-6.0 


-14.0 


V GS = -10V, V DS = -25V 


^DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




1.0 


1.4 


n 


V GS = -5V, l D = -1A 


0.5 


0.8 


V GS = -10V, l D = -3A 


A ^DS(ON) 


Change in R DS (on) witn Temperature 




1.0 


1.5 


%/°c 


l D = -3A, V GS = -10V 


G FS 


Forward Transconductance 


1 


2 




u 


V DS = -25V, l D = -3A 




Input Capacitance 




550 


650 




V GS = 0V, V DS = -25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




250 


350 


CrSS 


Reverse Transfer Capacitance 




50 


65 


'd(ON) 


Turn-ON Delay Time 




10 


30 


ns 


V DD = -25V 
l D = -4A 
R GEN = 10Q 


t, 


Rise Time 




17 


40 


'd(OFF) 


Turn-OFF Delay Time 




70 


105 


t. 


Fall Time 




35 


60 


V SD 


Diode Forward Voltage Drop 




-1.2 


-1.6 


V 


Isd = -5A, V GS = 0V 




Reverse Recovery Time 




500 




ns 


lsc = -1A, V GS = 0V 



1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300u.s pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




Typical Performance Curves 

Output Characteristics 



o. 
E 























































V 


GS = 


10V 




























































-8V 






































































-6V 

^tv 

























































-10 -20 -30 -40 

V DS (volts) 
Transconductance vs. Drain Current 



» 1.6 

O 



o 
o 



v D 


s = ' 


25V 
















































T A = 


-55 


















>C 


































t 






'A = 
- 


- + - 






t 










T A = 


125 


•c 
























t 









































-2-4-6-8 

l D (amperes) 
Maximum Rated Safe Operating Area 



CL 

E 
to 













l— V 






















■ 


Ml i 1 




















TO-39 (pulsed) 






- TO 


-22 


) (C 


)C 


) 






N 


































k 








































































































1 


0-: 


9 


( 


DC) 







































































































































































































-1.0 



-10 -100 

V DS (volts) 



VP12A 

Saturation Characteristics 



I -4 









1 


1 

v G s= 


1 

= -10\ 


t ^ 
























-8V 


































































































-6V 


























































































I 





-10 



V DS (volts) 
Power Dissipation vs. Case Temperature 



100 



1 
o 



















































-TO-2J 












o 


































- TO-3S 


1 






















25 50 75 100 125 150 
T C (°C) 

Thermal Response Characteristics 



15 
E 
o 



(0 

I 
£ 



0.4 





1 

TO-220 






P D =45W J 






T A =2 


5°C / 










































D-39 






<r P[ 


) = 6.5W 
= 25°C " 










0.001 



0.01 0.1 

t p (seconds) 



10 



■SJ 



Typical Performance Curves 

BV DSS Variation with Temperature 




Transfer Characteristics 



03 
Q. 

E 























V 


DS = 


-251 


1 














































T A 


= -5! 


>°c 
















= 25 


1 

c- 




/ 


















4 


■ 




































t a 


= 12! 


°C 











































-2 -4 •« 

V GS (volts) 



-10 



Capacitance vs. Drain-to-Source Voltage 



| 500 
O 









f = 1MHz 








Ciss 
















Coss 



-10 -20 -30 

V DS (volts) 



VP12A 

On-Resistance vs. Drain Current 



I 3 

z 
o 

(/) 2 













































v G s = 


-5V 




V GS =-10V 






















































































































— 



























0-3-6-9 -12 -11 

I D (amperes) 
V (th ) and R DS Variation with Temperature 



w 
o 
> 























R DS(ON) 


@ -1C 


V, -3> 


\ > 






- v (l 


. (rtt 1 Am A 

























































































































1.4 S 



O 

cc 



50 
TjfC) 



100 150 



Gate Drive Dynamic Characteristics 



& -6 
o 



to 





















y— 
















































1C 


60p 
























\ 


bs 


= -40 


V — 












-1C 


OOp 






















— 4 


BOpF 























































2 4 6 8 10 

Q G (nanocoulombs) 



9-44 



VP13A 

Supertax inc. 



P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BVoss/ 


(max) 


'd<0N) 

(mm) 


Order Number / Package 


BVdgs 


TO-39 


TO-92 


-40V 


25£2 


-0.25A 


VP1304N2 


VP1304N3 


-60V 


25H 


-0.25A 


VP1306N2 


VP1306N3 


-100V 


25Q 


-0.25A 


VP1310N2 


VP1310N3 



High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 
Low power drive requirement 

□ Ease of paralleling 

□ Low C lss and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 



Applications 



□ 
□ 



Motor control 
Converters 
□ Amplifiers 

□ 
□ 
□ 



Switches 

Power supply circuits 

Driver (relays, hammers, solenoids, lamps, memories, 



displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV D 



Drain-to-Gate Voltage 


BVdqs 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertax vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 



TO-39 



TO-92 



Note: See package outlh 



r discrete pinouts. 



9-45 



VP13A 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 






■da 


'drh 








© T c = 25 C 


°c/w 


°c/w 






TO-39 


-0.25A 


-0.8A 


3.0W 


125 


41 


-0.25A 


-0.8A 


TO-92 


-0.1 5A 


-0.65A 


0.8W 


170 


155 


-0.1 5A 


-0.65A 



* l (continuous) is limited by max rated T. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 




Min 


TVD 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VP1310 


-100 






V 


i D = -imA, v GS _ uv 


VP1306 


-60 


VP1304 


-40 


GS(th) 


OdLt; I IllfcibllOlU vuiidyc 


-1.5 




-3.5 


V 


V rc = Vnc, In = -1 ITlA 


^^GS(th) 


f^hannp in V_~, . . with Tpmnprati irp 
wiictiiycr hi »Q3(!hl vvin i i ci i i|jci ai.uic 




-3.2 


-3.85 


mV/°C 


V GS = v ds. b = -1 ™A 


'gss 


UaLc DUUy Lcdrlayc 




-0.1 


-100 


nA 


V GS = ±20V, V DS = 0V 


Loo 

'DSS 








-10 


uA 


V GS = 0V, V DS = Max Rating 


-500 


v gs = ov . v ds = 8 Max Rating 
T A = 125°C 




ON-State Drain Current 


-.08 


-0.23 




A 


V GS = -5V, V DS = -25V 


-0.25 


-0.7 




V GS = -10V, V DS = -25V 


^DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




32 


40 


a 


V GS = -5V, l D = -50mA 


19 


25 


V GS = -10V, l D = -250mA 


AR DS(ON) 


Change in R ds(0 n) witn Temperature 




0.8 


1.1 


%/°c 


l D = -250mA, V GS = -10V 




Forward Transconductance 


75 


120 




m!5 


V DS = -25V, l D = -200mA 


C ISS 


Input Capacitance 




20 


35 


PF 


V GS = 0V, V DS = -25V 
f=1 MHz 


Coss 


Common Source Output Capacitance 




12 


15 


Crss 


Reverse Transfer Capacitance 




3 


5 


'd(ON) 


Turn-ON Delay Time 




3 


5 


ns 


V D0 = -25V 
l D = -250mA 
R GEN = 25Q 


t, 


Rise Time 




3 


5 


l d(OFF) 


Turn-OFF Delay Time 




3 


5 


<f 


Fall Time 




3 


8 


V SD 


Diode Forward Voltage Drop 




-1.2 


-1.7 


V 


l SD = -1A,V GS = 0V 


trr 


Reverse Recovery Time 




350 




ns 


l SD = -1A, V GS = 0V 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




9-46 



VP13A 



Typical Performance Curves 

Output Characteristics 



jg -06 

I 
E 

CO 





































s - ' 


10V 
















V G 




















-8V. 


























































-6V- 


























































-4V< 


















-3V« 





















-10 -20 -30 -40 -SO 

V DS (volts) 



Saturation Characteristics 



-0.5 



§ -0.2 















I I 

\i mv 








































,-8V 




















.-6V 

























































































































0-2-4-8-8-10 

V DS (volts) 



Transconductance vs. Drain Current 



Power Dissipation vs. Case Temperature 



■ 
E 

.2 0.1 







I 


















s = 




























1 


A = 


-55° 


; 


































_J_ 

25°C _ 




























































25° 


3 































































-0.2 -0.4 -0.8 -0.8 -1.0 

l D (amperes) 
Maximum Rated Safe Operating Area 



E 
& 

j? 



-0.001 



TO-39 (pu 

I I I I 


•1 








■ 











sed)- 
1 




















ro- 


19 ( 


DC 


) 


























"N 


\ 
















- TO 


-92 


(DC 








s 






















s 









































































































































































-10 -100 

V DS (volts) 



-1000 



o? 2 







































TO-3S 
















































" TO-92 



































25 50 75 100 125 150 
T C (°C) 

Thermal Response Characteristics 



0.5 



i 























































TO-39 








P D =3W 



















0.001 0.01 0.1 1.0 

tp (seconds) 



Typical Performance Curves 



VP13A 




VP21A 



P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BVdss/ 
BVdqs 


R DS(ON) 

(max) 


If 


Order Number / Package 


TO-92 


DICE* 


-40V 


120 


-0.5A 


VP2104N3 


VP2104ND 


-60V 


12Q 


-0.5A 


VP2106N3 


VP2106ND 


-100V 


12£2 


-0.5A 


VP2110N3 


VP2110ND 



* MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
> and Ordering Information. 



Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C ISS and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 



Applications 



□ Motor control 

□ Converters 

□ Amplifiers 
P Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, memories, 
displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BVoqs 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°C to+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertax's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



Package Options 







? 

TO-92 




Note: See package outline section for discr 


ete pinouts. 







VP21A 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 
@ T c = 25°C 


c/w 


3c 
C/W 


"or* 


'drm 


TO-92 


-0.25A 


-0.8A 


LOW 


170 


125 


-0.25A 


-0.8A 



* l D (continuous) is limited by max rated T,. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Tim 

Typ 


Max 


Unit 


Lronaiiions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VP2110 


-1UU 






V 


l D = -1.0mA, V GS = 0V 


VP2106 


-60 


VP2104 




V GS(th) 


Gate Threshold Voltage 


-1 .5 




-3.5 


w 
V 


\/ \ / I 1 rim A 

v gs = v ds> 'o 1 -OrnA 


AV GS{th) 


Change in V GS(ttl) with Temperature 




C Q 

O.O 


O.O 


mv/ l> 


i D = -i.umA, v GS = v DS 


■gss 


Gate Body Leakage 




- 1 .u 


- I uu 


nA 


V GS = ±20V, V DS = 0V 


•dss 


Zero Gate Voltage Drain Current 






-f A 

-1U 


uA 


V GS = 0V, V DS = Max Rating 


-1 


mA 


v G s - ov, v DS = o.o Max Hating 
T A = 1 25°C 




ON-State Drain Current 


-0.15 


-0.25 




A 


V GS = -5V, V DS = -25V 


-0.50 


-1.0 




V GS = -10V, V DS = -25V 




Static Drain-to-Source 
ON-State Resistance 




11 


15 


n 


V GS = -5V, l D = -0.1A 


9 


12 


V GS = -10V, l D = -0.5A 


ARqs(ON} 


Change in R DS( on) witn Temperature 




0.55 


1.0 


%/°c 


l D = -0.5A, V GS =-10V 


G FS 


Forward Transconductance 


150 


200 






V DS = -25V, l D = -0.5A 




C|SS 


Input Capacitance 




45 


60 


pF 


V GS = 0V, V DS = -25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




22 


30 


c rss 


Reverse Transfer Capacitance 




3 


8 


l d(ON) 


Turn-ON Delay Time 




4 


5 


ns 


V DD = -25V 
l D = -0.5A 
Rqen = 25£2 


tr 


Rise Time 




5 


8 


'd(OFF) 


Turn-OFF Delay Time 




5 


9 


t. 


Fall Time 




4 


8 


V SD 


Diode Forward Voltage Drop 




-1.2 


-2.0 


V 


l SD = -0.5A, V GS = 0V 




Reverse Recovery Time 


| 400 




ns 


l SD = -1.0A, V GS = 0V 



Notes: 

1 .All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300ns pulse, 2% duty cycle.) 
2.AII A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




9-50 



Performance Curves 

Output Characteristics 



o 
a. 
E 

CO 































































































Vqs =- 


10V 




































p- 


, — 












-8V- 




















































-6V 

























-10 -20 -30 -40 -50 

V DS (volts) 

Transconductance vs. Drain Current 



250 



£ 100 

O 



50 



I I I 

\/ new 








T A = -55°C 




DS " 










— ■ 






















T A = 


25°( 


























































Ta = 


125 



















































































-0.2 -0.4 -0.6 -0.8 -1.0 

Id (amperes) 
Maximum Rated Safe Operating Area 



— I — l—W-l — I— 




























■ 








1 \J 




W 


u 




















• 


































TO 


92 


(C 


C 


) 

































































































































































































































































































































-1.0 -10 

V DS (volts) 



VP21A 

Saturation Characteristics 



































v G s =- 


10V 


















.-9V 




















•-OV 




















!-7V 






























































































-4V 























0-2-4-6 -8 -10 

V DS (volts) 
Power Dissipation vs. Case Temperature 



2.0 



8 i.o 



















































TO 


92 







































































25 50 75 100 125 150 

T C (°C) 

Thermal Response Characteristics 



.a 0.8 

CO 

E 



1 





























Tfl- 


52 






P D =1.0W 






Tc = 


25" C 





































0.001 0.01 0.1 1.0 

tp (seconds) 



Typical Performance Curves 



VP21A 




VP22A 




P-Channel Enhancement-Mode 
Vertical DMOS FETs 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


R DS(ON) 

(max) 


•d(ON) 

(min) 


Order Number / Package 


TO-39 


TO-92 


DICEt 


-40V 


0.9Q 


-4A 


VP2204N2 


VP2204N3 


VP2204ND 


-60V 


0.9Q 


-4A 


VP2206N2 


VP2206N3 


VP2206ND 


-100V 


0.9i2 


-4A 


VP2210N2 


VP2210N3 


VP2210ND 



+ MIL visual screening available 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C lss and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 



Applications 

□ Motor control 

□ Converters 



J Amplifiers 




□ Switches 




□ Power supply circuits 




□ Driver (relays, hammers, solenoids, lamps, memories, 
displays, bipolar transistors, etc.) 


Absolute Maximum Ratings 


Drain-to-Source Voltage 


BV DSS 


Drain-to-Gate Voltage 


BVqqs 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 



Advanced DMOS Technology 

These enhancement-mode (normally-off) transistors utilize a 
vertical DMOS structure and Supertex's well-proven silicon-gate 
manufacturing process. This combination produces devices with 
the power handling capabilities of bipolar transistors and with the 
high input impedance and positive temperature coefficient inher- 
ent in MOS devices. Characteristic of all MOS structures, these 
devices are free from thermal runaway and thermally-induced 
secondary breakdown. 

Supertex vertical DMOS FETs are ideally suited to a wide range 
of switching and amplifying applications where high breakdown 
voltage, high input impedance, low input capacitance, and fast 
switching speeds are desired. 



i!] 



Package Options 




* Distance of 1 .6 mm from case for 1 seconds. 



9-53 



VP22A 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed) 


Power Dissipation 






■dr 


'drm 








@ T c = 25°C 


c/w 


C/W 






TO-39 


-1.6A 


-8.0A 


6.0W 


125 


20 


-1.6A 


-8.0A 


TO-92 


-0.65A 


-4.0A 


LOW 


170 


125 


-0.65A 


-4.0A 



* l„ (continuous) is limited by max rated T r 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


VP2204 


-40 






V 


V„ = 0V, L=-10mA 

GS 1 D 


VP2206 


-60 


VP2210 


-100 


V GS(th) 


Gate Threshold Voltage 


-1.0 




-3.5 


V 


V GS = V DS , l D = -10mA 


AV G S(th) 


Change in V GS(th) with Temperature 




-4.3 


-5.5 


mV/°C 


V GS = V DS , l D = -10mA 


'gss 


Gate Body Leakage 




-1 


-100 


nA 


V GS = ±20V, V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






-50 


uA 


V es = 0V, V DS = Max Rating 


-10 


mA 


v gs = ov . v ds = °- 8 Max Rating 
T A = 125°C 


b(ON) 


ON-State Drain Current 


-1.5 


-2 




A 


V GS = -5V, V DS = -25V 


-4 


-9 


V GS = -10V, V DS =- 25V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 




1.3 


1.5 


a 


V GS = -5V, l D = -1A 


0.75 


0.9 


V GS = -10V, l D = -3.5A 


AR DS(ON) 


Change in R DS (on) with Temperature 




0.85 


1.2 


%/°c 


V GS = -10V, l D = -3.5A 




Forward Transconductance 


0.8 


1.4 




u 


V DS = -25V, l D = -2A 


C|SS 


Input Capacitance 




325 


450 


pF 


V 3S = 0V . V DS = - 25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 




125 


180 


Crss 


Reverse Transfer Capacitance 




30 


40 


*d(ON) 


Turn-ON Delay Time 




4 


10 


ns 


V DD = -25V 
l D = -4A 

R GEN = ion 


*, 


Rise Time 




16 


30 


'd(OFF) 


Turn-OFF Delay Time 




16 


30 


t, 


Fall Time 




22 


40 


V SD 


Diode Forward Voltage Drop 




-1.1 


-1.6 


V 


V GS = 0V, l SD = -3.5A 


trr 


Reverse Recovery Time 




500 




ns 


V GS = 0V, l so = -1A 



Note 1: All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300u.s pulse, 2% duty cycle.) 
Note 2: All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 



INPUT 



OUTPUT 




Typical Performance Curves 



VP22A 



Output Characteristics 



Saturation Characteristics 













1 






























Vq. 




10V 


































































f 








































































\ 





















































































1 1 

\l -im/ 
















•G 












































-8V 


























































-6V; 








































-4V, 




















-3V. 



-TO -20 -30 -40 

V DS (volts) 



-4 -6 

V DS (volts) 



Transconductance vs. Drain Current 



G 




T A = 25°C - 



" T A = -55°C 



T A =125°C 



-5 

l D (amperes) 



-10 



Power Dissipation vs. Case Temperature 



10 



1 

Q 4 
O- 







































TO-3S 














N 




























H 


















TO-9S 


— 











25 50 75 100 125 150 



Maximum Rated Safe Operating Area 



Thermal Response Characteristics 







TO-39 (pulsed) 




(p'ujsed)' > 














I 

TO-39 


(DC 








V 


i 










) 




\ ■ 
\ 


































> 


_ 
> 


























































TO- 


92 ( 


DC 





















































































































-10 -100 

V DS (volts) 





























-rr\ QQ 








P D =6.0W / 






T c =25 


= C / 










0-92 

D = 1.0W_ 






/ P 






r T 


: =25°C 











0.001 0.01 0.1 1 10 

tp (seconds) 



9-55 



Typical Performance Curves 




9-56 



Alphanumeric Index and Ordering Information 

•notoma tafc»q8.4M» 9C Corporate Prof i le WM 

Applications Notes WM 

Quality Assurance and Handling Procedures WiM 

f Process Flow WM 

Selector Guides and Cross Reference 1*91 

N- and P-Channel Low Threshold MOSFETs WM 



DMOS N-Channel Discretes MM 

DMOS P-Channei Discretes WM 

DMOS Arrays and Special Functions WW 

High Voltage Driver/Interface ICs !§■ 

High Voltage Analog Switches and Multiplexers &M 

High Voltage Power Supply ICs iKfl 

CMOS Consumer/Industrial Products \IM 

Surface Mount Packages and Lead Bend Options iffl 

Package Outlines \[M 

Die Specifications WM 

Rspresen tatives/DisI hb\ i toi s I £ I ■ 



Chapter 10 - DMOS Arrays and Special Functions 

AN01 8 N-Channel Monolithic Array; 1 60, 200, 300, 320, 400V; 300, 350 ohms 10-1 

AN04 8 N-Channel Monolithic Array; 160, 200, 300, 320, 400V; 300, 350 ohms 10-6 

AN05 Semicustom 8 N-Channel Monolithic Array with Logic; 1 60, 320V; 350 ohms 10-9 

AP01 8 P-Channel Monolithic Array; -160, -200, -300, -320, -400V; 600, 700 ohms 10-11 

AP04 8 P-Channel Monolithic Array; -1 60, -200, -300, -320, -400V; 700, 600 ohms 10-16 

AP05 Semicustom 8 P-Channel Monolithic Array with Logic; -1 60, -320V; 700 ohms 10-19 

HT01 8-Channel Logic to High Voltage Level Translator 10-21 

TC0604WG 40V, 3 ohms 10-24 

TN0604WG 40V, 1 ohms 1 0-25 

TN0606N6/TN0606N7 60V, 1 .5 ohms 1 0-26 

TP0604WG -40V, 2 ohms 10-27 

TP0606N6/TP0606N7 -60V, 3.5 ohms 10-28 

TQ3001/VQ3001A/Q7254 N- and P-Channel Quad Power MOSFET Array; 40, 20V; 3 ohms 10-29 

VC01 06N6/VC01 06N7 60V, 1 1 ohms 1 0-32 

VN01 04N6/VN01 04N7/VN01 06N6A/N01 06N7 40, 60V; 3 ohms 1 0-33 

VP0104N6/VP0104N7A/P0106N6A/P0106N7 -40, -60V; 8 ohms 10-34 

VQ1000 60V; 5.5 ohms 10-35 

VQ1 001 30V, 1 .0 ohms 1 0-40 

VQ1004 60V, 3.5 ohms 10-42 

VQ2001 -30V, 2 ohms 1 0-44 

VQ2006 -90V, 5 ohms 10-46 



AN01 



8 Channel MOSFET Array 
Monolithic N-Channel Enchancement Mode 

Ordering Information 



BV DSS / 
BV DGS 

(min) 


R DS(ON) 

(max) 


If 


Idss"«V ds = 
100V Max 


'dss** ® v os = 
250V Max 


Order Number / Package 


18- Lead 
Plastic DIP 


Plastic 
SOW-20* 


Diet 


160V 


350Q 


25mA 


1nA 




AN0116NA 


AN0116WG 


AN0116ND 


200V 


300Q 


25mA 






AN0120NA 




AN0120ND 


300V 


300a 


25mA 






AN0130NA 




AN0130ND 


320V 


350£2 


25mA 




1nA 


AN0132NA 


AN0132WG 


AN0132ND 


400V 


350Q 


25mA 






AN0140NA 


AN0140WG 


AN0140ND 



* Same as SO-20 with 300 mil wide body. 

** Average current per channel, measured with all eight channels connected in parallel. 

* MIL visual screening available 

Features 

□ Low drain to source leakage for AN01 1 6 and AN01 32 

□ 1 60-volt to 400-volt capability 

Z Interfaces directly to CMOS logic 

□ 8 independent channels 

□ Low crosstalk between channels 

□ Low power dissipation 

E3 Pin compatible with industry standard driver array 

□ Free from secondary breakdown 



Applications 



□ High impedance/low leakage measurements 
for bare board testers 

□ High voltage piezoelectric transducer drivers 

□ High voltage electroluminescent panel drivers 

□ High voltage electrostatic array drivers 

□ General multi-channel driver array 

Absolute Maximum Ratings 

Drain-tc-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


Channel-to-Channel Crosstalk 


10mV/V 


* Distance ot 1 .6 mm from case for 10 seconds. 



General Description 

The Supertex AN01 series of high voltage arrays is designed to 
provide the interface between CMOS logic and loads requiring 
high voltages and intermediate currents. Each circuit consists of 
eight channels in a common-source configuration with open 
drains. This design minimizes the number of package leads 
needed. 

The AN01 1 6 and AN01 32 are ideally suited for low leakage/high 
impedance measurement, providing excellent accuracy and 
resolution for automatic test equipment. 



Ill] 



Package Options 




18-Lead DIP 




SOW-20 



10-1 



AN01 



Package 


l D (continuous)* 


l D (pulsed)* 


Power Dissipation 
@ T c = 25°C 


°c/w 


% 

°c/w 


■or 


■ * 

DRM 


18 Lead Plastic 


30mA 


75mA 


1.5W 


135 


83 


30mA 


75mA 


SOW - 20 


30mA 


75mA 


1.4W 


110 


89 


30mA 


75mA 



1 D (continuous) is limited by max rated "H 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 



Parameter 



Min 



Typ 



Max 



Unit 



Conditions 



Drain-to-Source 
Breakdown Voltage 



AN0116 



160 



AN0120 



200 



AN0130 



300 



V GS = 0, l D = 100uA 



AN0132 



320 



AN0140 



400 



y GS<tti) 



Gate Threshold Voltage 



'GS~ V DS i 'D 



l n = 1 mA 



AV, 



GS(th) 



Change in V GS(Sl) with Temperature 



-3.5 



mV/°C 



»GS- V DS ■ 'D 



In = 1 mA 



Gate Body Leakage 



AN0120 



AN0130 



10 



nA 



V GS = ±20V,V DS = 0< 3 > 



AN0140 



AN0116 



nA 



V GS = ±20V, V DS = 



AN0132 



Zero Gate Voltage 
Drain Current 



AN0120 



uA 



V GS = 0, V DS = Max Rating^ 



AN0130 



mA 



AN0140 



AN0116 



nA 



V GS = 0, V DS = 0.8 Max Rating 

T A = 125°C< 3 > 

V GS = 0V, V DS = 100V< 3 > 



HA 



V G s = ov . v ds = 8 Max Rating 
T A = 125°C' 3 » 



AN0132 



nA 



Vgs = 0V. Vds = 250V' 3 ) 



uA 



V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C< 3 » 



'D(ON) 



ON-State Drain Current 



25 



mA 



V GS = 10V, V DS = 25V 



R DS(( 



:on> 



Static Drain-to-Source 
ON-State Resistance 



AN0120 



300 



V GS =10V, l D = 10mA 



AN0130 



AN0116 



AN0132 



350 



V GS =10V, l D = 10mA 



AN0140 



AR OS(l 



Change in Ros(th) with Temperature 



0.8 



%/°C 



V GS =10V, l D = 10mA, 



Forward Transconductance 



4.0 



8.0 



mU 



AV GS =1V, l D = 10mA 



Input Capacitance 



5.0 



7.5 



Common Source Output Capacitance 



3.0 



5.0 



PF 



Reverse Transfer Capacitance 



0.8 



1.5 



V GS = 0,V DS = 25V,f=1MHz 







V>N) 



Turn-ON Delay Time 



Rise Time 



Turn-OFF Delay Time 



Fall Time 



V DD = 25V, l D = 10mA 
R GEN = 25Q 



Diode Forward Voltage Drop 



1.3 



V GS = 0, l SD = 50mA 



1 . All D.C. parameters 1 00% tested at 25°C unless otherwise 

2. All A.C. parameters sample tested. 

3. Average current per channel, measured with all 8 channels 



stated. (Pulse test: 300us pulse, 2% duty cycle.) 
connected in parallel. 



10-2 



Switching Waveforms and Test Circuit 



10V 



INPUT 



*tHON) *r 



OV 



\H0FF) *F 



90% \ 3^90% 



V D0 




Typical Performance Curves 

Output Characteristics 



I 
o 











< 


GS = 


10V 
































































8V 

























































































































































10 20 30 40 50 

V DS (volts) 
Transconductance vs. Drain Current 



I 12 

i 

£ 9 
(D 



I I I 

Vns = -25V 
















































T A = 


-55 


C 


f 






















































t a = 


25° 


C 


f 












I I 


















T A = 


125 


•c 











































20 40 60 80 100 

l D (milliamperes) 



1 20 
a 



Saturation Characteristics 















v 


3S= 1 


OV 




























































.8V 






































i6V 








































■ 4V 













































2 4 6 

V DS (volts) 



Power Dissipation vs. Case Temperature 

(For one channel) 



§ 150 
5 



Q 100 
Q_ 































astic 





























































































25 50 75 100 125 150 

TcfC) 



10-3 



Typical Performance Curves 




10-4 



AN01 



Pin Configuration and Schematic 




top view 
18-pin DIP 





% 


IT 


w 


20 | 








2 






NC 




G 3 


3 






D 2 




G. 


4 




j3 


D 3 




G 5 


5 






°« 




G 6 








D 5 




G 7 








D 6 




Ga 


8 






D 7 




NC 


9 






NC 




S 


10 




in 


D 8 



top view 

SOW - 20 



10-5 



AN04 

Gate Protected 



Preliminary 



8 Channel MOSFET Array 
Monolithic N-Channel Enchancement Mode 

Ordering Information 



BV DSS / 
BV DGS 
(min) 


^DSION) 

(max) 


If 


W*@v DS = 

100V Max 


"dss" @ V DS = 
250V Max 


Order Number / Package 


18-Lead 
Plastic DIP 


Plastic 
SOW-20* 


Diet 


160V 


350H 


25mA 


1nA 




AN0416NA 


AN0416WG 


AN0416ND 


200V 


30on 


25mA 






AN0420NA 




AN0420ND 


300V 


300£i 


25mA 






AN0430NA 




AN0430ND 


320V 


350£J 


25mA 




1nA 


AN0432NA 


AN0432WG 


AN0432ND 


400V 


350£i 


25mA 






AN0440NA 


AN0440WG 


AN0440ND 



* Same as SO-20 with 300 mil wide body. 

** Average current per channel, measured with all eight channels connected in 
t MIL visual screening available 



Features 

□ ESD Gate Protection 

□ Low drain to source leakage for AN041 6 and AN0432 

□ 1 60-volt to 400-volt capability 

1 Interfaces directly to CMOS logic 

□ 8 independent channels 

□ Low crosstalk between channels 

□ Low power dissipation 

□ Pin compatible with industry standard driver array 

□ Free from secondary breakdown 



General Description 

The Supertex AN04 series of high voltage arrays is a ruggedized 
ESD gate protected version of the Supertex AN01 series. These 
multichannel arrays meet the El A ESD standard of 2000V, 1 0OpF 
capacitor in series with a 1 .5KI1 resistor. They are designed to 
provide interface between CMOS logic and loads requiring high 
voltages and intermediate currents. Each circuit consists of eight 
channels in a common-source configuration with open drains. 
This design minimizes the number of package leads needed. 

The AN041 6 and AN0432 are ideally suited for low leakage/high 
impedance measurement, providing excellent accuracy and reso- 
lution for automatic test equipment. 



Package Options 



Applications 



[ High impedance/low leakage measurements for Bare 
Board Testers 

: High voltage electroluminescent panel drivers 
C l High voltage electrostatic array drivers 
□ General multi-channel driver array 

Absolute Maximum Ratings 

Drain-to-Source Voltage 



BVn 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°CtO+150°C 


Soldering Temperature* 


300°C 


Channel-to-Channel Crosstalk 


10mV/V 


* Distance of 1.6 mm from case for 10 seconds. 




10-6 



AN04 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed)* 


Power Dissipation 

eTc=25°C 


% 

c/w 


°c/w 


'dr 


■ * 

>DRM 


1 8 lead plastic 


30mA 


75mA 


1.5W 


135 


83 


30mA 


75mA 


SOW - 20 


30mA 


75mA 


1.4W 


110 


89 


30mA 


75mA 



l D (continuous) is by max rated Ti 



Electrical Characteristics (@ 25 c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


DV DSS 


Drain-to-Source 
Breakdown Voltage 


AN0416 


160 






V 


l D =100uA, V GS =0V 


AN0420 


200 


AN0430 


300 


AN0432 


320 


AN0440 


400 


VGS(th) 


Gate Threshold Voltage 


2 




5 


V 


V gs = V ds , l = 1mA 


AV GS(th) 


Change in V GS(th) with Temperature 




-3.5 




mV/'C 


v gs= v ds. I D = 1mA 


'qss 


Gate Body Leakage 


AN0420 
AN0430 
AN0440 






10 


nA 


V GS = ±20V,V DS =0V(3) 


AN0416 
AN0432 






1 


nA 


V GS =±20V,V DS = 0V(3) 


'dss 


Zero Gate Voltage 
Drain Current 


AN0420 






1 


uA 


V GS = 0, V DS = Max Rating (3) 


AN0430 
AN0440 






1 


mA 


V QS = 0, V DS = 0.8 Max Rating 
T A ,=125°C (3) 


AN0416 






1 


nA 


V GS = 0V, V DS =100V (3) 






2 


uA 


V r o = 0V, Vno = 0.8 Max Rating 
T A =125°C(3) 


AN0432 






1 


nA 


V GS =0V,V DS =250V (3) 






2 


uA 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 125°C(3) 


'd(ON) 


ON-State Drain Current 




25 






mA 


V GS =10V, V DS = 25V 


R DS(ON) 


Static Drain-to-Source 


AN0420 
AN0430 






300 


a 


V GS = 10V, l D = 10mA 


ON-State Resistance 


AN0416 
AN0432 
AN0440 






350 


a 


V GS = 10V, l D = 10mA 


ARdS(ON) 


Charge in R ds(0 n) with Temperature 




0.8 




%/°c 


V GS = 10V, l D = 10mA 


G FS 


Forward Transconductance 


4.0 


8.0 




mU 


AV GS = 1V, l D =10mA 


C ISS 


Input Capacitance 




8.0 


12.0 


PF 


V DS = 25V,V GS = 0V 
f = 1 MHz 


^OSS 


Common Source Output Capacitance 




5.0 


8.0 


Crss 


Reverse Transfer Capacitance 




1.3 


2.4 


td(ON) 


Turn-ON Delay Time 




5.0 




ns 


V DD = 25V, 
l D = 10mA, 
Rgen = 25£2 


t, 


Rise Time 




5.0 




'd(OFF) 


Turn-OFF Delay Time 




8.0 




tf 


Fall Time 




5.0 




V SD 


Diode Forward Voltage Drop 






1.3 


V 


V GS = 0V, l SD = 50mA 



1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 

3. Average current per channel, measured with all 8 channels connected in parallel. 



10-7 



AN04 



Switching Waveforms and Test Circuit 



10V 



INPUT 



OUTPUT 



'(ON) 



SHOFF) *F 



\ Jf-10% 
50% \ jF 90% 



!"" 



PULSE 
GENERATOR 





o OUTPUT 



D.U.T. 



Pin Configuration and Schematic 

d] 



NC [T 
G 2 [~3 
G 3 LI 

g„ d 
g 5 d 

G 6 d 

g 7 d 
Go n 



J ^~^n s 



top view 
1 8-pin DIP 



a, Ldj 




20 1 


D, 


g 2 cr 






NC 


g 3 dC 




3D 


D 2 


G 4 dC 




JEl 


D 3 


g 5 dC 




3E 


E>, 


g 6 EE 






D 5 


G 7 dC 




jE 


D e 


g 8 EE 




3EI 


D ? 


NC C£ 




12 1 


NC 


s QE 




3D 





top view 
SOW - 20 



10-8 



AN05 



Semicustom 8 N-Channel Monolithic 
High Voltage Array With Logic 



Ordering Information 



HV 0UT 

(Max) 


"out 
(Max) 


'oUT(ON) 

(Max) 


'OUT(OFF)* ® V OUT - 

100V Max 


'0UT(0FF)* ® V 0UT - 

250V Max 


Order 
Number 7 


Package Options 


160V 


350£2 


25mA 


1nA 




AN0516 


Available in Plastic DIP, 
Surface Mount SOIC, and Die. 


320V 


350H 


25mA 




1nA 


AN0532 



* Average current per channel, measured with all eight channels connected in parallel, 
t Excluding package suffix. 



Features 

□ Custom logic control 

□ Low output leakage current 

□ ESD input protection 

P Interfaces directly to CMOS logic 

□ 8 independent channels 

□ Low crosstalk between channels 

□ Low power dissipation 

□ Free from secondary breakdown 



Description 



The Supertex AN05 series of semicustom high voltage monolithic 
devices consist of 8-channel open drain common source N- 
channel array with logic. The Logic configuration and packaging 
are determined by customer requirements. 

The AN051 6 and AN0532 are ideally suited for low leakage/high 
impedance measurement, providing excellent accuracy and 
resolution for automatic test equipment. 



Applications 



□ High impedance/low leakage measurements 
for bare board testers 

□ Sample and hold circuits 

□ High voltage electrostatic array drivers 

□ Addressable multi-channel driver array 



Absolute Maximum Ratings 1 


Output Voltage, HV OUT 


320V+ 


Logic Supply Voltage, V DD 


-0.5V to 18V 


Logic Input Voltage 


-0.5V to V DD +0.3V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature 2 


300°C 


Channel to Channel Crosstalk 


10mVA/ 



Notes: 

1 . All voltages referenced to V ss . 

2. Distance of 1 .6mm from case for 1 seconds, 
f ForAN0532 



Package Options 



16-Lead DIP 





SOW-20 



Notel : Consult factory for other package options. 



10-9 



Block Diagram 



Logic Input 
Controls 




O HV Oul 



O HV 0ul 1 



O HV 0ut 2 



O HV 0ut 3 



■O HV 0ut 4 



O HV 0ut 5 



O HV 0ut 6 



O HV 0ut 7 



Pin Configuration and Package 



Based on customer requirements 



10-10 



AP01 



8-Channel MOSFET Array 
Monolithic P-Channel Enchancement Mode 



Ordering Information 



BV DS9 / 
BVdos 
(min) 


"ds(on) 
(max) 


II 


'dss"®V ds = 
-100V Max 


loss" O V DS = 
-250V Max 


Order Number / Package 


18- Lead 
Plastic DIP 


Plastic 
SOW-20* 


Die* 


-160V 


700Q 


-15mA 


-1.5nA 




AP0116NA 


AP0116WG 


AP0116ND 


-200V 


600Q 


-15mA 






AP0120NA 




AP0120ND 


-300V 


600£1 


-15mA 






AP0130NA 




AP0130ND 


-320V 


700£2 


-15mA 




-1.5nA 


AP0132NA 


AP0132WG 


AP0132ND 


-400V 


700ii 


-15mA 






AP0140NA 


AP0140WG 


AP0140ND 



Same as SO-20 with 300 mil wide body. 
Average current per channel, measured 
MIL visual screening available 



with all eight channels connected in parallel. 



Features 

□ Low drain to source leakage for AP01 1 6 and AP01 32 

□ 1 60-volt to 400-volt capability 

□ Interfaces directly to CMOS logic 

□ 8 independent channels 

□ Low crosstalk between channels 

□ Low power dissipation 

□ Pin compatible with industry standard driver array 

□ Free from secondary breakdown 

Applications 

□ High voltage electroluminescent panel drivers 
n High voltage electrostatic array drivers 

□ General multi-channel driver array 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



General Description 

The Supertex AP01 series of high voltage arrays is designed to 
provide interface between CMOS logic and loads requiring high 
voltages and intermediate currents. Each circuit consists of eight 
channels in a common-source configuration with open drains. 
This design minimizes the number of package leads needed. 

The AP01 16 and AP0132 are ideally suited for low leakage/high 
impedance measurement, providing excellent accuracy and 
resolution for automatic test equipment. 



Ill] 



Package Options 



Drain-to-Gate Voltage 


BVdgs 




Gate-to-Source Voltage 


±20V 


SOW-20 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 




Channel-to-Channel Crosstalk 


10mV/V 





' Distance of 1 .6 mm from case for 1 seconds. 



10-11 



AP01 



Thermal Characteristics 



Package 


l (continuous)* 


l D (pulsed)* 


Power Dissipation 


9 |. 


9 ,c 


'dr 


■ * 
'drm 








@ T c = 25°C 


c/w 


°c/w 






1 8 lead plastic 


-15mA 


-40mA 


1.5W 


135 


83 


-15mA 


-40mA 


SOW - 20 


-15mA 


-40mA 


1.4W 


110 


89 


-15mA 


-40mA 



* l D (continuous) is limited by max rated Tj. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source 
Breakdown Voltage 


AP0116 


-160 






V 


V GS = 0, l D =-100uA 


AP0120 


-200 


AP0130 


-300 


AP0132 


-320 


AP0140 


-400 


V GS(th) 


Gate Threshold Voltage 


-2 




-5 


V 


v gs= v ds. l D = -1mA 


AV GS(th) 


Change in V GS(th) with Temperature 




-3.5 




mV/°C 


V - V l~ - -1 mA 

v GS — "DS i D ll'IM 


'gss 


Gate Body Leakage 


AP0120 
AP0130 
AP0140 






-10 


nA 


V GS = ±20V, V DS = 0V< 3 > 


AP0116 
AP0132 






-1 


nA 


V GS = ±20V, V DS = 0V< 3 > 


'dss 


Zero Gate Voltage 
Drain Current 


AP0120 






-1 


uA 


V GS = 0, V DS = Max Rating' 3 ' 


AP0130 
AP0140 






-1 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C( 3 > 


AP0116 






-1.5 


nA 


V GS = 0V, V DS = -100V< 3 > 






-3 


uA 


V GS = 0, V DS = 0.8 Max Rating 

I £ — I d.O ' 


AP0132 






-1 .0 


nA 


V GS = 0V, V DS = -250VP) 


-o 


uA 


V GS = 0, V os = 0.8 Max Rating 
T A = 125°C< 3 > 


^D(ON) 


ON-State Drain Current 


-15 






mA 


V GS = -10V. V DS = -25V 


^DS(ON) 


Static Drain-to-Source 
ON-State Resistance 


AP0120 
AP0130 






600 


a 


V GS =-10V, l D = -10mA 


AP0116 
AP0132 
AP0140 






700 


a 


V GS =-10V, l D = -10mA 


AR DS(th) 


Change in R DS(th) with Temperature 




0.8 




%/°C 


V GS = -10V, l D = -10mA, 


G FS 


Forward Transconductance 


3.0 


5.0 




mU 


V DS = -25V, l D = -5mA 


Ciss 


Input Capacitance 




5.0 


7.5 


PF 


V GS = 0, V DS = -25V,f=1MHz 


Coss 


Common Source Output Capacitance 




3.0 


5.0 


Crss 


Reverse Transfer Capacitance 




1.0 


2.0 


*d(ON) 


Turn-ON Delay Time 




3 




ns 


V DD = -25V, l D = -10mA 

^GEN = 25ti 


tr 


Rise Time 




3 




'd(OFF) 


Turn-OFF Delay Time 




5 




t. 


Fall Time 




3 




v SD 


Diode Forward Voltage Drop 






-1.5 


V 


V GS = 0, l so = -25mA 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300ns pulse. 2% duty cycle.) 

2. All A.C. parameters sample tested. 

3. Average current per channel, measured with all 8 channels connected in parallel. 



10-12 




Typical Performance Curves 

Output Characteristics 































































































v 













































-8V 


























1 



















































-10 -20 -30 -40 -50 

V DS (volts) 
Transconductance vs. Drain Current 



I 

Vnc = 


I 

-25V 




























T A = 


-55 


C 
























































T A = 


25° 


Z — 






































































Ta 


= 15( 


>°C 











































Saturation Characteristics 



g -8 



































v 


3S=- 


10V 








































( -8V 




























































-6V, 






































































-4V 























250 



| 150 



Q 100 
Q- 



-2 -4 -6 -8 -10 

V DS (volts) 
Power Dissipation vs. Case Temperature 

(For one channel) 











































Pla 


stic 















































































-1 -3 

l D (milliamperes) 



25 50 75 100 125 150 

T C (°C) 



10-13 



Pin Configuration and Schematic 



AP01 



NC [J 

g 2 q: 



-In -~m 



4 J n 



3T_r 



G 3 

G 4 [I 

G e rr-' n ^ ^j - 12 1 l>7 

Q 7 EE-'n rim D <» 

/ -X-t T_l 

G 8 I 9 H r-| 10 I S 



17J D 2 
~16~| D 3 

D 7 



top view 
18-pin DIP 







20 1 


D, 


G 2 EE 




J9] 


NC 


g 3 LZ 




XI 


D 2 








D 3 


g 5 lZ 




jE 


D 4 


g 6 lZ 




jE 


D 5 


g 7 nt 




jE 


D 6 


g s EE 




3E 


D 7 


nc rr 




jE 


NC 


s EE 




no 


D 8 



top view 
SOW - 20 



mm 



AP04 



Gate Protected 



Preliminary 



8 Channel MOSFET Array 
Monolithic P-Channel Enchancement Mode 



Ordering Information 



Moss/ 
(min) 


^DS(ON) 

(max) 


'd(ON) 

(min) 


•dss** ® v ds - 
-100V Max 


'dSS** • V DS = 

-250V Max 


Order Number / Package 


18-Lead 
Plastic DIP 


Plastic 
SOW-20* 


Diet 


-160V 


700S2 


-15mA 


-1.5nA 




AP0416NA 


AP0416WG 


AP0416ND 


-200V 


600£2 


-15mA 







AP0420NA 




AP0420ND 


-300V 


600Q 


-15mA 






AP0430NA 




AP0430ND 


-320V 


700U 


-15mA 




-1.5nA 


AP0432NA 


AP0432WG 


AP0432ND 


-400V 


700£J 


-15mA 






AP0440NA 


AP0440WG 


AP0440ND 



Same as SO-20 with 300 mil wide body. 
** Average current per channel, measured with all eight channels connected in parallel, 
t MIL visual screening a 



Features 

□ ESD gate protection 

□ Low drain to source leakage for AP041 6 and AP0432 

□ 1 60-volt to 400-volt capability 

□ Interfaces directly to CMOS logic 

□ 8 independent channels 

□ Low crosstalk between channels 

□ Low power dissipation 

□ Pin compatible with industry standard driver array 
Free from secondary breakdown 



General Description 

The Supertex AP04 series of high voltage arrays is a ruggedized 
ESD gate protected version of the Supertex AP01 series. These 
multichannel arrays meet the EIA ESD standard of 2000V, 1 0OpF 
capacitor in series with a 1 .5KQ resistor. They are designed to 
provide interface between CMOS logic and loads requiring high 
voltages and intermediate currents. Each circuit consists of eight 
channels in a common-source configuration with open drains. 
This design minimizes the number of package leads needed. 

The AP041 6 and AP0432 are ideally suited for low leakage/high 
impedance measurement, providing excellent accuracy and 
resolution for automatic test equipment. 



Package Options 



Applications 



□ High impedance/low leakage measurements 
for bare board testers 

f I High voltage electroluminescent panel drivers 

□ High voltage electrostatic array drivers 

□ General multi-channel driver array 

Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±20V 


Operating and Storage Temperature 


-55°CtO+150°C 


Soldering Temperature* 


300°C 


Channel-to-Channel Crosstalk 


10m V/V 


* Distance of 1 .6 mm from case for 1 seconds. 




10-16 



AP04 



Thermal Characteristics 



Package 


l D (continuous)* 


l D (pulsed)* 


Power Dissipation 

@T C =25°C 


9 i. 

°c/w 


% 

°c/w 


'dh 


'drm 


18 lead plastic 


-15mA 


-40mA 


1.5W 


135 


83 


-15mA 


-40mA 


SOW -20 


-15mA 


-40mA 


1.4W 


110 


89 


-15mA 


-40mA 



l D {continuous) is limited by max rated Tj 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


bV DSS 


Drain-to-Source 
Breakdown Voltage 


AP0416 


- idu 






V 


l D =-100uA, V GS =0V 


AP0420 




AP0430 


-300 


AP0432 


-320 


AP0440 


-400 


V GS(th) 


Gate Threshold Voltage 


-2 




-5 


V 


v gs = V DS . l D = -1mA 


AV G S(th) 


Change in V GS(th) with Temperature 




-3.5 




mV/°C 


v gs= v ds. l D = -1mA 


Iqss 


Gate Body Leakage 


AP0420 
AP0430 
AP0440 






-10 


nA 


V GS = ±20V, V DS =0V (3) 


AP0416 
AP0432 






-1 


nA 


V GS =±20V, V DS =0V(3) 


'dss 


Zero Gate Voltage 
Drain Current 


AP0420 






-1 


uA 


V GS = 0, V DS = Max Rating (3) 


AP0430 
AP0440 






-1 


mA 


V GS = 0, V DS = 0.8 Max Rating 
T A =125°C(3) 


AP0416 






-1.5 


nA 


V GS = 0V, V DS = -100V (3) 






-3 


uA 


V GS = 0V, V DS = 0.8 Max Rating 
T A =125°C (3) 


AP0432 






-1.5 


nA 


V GS = 0V,V DS =-250V (3) 






-3 


uA 


V GS = 0V, V DS = 0.8 Max Rating 
I A = 125 C/ (3) 


'n(ON) 


ON-State Drain Current 




"ID 






mA 


V GS = -10V, V DS =-25V 


M DS(ON) 


Static Drain-to-Source 
ON-State Resistance 


AP0420 
AP0430 






600 


£i 


V GS = -10V, l D =-10mA 


AP0416 
AP0432 
AP0440 






700 


SI 


V rt; = -10V, l n = -10mA 


AR DS(ON) 


Charge in R DS (on) witn Temperature 




0.8 




%/°C 


V GS = -10V, l D = -10mA 




Forward Transconductance 


3.0 


5.0 




mU 


V DS =-25V, l D = -5mA 


Ciss 


Input Capacitance 




8.0 


12.0 


pF 


V DS =-25V, V GS = 0V 
t=1 MHz 


c oss 


Common Source Output Capacitance 




5.0 


8.0 


Crss 


Reverse Transfer Capacitance 




1.6 


3.2 


'd(ON) 


Turn-ON Delay Time 




5.0 




ns 


V DD = -25V, l D = -10mA, 
R GEN = 25£2 


t, 


Rise Time 




5.0 




•dfOFF) 


Turn-OFF Delay Time 




8.0 






Fall Time 




5.0 




V SD 


Diode Forward Voltage Drop 






-1.5 


V 


V GS = 0V, l SD =-25mA 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 

3. Average current per channel, measured with all 8 channels connected in parallel. 



10-17 



OUTPUT 



\ 90%j/ 



'(ONI 



A 90% 90%^ 
jf- 10% 10%\_ 



Pin Configuration and Schematic 



G, 
NC 

G 2 
G 3 
G 4 
G 5 
G fi 



IE D 2 

lH D 3 

ill D 4 

m d 6 



D 7 
10 | S 



top view 
18-pin DIP 



10-18 



KULSt 




20 I 


D, 




NC 


18 | 


D 2 




D 3 




D 4 




D a 


J£] 


°a 




D 7 


jF] 


NC 


ZD 


D 8 



top view 
SOW - 20 



AP05 



Semicustom 8 P-Channel Monolithic 
High Voltage Array With Logic 

Ordering Information 



HV 0UT 
(Max) 


"out 
(Max) 


•oUTION) 

(Max) 


•oUT(OFF)* ® V OUT - 

100V Max 


'OUT(OFF)* ® V OUT - 

250V Max 


Order 
Number 1 


Package Options 


-160V 


700£2 


-15mA 


-1.5nA 




AP0516 


Available in Plastic DIP, 
Surface Mount SOIC, and Die. 


-320V 


700n 


-15mA 




-1.5nA 


AP0532 



* Average current per channel, measured with all eight channels connected in parallel, 
t Excluding package suffix. 



Features 

□ Custom logic control 

□ Low output leakage current 

□ ESD Input protection 

□ Interfaces directly to CMOS logic 

□ 8 independent channels 

□ Low crosstalk between channels 

□ Low power dissipation 

□ Free from scecondary breakdown 



General Description 

The Supertex AP05 series of semicustom high voltage mono- 
lithic devices consist of 8-channel open drain common source 
P-channel array with logic. The Logic configuration and packag- 
ing are determined by customer requirements. 

The AP0516 and AP0532 are ideally suited for low leakage/high 
impedance measurement, providing excellent accuracy and 
resolution for automatic test equipment. 



Applications 



□ High impedance/low leakage measurements 
for bare board testers 

□ Sample and hold circuits 

□ High voltage electrostatic array drivers 

□ Addressable multi-channel driver array 



Absolute Maximum Ratings 1 


Output Voltage, HV 0UT 


-320Vt 


Logic Supply Voltage, V DD 


+0.5Vto-18V 


Logic Input Voltage 


+0.5V to V DD -0.3V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature 2 


300°C 


Channel to Channel Crosstalk 


10mV/V 



Notes: 

1 . All voltages referenced to Vgs- 

2. Distance of 1 ,6mm from case for 1 seconds, 
t For AN0532 



Package Options 




16-Lead DIP 




SOW-20 



Note: Consult factory for other package options. 



10-19 



AP05 



Block Diagram 



Logic Input 
Controls 



Vss 





Custom 
Logic 



i 



Vdd 



Pin Configuration and Package 

Based on customer requirements 



-O HV 0ut O 



-O HV 0u ,1 



-O HV 0ul 2 



-O HV 0ul 3 



-O HV 0u ,4 



-O HV 0ul 5 



-O HV 0ul 6 



ST 



-O HV 0ul 7 



I 



10-20 



Supertex inc. 



HT01 



8-Channel Logic to High-Voltage 
Level Translator 



Ordering Information 



Device 


Package Options 


20 Lead C-DIP* 


20 Lead Plastic DIP 


Plastic SOW-20* 


Die 


HT01 


HT0130C 


HT0130P 


HT0130WG 


HT0130X 



• Same as SO-20 300 mil wide body. 
I Side brazed dual in-line package. 

Features 

□ Operating voltage up to 300V 

□ 5V to 15V logic input capability 

□ Output swings below GND if required 

□ Drives high-voltage P-channel MOS from logic level signal 
Surface mount packaging available 

□ No "floating logic" required 

□ 8 independent channels 

Applications 

□ ATE systems 

□ Printers/plotters 

□ P-channel MOSFET control 



Absolute Maximum Ratings 



1,2 



Supply Voltage, V DD 




V NN -0.3Vto+16V 


Supply Voltage, V PP 




V NN - 0.3V to + 300V 


Supply Voltage, V NN 




-16V to 0.3V 


Logic inputs levels 




V NN - 0.3V to V DD + 0.3V 




^OUTPUT 


V PP + 0.3V max 


l OUT — DC per Channel 


30mA 


Continuous total power dissipation 2 


700mW 


Operating temperature range 


0°C to 70°C 


Storage temperature range 


-65°Cto + 150°C 



1 : All voltages are referenced to chip ground. 

2: For operation above 25°C ambient derate linearly to 85°C at 8mw/°C. 



General Description 



The Supertex HT01 8-channel level translator is designed to 
implement necessary level translation between logic level signals 
and voltage swings required to drive high-voltage P-channel 
MOSFET transistors. This device is intended to provide gate drive 
signals to devices such as the Supertex AP01 P-channel MOSFET 
array in applications requiring active pull-up to a high-voltage (V pp ) 
line of up to 300 volts. Logic input can be from 5 volts to 15 volts 
and is referenced to the logic supply (V D0 ). 

When an input is switched to 4.2 volts below the V DD supply, the 
corresponding output will typically switch from V pp to V pp -1 4 volts. 
If the V pp supply remains above 1 2 volts, the negative supply (V NN ) 
would be connected to system ground (GND). If variations of the 
V pp supply level require the P-channel MOSFET gate drive to 
swing below GND in order to turn on, connect the V NN pin to a 
negative supply of up to -15 volts. The logic inputs can remain 
between V 0D and system ground (GND) and still provide correct 
operation. 

In an OFF condition, the HT01 is a low power device. In an ON 
condition, each channel will dissipate power determined by the V,^ 
and V NN voltage. Internal power dissipation must be considered 
when the application requires that more than one channel be 
active at one time, especially at higher V,,,, voltage values. 



Pin Configuration 




top view 
20-pin DIP/SOW 20 



10-21 



HT01 

Electrical Characteristics (over recommended operating conditions unless noted) 
DC Characteristics 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


Conditions 


Idd 


V DD Supply Current 






0.001 


mA 


All OFF 




0.6 


3.50 


mA 


1 ch ON, no load 


■pp 


Vpp Supply Current 






0.001 


mA 


All OFF 




0.4 


1.0 


mA 


1 ch ON, no load 


'nn 


V NN Supply Current 






0.001 


mA 


All OFF 




1.0 


4.50 


mA 


1 ch ON, no load 


I SOURCE 


Output Current 


135 


200 




MA 


Capacitive load 


•sink 


Output Current 


66 


100 




ma 


Capacitive load 


Von 


Output Voltage 


Vpp -17 




Vpp- 10 


V 


V DD = 4.75V 


V PP -17 




Vpp -12.5 


V 


V D0 =15V 


Voff 


Output Voltage 


Vp P - 0.5 






V 






Zener Voltage 


11 


14 


17 


V 


Output to V PP 


AC Characteristics 


Symbol 


Parameter 


Min 


Typ 


Max 


Units 


Conditions 


toN 


Turn on time, any channel 




5 




us 


V DD = 10V, V NN = GND 


AtoN 


Variation in t^, 
any 2 channels 




5 




% 


V DD = 10V, V NN = GND 


toFF 


Turn off time, any channel 




3 




us 


V DD = 10V, V NN = GND 


AtoFF 


Variation in t OFF , 
any 2 channels 




5 




% 


V DD = 10V, V NN = GND 



Recommended Operating Conditions* 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


V DD 


Logic supply voltage 


4.75 




15 


V 


Vpp 


Positive high voltage supply 


V NN + 12 




275 


V 


v NN 


Negative supply 


-15 







V 


V IH 


High-level input voltage 


V DD -1.2 




v DD 


V 


V,L 


Low-level input voltage 







V DD -4.2 


V 


T A 


Operating free-air temperature 







+70 


°C 



Power-up sequence V m , V DD , Vpp. 
Power-down sequence V PP , V 0D , V NN . 



Function Table 



Input Condition 


Output Stage 


High level 


V P p 


Low level 


V PP -V Z 



10-22 



Functional Block Diagram 



OVpp 



HT01 



<?V DI 



LOGIC LEVEL 
INPUT 



> 



INPUT 
LOGIC 



SOURCE 
CONTROL 



OUTPUT 



> 



SINK 
CONTROL 



ov NI 

(One of eight channels within the HT01) 



Switching Waveforms and Test Circuit 



V DD - 
INPUT 

Volts - 



OUTPUT 
Vpp-V z - 



50% 

Jseeh 



50% 



50% 



INPUT 



GND 



V PP 200V 




TEST POINT 

O 



V DD+ 15V — V NN 
(One of eight channels within the HT01) 



10-23 



TC0604WG 

Surface Mount 

Low Threshold 



Complementary Enhancement-Mode 
Vertical DMOS FET Quad Array 



Ordering Information 



BVoss/ 
BV TCS 


r ds (on) Max 
Q, + Q 2 or Q 3 -i- Q 4 


Order Number / Package 


SOW-20* 


40V 


3.0a 


TC0604WG 



" Same as SO-20 with 300 mil wide body. 



Features 

□ 4 independent channels 
C 4 electrically isolated die 

□ Commercial and military versions available 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Low C| SS and fast switching speeds 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Telecom switches 

□ Logic level interface 

□ Battery operated system 

□ Photo voltaic drive 

□ Soild state relays 

□ Motor control 



Thermal Characteristics 



Package 


Plastic 
SOW-20 


l D continuous 
& l DR (single die) 


N-Channel 


1.0A 


P-Channel 


-0.6A 


l D pulsed* 
& W 


N-Channel 


4.0A 


P-Channel 


-2.0A 


Power Dissipation @ T c = 25°C* 


1.5W 


e ia (°C/W)* 


85 


9jc(°C/W) 





Advanced DMOS Technology 

These enhancement-mode (normally-off) DMOS FET arrays 
utilize a vertical DMOS structure and Supertax's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex quad arrays use four independent DMOS transistors. 
They are ideally suited to a wide range of switching and amplify- 
ing applications where high breakdown voltage, high input im- 
pedance, low input capacitance, and fast switching speeds are 
desired. 



Electrical Characteristics 

Refer to TN06L and TP06L data sheets for detailed characteris- 
tics of N- and P-channel devices. 



Configuration 



Pulse test 300 uS pulse, 2% duty cycle. 
Total for package. 





El 




XI D 4 


e, 


LX 




js2 D 4 


D, 
G, 


LX 
LX 


P-Q, N-Q 4 


X] D 4 

ID g 4 


s, 


LX 




X] s 4 


S 2 
G 2 


LX 
LX 


N-Q 2 P-Q 3 


X] s 3 

X] G 3 


D 2 


LX 




XI D 3 


D 2 


LX 




X] D 3 


D 2 


LX 




X] D 3 






top view 








SOW-20 





10-24 



TN0604WG 

Supertax inc. Surface Mount 



Low Threshold 




N-Channel Enhancement-Mode 
» FE 



Ordering Information 



BV DSS / 
BV^s 


R DS(ON) MaX 


Order Number / Package 




SOW-20* 


40V 


1.0Q 


TN0604WG 



Same as SO-20 with 300 mil wide body. 



Features 

□ 4 independent channels 

□ 4 electrically isolated die 

□ Commercial and military versions available 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Low C| SS and fast switching speeds 

□ High input impedance and high gain 

Applications 

□ Telecom switches 

□ Logic level interface 

□ Battery operated system 

□ Photo voltaic drive 

□ Soild state relays 

□ Motor control 



Thermal Characteristics 



Package 


Plastic 
SOW-20 


l D continuous & l DR (single die) 


1.0A 


l D pulsed- & l DRM - 


4.0A 


Power Dissipation @ T c = 25°C* 


1.5W 


e la (°C/W)* 


85 


e„(°c/w) 





Advanced DMOS Technology 

These enhancement-mode (normally-off) DMOS FET arrays 
utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex quad arrays use four independent DMOS transistors. 
They are ideally suited to a wide range of switching and amplify- 
ing applications where high breakdown voltage, high input im- 
pedance, low input capacitance, and fast switching speeds are 
desired. 



Electrical Characteristics 

Refer to TN06L data sheet for detailed characteristics. 



Pin Configuration 



Pulse test 300 nS pulse, 2% duty cycle. 
Total for package. 





EE 




20 


D 4 


Bk 


EE 




EE] 


D 4 


D, 


EE 




jE 


D 4 


G, 


EE 




jE 


G 4 


s, 


EE 




EE] 


s 4 


s 2 


EE 




EE 


s 3 


G 2 


EE 




EE 


G 3 


D 2 


EE 




EE 


D 3 


D 2 


EE 




EE 


D 3 


D 2 


EE 




EE 


D 3 



EM 



10-25 



top view 
SOW-20 



TN0606N6 
TN0606N7 

Low Threshold 



1 



N-Channel Enhancement-Mode 
Vertical DMOS FET Quad Array 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


R DS(ON) 

(max) 




Order Number / Package 


BVogs 


14-Pin P-Dip 


14-Pln C-Dip* 


60V 


1.5£2 


TN0606N6 


TN0606N7 



* 14 pin side brazed ceramic DIP 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 



Features 

□ 4 independent channels 

□ 4 electrically isolated die 

O Commercial and military versions available 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Low C, ss and fast switching speeds 

□ High input impedance and high gain 



Applications 

□ Telecom switches □ Photo voltaic drive 

□ Logic level interface □ Soild state relays 

□ Battery operated systems □ Motor control 



Thermal Characteristics 



Package 


Plastic 
DIP 


Ceramic 
DIP 


l D continuous & l DH (single die) 


1.4A 


1.60A 


l D pulsed* & 'drm + 


6.0A 


6.0A 


Power Dissipation @ T c = 25°C* 


3W 


4W 


8 ja (°C/W)* 


83.3 


62.5 


e jc (°c/w>* 


41.6 


31.2 



* Pulse test 300 uS pulse, 2% duty cycle. 

* Total for package. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) DMOS FET arrays 
utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex quad arrays use four independent DMOS transistors. 
They are ideally suited to a wide range of switching and ampli- 
fying applications where high breakdown voltage, high input im- 
pedance, low input capacitance, and fast switching speeds are 
desired. 



Electrical Characteristics 

Refer to TN06A data sheet for detailed characteristics. 



Pin Configuration 



D, 


LX 




J±]D 4 


G, 


EE 






s, 


LX 






NC 


LX 




NC 


S 2 


ni 






G 2 


cx 




jOg 3 


D 2 






jOd 3 



top view 
14-pin DIP 



10-26 



TP0604WG 

\j£ jnCm Surface Mount 

Low Threshold 



P-Channel Enhancement-Mode 

Ordering Information 




BV DSS / 
BV DGS 


R DS(ON) MaX 


Order Number / Package 


SOW-20* 


-40V 


2.on 


TP0604WG 



* Same as SO-20 with 300 mil wide body. 

Features 

□ 4 independent channels 

□ 4 electrically isolated die 

□ Commercial and Military versions available 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Low C| SS and fast switching speeds 

□ High input impedance and high gain 



Applications 

□ Telecom switches 

□ Logic level interface 

□ Battery operated systems 

□ Photo voltaic drive 

□ Soild state relays 

□ Motor control 



Thermal Characteristics 



Package 


Plastic 
SOW-20 


l D continuous & l DR (single die) 


-0.6A 


l D pulsed* & l DRM * 


-2.0A 


Power Dissipation @ T = 25°C* 


1.5W 


e ja (°c/w)* 


85 


e ic (°c/w) 





* Pulse test 300 uS pulse, 2% duty cycle. 

* Total (or package. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) DMOS FET arrays 
utilize a vertical DMOS structure and Supertax's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex quad arrays use four independent DMOS transistors. 
They are ideally suited to a wide range of switching and ampli- 
fying applications where high breakdown voltage, high input im- 
pedance, low input capacitance, and fast switching speeds are 
desired. 



Electrical Characteristics 

Refer to TP06L data sheet for detailed characteristics. 



Pin Configuration 





Cl 




20 | 


D 4 


B| 


CX 






D 4 


01 


LX 






D 4 


a, 


UL 




17 | 


G 4 


s, 


\3L 






s 4 


s 2 


nx 




3D 


s 3 


G 2 






J±} 


G.3 


D 2 


EL 




JB 


D 3 


D 2 


LX 




3D 


D 3 


D 2 






3D 


D 3 



top view 

20-pin DIP 
SOW 20 



10-27 



TP0606N6 
TP0606N7 

Low Threshold 




P-Channel Enhancement-Mode 
DMOS FET Quad Array 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV TCS 


"dS(ON) 

(max) 


Order Number / Package 


14-Pin P-Dip 


14-Pin C-Dip* 


-60V 


3.50 


TP0606N6 


TP0606N7 



* 14 pin side brazed ceramic DIP 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ 4 independent channels 

□ 4 electrically isolated die 

□ Commercial and Military versions available 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Low C| SS and fast switching speeds 

□ High input impedance and high gain 

Applications 

□ Telecom switches 

□ Logic level interface 

□ Battery operated systems 

□ Photo voltaic drive 

□ Soild state relays 

□ Motor control 

Thermal Characteristics 



Package 


Plastic 
DIP 


Ceramic 
DIP 


l D continuous & l DR (single die) 


-0.65A 


-0.75A 


l D pulsed* & l DRM * 


-3.5A 


-3.5A 


Power Dissipation @ T c = 25°C* 


3W 


4W 


9 ja (°C/W)* 


83.3 


62.5 


9 jc (°C/W)t 


41.6 


31.2 



♦ Pulse test 300 |iS pulse, 2% duty cycle. 
+ Total for package. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) DMOS FET arrays 
utilize a vertical DMOS structure and Supertax's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex quad arrays use four independent DMOS transistors. 
They are ideally suited to a wide range of switching and ampli- 
fying applications where high breakdown voltage, high input im- 
pedance, low input capacitance, and fast switching speeds are 



Electrical Characteristics 

Refer to TP06A data sheet for detailed characteristics. 

Pin Configuration 



D, 


LX 




jH 


D 4 


Qi 


LX 




jE 




Si 


LX 




4p 


s< 


NC 


LX 




ZD 


NC 


S 2 


LX 




JO] 


s 3 


G 2 


LX 




X] 




D 2 


LX 




±2 


D 3 



top view 
14-pin DIP 



10-28 



Qf) Supertexinc. 



TQ3001 VQ3001 
VQ7254 

Surface Mount 



N- and P-Channel Quad Power 
MOSFET Arrays 



Ordering Information 

Standard Commercial Devices 



BV DSS / 
BV DGS 


^DS (ON) 

(max) 
Q1 + Q2 or 
Q3 + Q4 


as (tii) 
(max) 


Order Number / Package 


N-Channel 


P-Channel 


14-Pin P-Dip 


14-Pin C-Dip* 


20 Terminal 
LCC Quad 


40V 


3£2 


2.0V 


-3.0V 


VQ3001 N6 


VQ3001N7 


VQ3001NF 


40V 


3Q 


1.6V 


-2.4V 


TQ3001N6 


TQ3001N7 


TQ3001NF 


20V 


3Q. 


2.0V 


-3.0V 


VQ7254N6 


VQ7254N7 





* 14 pin side brazed ceramic DIP 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

C Low C, ss and fast switching speeds 

□ Excellent thermal stability 

I Integral Source-Drain diode 

□ High input impedance and high gain 

_ Complementary N- and P-channel devices 

□ Low threshold version available 



Advanced DMOS Technology 

These enhancement-mode (normally-off) DMOS FET arrays 
utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex quad arrays use four independent DMOS transistors. 
They are ideally suited to a wide range of switching and ampli- 
fying applications where high breakdown voltage, high input im- 
pedance, low input capacitance, and fast switching speeds are 
desired. 



Applications 

□ Telecom switches 
•□ Logic level interface 

□ Battery operated systems 



□ Photo voltaic drive 

□ Soild state relays 

□ Motor control 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±30V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 


* Distance of 1 .6 mm from case for 1 seconds. 



10-29 



Plastic Dip 



1.4A 



-0.65A 



3.0A 



-3.0A 



1.5W 



83.3 



1.4A 



-0.65A 



3.0A 



-3.0A 



20 Terminal 
LCC 



410mA 



■300mA 



3.0A 




-3.0A 




LOW 



J 



125.0 




410mA 



-300mA 



3.0A 



-3.0A 



"Total for 4 die. 
T Each die. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


N-Channei 


P-Channel 


Unit 


Test Conditions 


Min 


Max 


Min 


Max 


BV DSS 


Drain-to- Source 


TQ3001 


40 




-40 




V 


V GS = 0, l D = 10uA 


Breakdown Voltage 


VQ3001 


VQ7254 


20 




-20 






Gate Threshold Voltage 


VQ3001 


8 


2.0 


-0.8 


-3.0 


v 


v _ w 1-1 mA 

V GS V DS' 'D 

T A = 25°C 


VQ7254 


TQ3001 


0.6 


1.6 


-1.0 


-2.4 


V 


VQ7254 


0.5 




-0.65 




V 


v gs = v ds. I D = 1mA 
T A = 85°C 


'gss 


Gate Body Leakage 




100 




-100 


nA 


V GS = ±16V, V DS = 0V 


loss 


Zero Gate Voltage Drain Current 




10 




-10 


uA 


V GS = 0V, V DS = 0.8 Min. Rating 




500 




-500 


HA 


V GS = 0V, V DS = 0.8 Min. Rating, 
T A = 125°C 


Vos (on) 


Total Static 
Drain-to-Source 
ON-State Voltage 


VQ3001 




1.0 




-2.0 


V 


V GS = 11.4V, l D = 1A 


TQ3001 


VQ7254 




1.0 




-2.0 


RdS (ON) 


Total Static 
Drain-to-Source 
ON-State Resistance 


TQ3001 




1.5 




3.5 


a 


V QS = 5.0V, l D = 250mA 


VQ3001 




1.0 




2.0 


V^o = 11 4V In = 1A 


TQ3001 


VQ7254 




1.0 




2.0 


Gfs 


Forward Transconductance 


200 




200 




mU 


V DS = 10V. I D = 0.5A 


C|SS 


Input Capacitance 




190 




195 


pF 


V GS = 0V, V DS = 20V 
f = 1Mz 


Coss 


Output Capacitance 




110 




120 


Crss 


Reverse Transfer Capacitance 




50 




60 


•(ON) 


Turn-ON Time 




30 




30 


ns 


V D0 = 15V, l D = 0.65A, 
Rqen = 25n 


tfOFF) 


Tum-OFF Time 




30 




30 


ns 


Vso 


Forward ON Voltage 


VQ7254 




1.8 




-2 


V 


V GS = 0V, l F = 1 .5A 


VQ3001 


1.8 




-2 


V GS = 0V, l F =1.5A 


TQ3001 



1. All D.C. parameters 100% tested (pulse test: 300us pulse, 2% duty cycle). 

2. All A C. parameters sample tested. 

3. Refer to device types TN06L and TP06L for characteristic curves. 



10-30 



Switching Waveforms and Test Circuit 



OUTPUT 




PULSE 
GENERATOR 



TQ3001 , VQ3001 , VQ7254 

Vn, 



■o OUTPUT 




FET polarity in test 




only. 



Pin Configurations 



NC 


19 


s 4 


20 




1 


NC 


2 




3 



G, NC D„ S 3 NC 
18 17 16 15 14 



NQ, 



4 5 



NQ, 



PQ 2 



\ 




D, 


13 




% 


12 


NC 


G, 






NC 


11 




G 2 


10 


s, 


S 2 


9 


NC 


D 2 


/ 









top view 
14-pin DIP 



10-31 



VC0106N6 
VC0106N7 



Complementary Enhancement-Mode 
Vertical DMOS FET Quad Array 



Ordering Information 

Standard Commercial Devices 



BVdss/ 


Ros(ON)(max) 
Q1 + Q2 or Q3 + Q4 


Order Number / Package 


14-Pin P-Dip 


14-Pin C-Dip* 


60V 


11£2 


VC0106N6 


VC0106N7 



* 14-pin Side Brazed Ceramic Dip. 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ 4 independent channels 

□ 4 electrically isolated die 

□ Commercial and military versions available 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Low C, ss and fast switching speeds 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control □ Amplifiers 

□ Converters □ Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Thermal Characteristics 



Package 


Plastic 
DIP 


Ceramic 
DIP 


l D continuous 
& l Dn (single die) 


N-Channel 


0.56A 


0.7A 


P-Channel 


-0.35A 


-0.4A 


l D pulsed* 


N-Channel 


2.0A 


2.0A 


P-Channel 


-1.0A 


-1.0A 


Power Dissipation @ T c = 25°C* 


2W 


3W 


6 ia (°C/W)* 


110 


83.3 


e jc (°c/w)* 


62.5 


41.6 



+ Pulse test 300 uS pulse, 2% duty cycle. 
* Total for package. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) DMOS FET arrays 
utilize a vertical DMOS structure and Supertax's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex quad arrays use four independent DMOS transistors. 
They are ideally suited to a wide range of switching and ampli- 
fying applications where high breakdown voltage, high input im- 
pedance, low input capacitance, and fast switching speeds are 
desired. 



Electrical Characteristics 

Refer to VN01 A and VP01 A data sheets for detailed characteris- 
tics of N- and P-channel devices. 



Pin Configuration 




d 2 nz 



top view 
14-pin DIP 



10-32 



VN0104N6/ VN0104N7 
VN0106N6/ VN0106N7 



N-Channel Enhancement-Mode 




Ordering Information 

Standard Commercial Devices 



BV DSS / 


^DS(ON) 

(max) 


Order Number / Package 


BV DGS 


14-Pin P-Dip 


14-Pin C-Dip* 


40V 


3£l 


VN0104N6 


VN0104N7 


60V 


3£2 


VN0106N6 


VN0106N7 



* 14-pin Side Brazed Ceramic Dip. 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ 4 independent channels 

□ 4 electrically isolated die 

□ Commercial and military versions available 
] Free from secondary breakdown 

Low power drive requirement 

□ Low C, ss and fast switching speeds 

□ High input impedance and high gain 

Applications 

□ Motor control □ Amplifiers 

□ Convenors □ Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Thermal Characteristics 



Package 


Plastic 
DIP 


Ceramic 
DIP 


l D continuous & l DR (single die) 


0.56A 


0.7A 


l D pulsed* & l DRM * 


2.0A 


2.0A 


Power Dissipation @ T c = 25°C* 


2W 


3W 


e ia (°cav)* 


110 


83.3 


e ic (°c/w)* 


62.5 


41.6 



* Pulse test 300 u,S pulse, 2% duty cycle. 

* Total for package. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) DMOS FET arrays 
utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex quad arrays use four independent DMOS transistors. 
They are ideally suited to a wide range of switching and ampli- 
fying applications where high breakdown voltage, high input im- 
pedance, low input capacitance, and fast switching speeds are 
desired. 



Electrical Characteristics 

Refer to VN01A data sheet for detailed characteristics. 

Pin Configuration 




top view 
14-pin DIP 



ill] 



10-33 



VP0104N6/VP0104N7 
VP0106N6/ VP0106N7 




P-Channel Enhancement-Mode 



Ordering Information 

Standard Commercial Devices 



BVdss/ 


"ds<on) 
(max) 


Order Number / Package 


BV DGS 


14-Pin P-DIP 


14-Pin C-DIP* 


-40V 


8n 


VP0104N6 


VP0104N7 


-60V 


8£2 


VP0106N6 


VP0106N7 



' 14-pin Side Brazed Ceramic DIP. 



Features 



□ 4 independent channels 

□ 4 electrically isolated die 

□ Commercial and military versions available 

□ Free from secondary breakdown 

□ Low power drive requirement 

Z Low C, ss and fast switching speeds 

□ High input impedance and high gain 



□ Amplifiers 

□ 



Applications 

□ Motor control 

□ Convenors 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 



Thermal Characteristics 



Package 


Plastic 
DIP 


Ceramic 
DIP 


l D continuous & l DR (single die) 


-0.35A 


-0.4A 


l D pulsed* & l DRM + 


-1.0A 


-1.0A 


Power Dissipation @ T c = 25°C* 


2W 


3W 


e ]a (°C/W)* 


110 


83.3 


9 jc (°C/W)* 


62.5 


41.6 



* Pulse lest 300 uS pulse, 2% duty cycle. 

* Total for package. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) DMOS FET arrays 
utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex quad arrays use four independent DMOS transistors. 
They are ideally suited to a wide range of switching and amplifying 
applications where high breakdown voltage, high input imped- 
ance, low input capacitance, and fast switching speeds are de- 
sired. 



Electrical Characteristics 

Refer to VP01 A Data Sheet for detailed characteristics. 



Pin Configuration 



D, 


nz 




J±2 D„ 


G, 


EH 




3D g 4 


s, 


EC 




jEI s 4 


NC 


CC 




dD nc 


S 2 


LX 




s 3 


G 2 






ID G 3 


D 2 






T3 d 3 



top view 
14-pin DIP 



10-34 



. VQ1000 

Supertex inc. 



N-Channel Enhancement-Mode 
Vertical DMOS FET Quad Array 



Ordering Information 

Standard Commercial Devices 





"ds<on) 


'd(ON) 


Order Number / Package 




(max) 


(mln) 


14-Pin P-DIP 


14-Pln C-DIP* 


60V 


5.5£2 


0.5A 


VQ1000N6 


VQ1000N7 



* 14 pin side brazed ceramic DIP 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 



Features 

□ Very high input impedance 

□ Very high speed 

□ Low on-resistance 

G No secondary breakdown 
B High reliability 



Advanced DMOS Technology 

These enhancement-mode (normally-off) DMOS FET arrays 
utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex quad arrays use four independent DMOS transistors. 
They are ideally suited to a wide range of switching and amplifying 
applications where high breakdown voltage, high input imped- 
ance, low input capacitance, and fast switching speeds are de- 
sired. 



Applications 

□ Logic to high current interface 

□ High speed line driver 

□ LED digit strobe driver 

□ Linear amplifiers 

n Stepper motor drive 



Absolute Maximum Ratings 

Drain-to-Source Voltage 



Drain-to-Gate Voltage 


BVogs 


Gate-to-Source Voltage 


+ 30V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 



Pin Configuration 





EE 


w 


3D 


D 4 


s, 


LH 




m 


s 4 


G, 


LX 




3D 


G 4 


NC 


LX 




3D 


NC 


G 2 


DI 




JE 


G 3 


S 2 


m 




U 


s 3 


D 2 






<±3 


D 3 



top view 
14-pin DIP 



• Distance of 1 .6 mm from case for 10 seconds. 



10-35 



VQ1000 



Thermal Characteristics (@ t a = 25°c) 



Test 


Unit 


Each Transistor 


All four Transistors 


VQ1000N7 


Total Power Dissipation 


Watts 


1.30 


2.0 


Thermal Resistance 


°C/W 


96.2 


62.5 


Thermal Coupling Factor (K) 
Q, - Q 4 or Q 2 - Q 3 
Q,-Q 2 ,Q 3 -Q 4 , Q,-Q 3 or Q 4 -Q 2 


% 
% 


60 
50 




Continuous Drain Current 2 - 3 


A 




0.225 




Pulsed Drain Current '» 3 


A 


1.0 


_ 



Notes: 



1 . All D.C. parameter 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300 us, 2% duty cycle.) 

2. I D (continuous) is limited by max rated T,. 

3. T C = 25°C. 



Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


' 

Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DS s 


Drain-to-Source Breakdown Voltage 


60 






V 


V GS = 0V, l D = 100uA 


^GS(tfi) 


Gate Threshold Voltage 


0.8 




2.5 


V 


V GS = V DS , l D = 10mA 


A ^GS(th) 


Change in V GS(th) with Temperature 




-3.0 


-5.0 


mV/°C 


v gs = v ds. b = 1-OmA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±20V, V DS = 0V 


loss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0V, V DS = Max Rating 






500 


V GS = 0, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


0.5 






A 


V GS =10V, V DS = 25V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 






7.5 


a 


V GS = 5V, l D = 0.2A 






5.5 


V GS = 10V. I D = 0.3A 


AR DS(ON) 


Change in Rqsion; w '' n Temperature 




0.6 


1.1 


%/°c 


V GS = 10V, l D = 0.3A 


G FS 


Forward Transconductance 


100 






mu 


V DS = 10V, l D = 0.5A 


C|SS 


Input Capacitance 






60 


PF 


V GS = 0V, V DS = 25V, f = 1 MHz 


c oss 


Common Source Output Capacitance 






25 


Crss 


Reverse Transfer Capacitance 






5 


•(ON) 


Turn-ON Time 






10 


ns 


V DD = 15V, l D = 0.6A 
R GEN = 50£1 


'(OFF) 


Turn-OFF Time 






10 


V SD 


Diode Forward Voltage Drop 




0.85 




V 


V GS = 0, l SD = 0.5A 


trr 


Reverse Recovery Time 




165 




ns 


V GS = 0, l SD = 0.3A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



10-36 



VQ1000 



Thermal Coupling and Effective Thermal Resistance 



In multiple chip devices, coupling of heat between die occurs. The 
junction temperature can be calculated as follows: 

A Tj1 = ^81 PD1 + ^92 ^62 PD2 + ^83 ^83 ^03 + ^84 ^84 ^04 (') 

where AT,, is the change injunction temperature of die 1 . 

R 81 thru 4 is the thermal resistance of die 1 through 4. 

P D1 thru 4 is the power dissipated in die 1 through 4. 

K e2 thru 4 is the thermal coupling between die 1 and die 2 
through 4. 

An effective package thermal resistance can be defined as 
follows: 



Re (EFF) - A Tj,/P 0T 
where P DT is the total package power dissipation. 



(2) 



Assuming equal thermal resistance for each die, equation (1) 
simplifies to: 

ATj, = R e i(Ppi + Ke2 Pd2 + Ke3 Pd3 + K« Pew) (3) 
For conditions where P D1 = P D2 = P D3 = P^, P DT = 4P D , equation 
(3) can be further simplifed and, by substituting into equation (2), 
results in: 



R9 (EF F) = Rei + K«2 + K93 + KmV^ 



(4) 



Values for the coupling factors when the ambient is used as a 
reference are given in the previous table. If significant power is to 
be dissipated in two die, die at the opposite ends of the package 
should be used so that lowest position junction temperatures will 
result. 



Drain-Source Diode (t^ - Reverse Recovery Time) 

The internal drain-source diodes of DMOS FETs may be used as 
catch diodes or free-wheeling diodes. Current ratings for these 
diodes are the same as the contnuous and peak drain current 
ratings for the DMOS FET. 



Reverse recovery time is measured using the circuit below. 
Forward and reverse current l F and l R are equal and are tested at 
the continuous and peak current ratings of the DMOS FET. 



Switching Waveforms and Test Circuits 



20ns, 0.1% » 
Duty Cycle 




-30V 

•R s chosen for correct l F and l R 




EM 



T„ Test Waveforms 




PULSE WIDTH 



20db Sa ^Jf 
50£2 Attenuator ocope 

1 fix 



INPUT 



OUTPUT 



J/ 90% 90% -"t 

i '50% \so 
10% \ 

'(ON) 



50% 
■10% 

W) 



0% 




■90% 



Switching Time Test Circuit 



Switching Time Test Waveform 



10-37 



Typical Performance Curves 



VQ1000 



Output Characteristics 



Saturation Characteristics 



CL 

E 





Trr 
111 














3 = 7\ 




J 

1 


}l * 


















11 
















6V 




-A 


/ 


































5V 








































4V 








































3V 




















2V 

























10 20 30 40 50 

V DS (volts) 
Static Transfer Characteristics 




V GS (volts) 
Output Conductance vs. Drain Current 



I ^ 

8 











































V DS = 1UV 

300ns, 2% 
















D 
P 


Jty C) 
jlse T 


cle 
est 








Redi 

due 

heat 


ctic 


ng 


n 


> 











































































































0.1 

l D (amps) 



0.8 

Q. 

E 

-9 0.4 
0.2 







v c 


1 

S = 1 




'A 




7V 
















2* 
















/ 


r — 








6V 








4 




— ^ 
















/4 
/# 


r 










5V 








































4V 






































3V 


















2V 




) 


2 








c 




1 




1( 



V DS (volts) 
Transconductance vs. Drain Current 



250 



200 



^ 150 
E. 

□5 100 



50 





































































































































\ 




= 10 


V 














300us, 2% 
Duty Cycle 
















3 uls 


3 Te 


St 

























200 400 600 800 1000 

Id (mA) 

Transconductance vs. Gate-Source Voltage 



200 



S 150 

E. 

<5 100 



50 







































































































































V 


nc — 


10V 
















300us, 2% 

Hutu P.w^lo 














p 


ulse 


Tes 


t 























1.0 



2 4 6 8 10 

V GS (volts) 



10-38 



VQ1000 

Typical Performance Curves 



Drain-to-Source ON Resistance Capacitance vs. Drain-to-Source Voltage 

vs. Gate-to-Source Voltage 




nOitS'lUBllf IOC 1< " 20 30 40 50 

t - Time (ns) 



10-39 



VQ1001 



1 



N-Channel Enhancement-Mode 
Vertical DMOS FET Quad Array 



Ordering Information 

Standard Commercial Devices 



BV DSs' 

BVogs 


"ds<on) 
(max) 


'□(ON) 

(min) 


Order Number / Package 


Quad Ceramic DIP* 


30V 


1.0£2 


2.0A 


VQ1001P 



* 14 pin side brazed ceramic DIP 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 
C Ease of paralleling 

□ Low C| SS and fast switching speeds 

□ Excellent thermal stability 
Z Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 



Applications 



□ Motor control 

□ Convenors 
Z Amplifiers 

□ Switches 

Z Power supply circuits 

Z Driver (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage 



BV n 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±30V 


Operating and Storage Temperature 


-55Xto+150 : C 


Soldering Temperature* 


300°C 


* Distance of 1.6 mm from case for 10 seconds. 



Advanced DMOS Technology 

These enhancement-mode (normally-off) DMOS FET arrays 
utilize a vertical DMOS structure and Supertax's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex quad arrays use four independent DMOS transistors. 
They are ideally suited to a wide range of switching and amplifying 
applications where high breakdown voltage, high input imped- 
ance, low input capacitance, and fast switching speeds are de- 
sired. 



Pin Configuration 









D 4 






ZD 


S 4 


G 'LX 




jE 


G 4 


NC [^ 




m 


NC 








Q 3 






ID 


S 3 






T3 


D 3 



top view 
14-pin DIP 



VQ1001 



Thermal Characteristics 



Test 


Unit 


Each Transistor 


All Four Transistors 


VQ1001P 


VQ1001P 


Total Power Dissipation 


Watts 


1.3 


2.0 


Thermal Resistance 


°C/W 


96.2 


62.5 


Continuous Drain Current 


A 


0.85 




Pulsed Drain Current 


A 


3.0 





Electrical Characteristics (@ 25°c unless otherwise specified) 



Cumhnl 
Oy 


Paramotor 
rcJiailltrltfl 


Min 


Typ 


Max 


Unit 


Conditions 

V*UI IHI IIUI id 


BV DSS 


L/r all 1 l(J OUUItc DiUclftUUvvl 1 v uiidyc 


30 






V 


V GS = 0V, l D = 10uA 


v GS(th) 


(*^atd "Throchnlrl \/oltano 
ualc 1 IMfcJoMUlU VUlldyc 


0.8 




2.5 




V GS — V DS ' 'D — 


1 

'gss 








100 


nA 


V GS — — ,ov ' V DS~ UV 


'dss 


Zero Gate Voltage Drain Current 






10 


uA 


V GS = 0V, V DS = Max Rating 


500 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 125°C 


b(ON) 


ON-State Drain Current 


2 






A 


V GS = 12V,V DS = 10V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 






1 


a 


V GS =12V, l D = 1 .OA 


G FS 


Forward Transconductance 


200 






mU 


V DS = 10V, l D = 0.5A 


C|SS 


Input Capacitance 






110 


PF 


V GS = 0. V DS = 15V,f=1 MHz 


*-"OSS 


Common Source Output Capacitance 






110 


C RSS 


Reverse Transfer Capacitance 






35 


l (ON) 


Turn-ON Time 






30 


ns 


V DD = 15V, l D = 0.6A 

^gen - 25n 


'(OFF) 


Turn-OFF Time 






30 


v SD 


Diode Forward Voltage Drop 




0.85 




V 


V GS = 0, l SD = 1A 



am 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




10-41 



VQ1004 



N-Channel Enhancement-Mode 
Vertical DMOS FET Quad Array 



Ordering Information 

Standard Commercial Devices 



BV DSS / 


" DS<ON) 

(max) 


'd(ON) 

(min) 


Order Number / Package 




Quad Ceramic DIP* 


Quad Plastic DIP 


60V 


3.5£2 


1.5A 


VQ1004P 


VQ1004J 



* 14 pin side brazed ceramic DIP 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

Z Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C, ss and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Convertors 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


+ 30V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 



Advanced DMOS Technology 

These enhancement-mode (normally-off) DMOS FET arrays 
utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex quad arrays use four independent DMOS transistors. 
They are ideally suited to a wide range of switching and amplifying 
applications where high breakdown voltage, high input imped- 
ance, low input capacitance, and fast switching speeds are de- 
sired. 



Pin Configuration 




top view 

14-pin DIP 



Distance of 1 .6 mm from case for 10 seconds. 



10-42 



VQ1004 



Thermal Characteristics 



Test 


Unit 


Each Transistor 


All Four Transistors 


VQ1004P 


VQ1004J 


VQ1004P 


VQ1004J 


Total Power Dissipation 


Watts 


1.3 


1.3 


2.0 


2.0 


Thermal Resistance 


°C/W 


96.2 


96.2 


62.5 


62.5 


Continuous Drain Current 


A 


0.46 


0.46 






Pulsed Drain Current 


A 


2.0 


2.0 







Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source Breakdown Voltage 


60 






V 


V GS = 0V, l D = 10uA 


V GS(th) 


Gate Threshold Voltage 


0.8 




2.5 


V 


V GS = V DS- 'd= 1mA 


'gss 


Gate Body Leakage 






100 


nA 


V GS = ±15V,V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






1 




V GS = 0V, V DS = Max Rating 










500 


uA 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


1.5 






A 


V GS = 10V,V DS = 10V 


R DS(ON) 


Static Drain-to-Source 
ON-State Resistance 






5 


a 


V GS = 5V, l D = 0.3A 








3.5 


V GS =10V, l D = 1.0A 


G FS 


Forward Transconductance 


170 






mfJ 


V DS = 10V, l D = 0.5A 


C ISS 


Input Capacitance 






60 






c oss 


Common Source Output Capacitance 






50 


PF 


V GS = 0V, V DS = 15V,f = 1 MHz 


Crss 


Reverse Transfer Capacitance 






10 






'(ON) 


Turn-ON Time 






10 


ns 


V DD = 25V, l D = 1A 
R GEN = 25£i 


'(OFF) 


Turn-OFF Time 






10 




V SD 


Diode Forward Voltage Drop 




0.9 




V 


V GS = 0, l SD = 1A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 




10-43 



VQ2001 



MS 

at! 



P-Channel Enhancement-Mode 
Vertical DMOS FET Quad Array 



Ordering Information 



BVpss/ 
BVdgs 


R DS<ON) 

(max) 


•iXON) 

(mln) 


Order Number / Package 


Quad Ceramic DIP* 


-30V 


2.0SI 


-1.5A 


VQ2001P 



14-pin side-brazed ceramic DIP. 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 

□ Ease of paralleling 

□ Low C| SS and fast switching speeds 

□ Excellent thermal stability 
Z Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Converters 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 

Absolute Maximum Ratings 

Drain-to-Source Voltage BV D 



* Distance of 1 .6 mm from case for 1 seconds. 



Drain-to-Gate Voltage 


BV Des 


Gate-to-Source Voltage 


±30V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 



Advanced DMOS Technology 

These enhancement-mode (normally-off) DMOS FET arrays 
utilize a vertical DMOS structure and Supertax's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertax quad arrays use four independent DMOS transistors. 
They are ideally suited to a wide range of switching and amplifying 
applications where high breakdown voltage, high input imped- 
ance, low input capacitance, and fast switching speeds are de- 
sired. 



Pin Configuration 



M 






J4]D 4 


s i 


2 






M 


3 




3D G 4 


NC 


4 




~TT~l nc 


M 


5 




jEI g 3 


M 


~6~ 






M 






ZO°3 



top view 
14-pin DIP 



10-44 



VQ2001 



Thermal Characteristics <t a =25°c) 



Test 


Unit 


Each Transistor 


All Four Transistors 


Total Power Dissipation 


Watts 


1.3 


2.0 


Thermal Resistance 


°C/W 


96.2 


62.5 


Continuous Drain Current 


A 


-0.6 




Pulsed Drain Current 


A 


-2.0 





Electrical Characteristics (@ 25°c unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source Breakdown Voltage 


-30 






V 


V GS = 0V, V DS =-10uA 


V GS(th) 


Gate Threshold Voltage 


-1.4 


-1.8 


-4.5 


V 


v gs = v ds. I D = -1mA 


'gss 


Gate Body Leakage 






-100 


nA 


V GS = +15V, V DS = 0V 


loss 


Zero Gate Voltage Drain Current 






-10 


uA 


V GS = 0V, V DS = Max Rating 






-500 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


-1.5 






A 


V QS = -12V, V DS = -10V 


^DS(ON) 


Static Drain-to-Source ON-State Resistance 




1.5 


2.0 


a 


V GS = -12V, l D = -1A 


G FS 


Forward Transconductance 


200 






ml3 


V DS = -10V, l D = -0.5A 




Input Capacitance 






150 


pF 


V GS = 0V, V DS = -25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 






120 


C RSS 


Reverse Transfer Capacitance 






60 


l (ON) 


Turn-ON Time 








30 


ns 


V DD = -15V, l D = -0.6A 
R GEN = 25£i 


'(OFF) 


Turn-OFF Time 






30 


ns 


V SD 


Diode Forward Voltage Drop 






-1.8 


V 


V GS = 0, l S D = -1A 



Hi] 



Notes: 

1 . All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300us pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 

Switching Waveforms and Test Circuit 



ov 



INPUT 



'(ON) 



td(ON) t, 



J^0% 



'd(OFF) >F 



90% 90%T 




10-45 



VQ2006 




P-Channel Enhancement-Mode 
Vertical DMOS FET Quad Array 



Ordering Information 



BVdss/ 
BV DGS 


R DS(ON) 

(max) 


'd(ON) 

(min) 


Order Number / Package 


Quad Ceramic DIP* 


-90V 


son 


-1.0A 


VQ2006P 



14-pin side-brazed ceramic DIP. 

High Reliability Devices 

See pages 5-4 and 5-5 for MILITARY STANDARD Process 
Flows and Ordering Information. 

Features 

□ Free from secondary breakdown 

□ Low power drive requirement 
Z Ease of paralleling 

□ Low C| SS and fast switching speeds 

□ Excellent thermal stability 

□ Integral Source-Drain diode 

□ High input impedance and high gain 

□ Complementary N- and P-channel devices 

Applications 

□ Motor control 

□ Convenors 

□ Amplifiers 

□ Switches 

□ Power supply circuits 

□ Driver (relays, hammers, solenoids, lamps, 
memories, displays, bipolar transistors, etc.) 



Absolute Maximum R< 


itings 


Drain-to-Source Voltage 


BV DSS 


Drain-to-Gate Voltage 


BV DGS 


Gate-to-Source Voltage 


±30V 


Operating and Storage Temperature 


-55°Cto+150°C 


Soldering Temperature* 


300°C 



Advanced DMOS Technology 

These enhancement-mode (normally-off) DMOS FET arrays 
utilize a vertical DMOS structure and Supertex's well-proven 
silicon-gate manufacturing process. This combination produces 
devices with the power handling capabilities of bipolar transistors 
and with the high input impedance and positive temperature 
coefficient inherent in MOS devices. Characteristic of all MOS 
structures, these devices are free from thermal runaway and 
thermally-induced secondary breakdown. 

Supertex quad arrays use four independent DMOS transistors. 
They are ideally suited to a wide range of switching and amplifying 
applications where high breakdown voltage, high input imped- 
ance, low input capacitance, and fast switching speeds are de- 
sired. 



Pin Configuration 





















nc n~ 




TT| n c 


G 2 [H 



















top view 
14-pin DIP 



Distance of 1 .6 n 



10-46 



VQ2006 



Thermal Characteristics (t a =25°c) 



Test 


Unit 


Each Transistor 


All Four Transistors 


Total Power Dissipation 


Watts 


1.3 


2.0 


Thermal Resistance 


°C/W 


96.2 


62.5 


Continuous Drain Current 


A 


-0.41 




Pulsed Drain Current 


A 


-3.0 





CieCiriCal V^naraUlCriSIICS (@ 25°C unless otherwise specified) 



Symbol 


Parameter 


Min 


Typ 


Max 


Unit 


Conditions 


BV DSS 


Drain-to-Source Breakdown Voltage 


-90 






V 


V GS = 0V, V DS =-10uA 




Gate Threshold Voltage 


-1.4 


-1.8 


-4.5 


V 


V GS = V DS , l a = -1mA 


'gss 


Gate Body Leakage 






-100 


nA 


V GS = ±30V, V DS = 0V 


'dss 


Zero Gate Voltage Drain Current 






-10 


uA 


V GS = 0V, V DS = Max Rating 


-500 


V GS = 0V, V DS = 0.8 Max Rating 
T A = 125°C 


'd(ON) 


ON-State Drain Current 


-1.0 






A 


V GS = -10V, V DS = -10V 


R DS(ON) 


Static Drain-to-Source ON-State Resistance 




2.5 


5.0 


£2 


V GS = -10V, l„ = -1A 


Gfs 


Forward Transconductance 


200 






m V 


V DS = -10V, l D = -0.5A 


Ciss 


Input Capacitance 






150 


pF 


V ss = ov . V DS = -25V 
f = 1 MHz 


Coss 


Common Source Output Capacitance 






65 


C RSS 


Reverse Transfer Capacitance 






25 


tr 


Rise Time 






15 


ns 


V DD = -25V, l D = -0.5A 
R GEN = 25£2 


'd(ON) 


Turn-ON Delay Time 






40 


tf 


Fall Time 






30 


'd(OFF) 


Turn-OFF Delay Time 






30 


v SD 


Diode Forward Voltage Drop 






-1.8 


V 


V GS = 0, l SD = -1A 



Notes: 

1 . All D.C. parameters 1 00% tested at 25°C unless otherwise stated. (Pulse test: 300ms pulse, 2% duty cycle.) 

2. All A.C. parameters sample tested. 



Switching Waveforms and Test Circuit 




10-47 



Alphanumeric Index and Ordering Information MM 

Corporate Profile WM 

Applications Notes |cfl 

Quality Assurance and Handling Procedures MM 

Process Flow M 

Selector Guides and Cross Reference E*M 

N- and P-Channei Low Threshold MOSFETs WM 

DMOS N-Channe! Discretes I:H 

OMOS P-Channel Discretes E*W 

DMOS Arrays and Special Functions ![§■ 
nign voltage uriver/interrace ius 

High Voltage Analog Switches and Multiplexers WM 

High Voltage Power Supply ICs ikfl 

CMOS Consumer/Industrial Products \IM 
Surface Mount Packages and Lead Bend Options 

Package Outlines ildl 

Die Specifications WM 

Representatives/Distributors i HM 



Chapter 11 - High Voltage Driver/Interface ICs 

High Voltage Integrated Circuit Custom Design and Process Capabilities 11-1 

HV03/HV05 64-Channel Serial to Parallel Converter with Open Drain Outputs 11-3 

HV04/HV06 64-Channel Serial to Parallel Converter with High Voltage CMOS Outputs 11-9 

HV04H/HV06H 64-Channel Serial to Parallel Converter with Ruggedized High Voltage CMOS Outputs .... 11-15 

HV31 64-Channel Serial to Parallel Converter with Open Drain Outputs 11-21 

HV33 32 + 22 Channel Matrix Printhead Driver 1 1 -26 

HV34 64-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs 1 1 -28 

HV35 275V, 64-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs 1 1 -33 

HV36 High Voltage Pin Diode Driver 1 1 -38 

HV38 32-Channel Gray-Shade Display Column Driver 1 1 -43 

HV41/HV42 32-Channel Serial to Parallel Converter with P-Channel Open Drain Outputs 11-51 

HV45/HV46 32-Channel Serial to Parallel Converter with P-Channel Open Drain Outputs 1 1 -56 

HV49 64-Channel Serial to Parallel Converter with P-Channel Open Drain Outputs 11-62 

HV51/HV52 32-Channel Serial to Parallel Converter with Open Drain Outputs 11-67 

HV53/HV54 32-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs 1 1 -73 

HV55/HV56 32-Channel Serial to Parallel Converter with Open Drain Outputs 1 1 -78 

HV57/HV58 32-Channel Serial to Parallel Converter with Push-Pull Outputs 1 1 -84 

HV500 32-Channel AC Plasma Display Driver 1 1 -89 

HV501 32-Channel AC Plasma Display Driver 1 1 -94 

HV51 8 32-Channel Vacuum-Fluorescent Display Driver 1 1 -99 

HV60 32-Channel ± 40V Liquid Crystal Display Row Driver 11-104 

HV65 32-Channel LCD Driver with Separate Backplane Output 1 1 -1 09 

HV6810 10-Channel Serial-Input Latched Display Driver 11-114 

HV70 34-Channel Symmetric Row Driver 11-119 

HV72 40-Channel Symmetric Row Driver 11-125 

HV77/HV577/HV79 32MHz, 64-Channel Serial to Parallel Converter with Push-Pull Outputs 11-131 

HV78 20MHz, 64-Channel Serial to Parallel Converter with Push-Pull Outputs 1 1 -1 36 

HV701/HV711 200V, 40-Channel Vacuum-Fluorescent Display Driver 11-141 

HV702/HV712 200V, 40-Channel Vacuum-Fluorescent Display Driver 11-147 

HV83/HV84 32-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs 11-153 

HV87/HV88 32-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs 1 1 -1 58 

HV93/HV94 32-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs 1 1 -1 63 

HV97/HV98 32-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs 1 1 -1 68 



High-Voltage Integrated Circuit 
Custom Design and Process Capabilities 



HVIC Custom Capabilities 

Supertex, Inc. is a supplier of technologically-advanced high- 
voltage MOS transistors and integrated circuits. The standard 
devices in our catalogs are found in military, industrial and com- 
mercial applications requiring high voltage, high circuit density, low 
turn-on thresholds, and logic-plus-power on the same chip, known 
as high voltage integrated circuits (HVIC). 

Some of the special applications of our HVICs include drivers for 
printer heads and plotters, flat panel displays (including plasma 
and electroluminescent, vacuum fluorescent and liquid crystal 
displays), medical ultrasound transducers, and bare-board testers. 
Our special high-voltage manufacturing and design capabilities 
have been used for many years to provide unique solutions for 
many customers. The capability summary shown here provides a 
brief overview of current Supertex custom capabilities to design 
and manufacture HVICs. These HVICs provide not only propri- 
etary protection for our customers, but also offer them improved 
performance, lower power dissipation, better reliability, space 
savings and above all, lower total system cost. 



High-Voltage Circuit Design 

Supertex provides over twelve years of experience in high voltage 
integrated circuit design with true complementary N-channel and 
P-channel output configurations. These may be output devices for 
push-pull drive, or for fast pull-up or pull-down, providing high 
density with cost effectiveness. Supertex also offers proprietary 
low-power level translators for driving high-side drivers with mini- 
mal quiescent dissipation. 



By design, our logic circuitry is particularly latch-up resistant for 
increased reliability in noisy environments. This is especially 
important because many circuits need to perform beyond 20MHz, 
as in high speed graphic equipment. Where higher speeds are 
needed, multiple shift registers can be put on a chip for parallel 
multiplex feeds to conserve power dissipation. 



Standard High-Voltage Processes 

The foundation for any semiconductor manufacturer is process 
technology. At Supertex, we have developed and refined a family 
of high-voltage CMOS/DMOS processes, working closely with our 
customers for over ten years. They are summarized as follows: 

HVCMOS 1 : 1 60V or ±80V analog switch with 
12V CMOS logic 

HVCMOS II-S1 : 80V push-pull, 400V open drain with 
5V or 12V CMOS logic 

HVCMOS II-S2: 275V push-pull with 5V or 12V CMOS logic 

HVCMOS III: 200V bilateral analog switch with 
5V or 12V CMOS logic 

The choice of 5V or 12V is usually dictated by logic interface (5V) 
or noise-immunity and higher turn-on (12V) requirements. These 
processes produce truly low power CMOS designs. Our HVICs 
have low power dissipation that are uniquely suited for low cost 
high pin count packages. 



ill 



Custom Product Capability Summary 




Open-Drain Outputs 
(N-Channel or P-Channel) 


Complementary 
Push-Pull Outputs 


Analog 
Output 


Output Breakdown 
Voltage 


30V-400V 


30V-275V 


30V-160V 


Output Current 


10UA-3A 


10UA-1A 


10UA-1A 


Number of Outputs 


I-160 


1-160 


1-32 


Logic Supply Voltage 


5V or 12V 


Package Material 


Ceramic or Plastic 


Package Types 


J-Lead (PLCC), Gullwing*, DIP, or Dice 


Temperature 
Ranges 


0° to 70°C (commercial), -40° to 85°C (industrial), 
-55° to 125°C (military) 


Technologies 


CMOS/DMOS, Analog, Digital, or Mixed Signal 


Frequencies 


DC to Video 


100kHz 



*Flat packs with leads on 3 or 4 sides 



11-1 



Custom Capabilities 



Packages and Die Options 

One of our main strengths is providing the advantages of high- 
voltage ICs in high pin count packages. 

We can provide: 

• Standard QFP packages up to 1 00 leads 

• Special packages for more than 84 leads 

• J-lead (PLCC), gullwing, or DIP packages 

• Small-outline packages 

• Custom lead frames and special lead bends 

• Hybrids and arrays 

These offerings provide space efficiency and reduced insertion 
costs to our customers. They are particularly appropriate in flat- 
panel displays and printer assemblies as well as other applications 
where space is at a premium. All offerings are available in industrial 
temperature range versions, and most can be supplied as military 
versions as well. 

Forthe ultimate packaging density, we can supply dice. Using pad 
pitches down to 100 microns or less, with aspect ratios up to 7 to 
1 , optimum interface to printers and displays can be achieved. The 
user thus has several choices: die in waffle pack, in wafer form, or 
as bumped die for tape automated bonding (TAB); chip-on-glass 
or die on printed circuit board. All of these offer cost and space 
savings. However, packaged products provide testability and field 
repairability as well as the capability of machine (robot) insertion 
or placement. 



Quality Monitoring 

The latest statistical methods are used continuously to improve 
quality levels. Statistical Quality Control (SQC) is an ongoing 
tightening of such levels in-process. 

Our Parts per Million (PPM) program is a continual feedback loop 
to ensure conformance to the customer's specifications using 
computerized data generated from each processed lot. Custom 
parts receive the same benefits from our Quality and Reliability 
Programs as standard parts. Supertex routinely supplies 883C 
parts to manufacturers of military equipment. 



Reliability 

We also have in-house activities to ensure the reliability of our 
products in the field. These include: 

Reliability Monitoring Program - Lot samples are tested and 
monitored on a periodic basis for infant mortalities and long-term 
degradation. 

Failure Analysis Laboratory - We have our own lab on the 

premises, with SEM, SRP, LCD thermal, and other analytical 
equipment. This lab enables us to get fast feedback for corrective 
action whenever necessary. 

Our R & D departments are continually developing improved circuit 
and processing techniques for raising the electrostatic discharge 
(ESD) protection on our devices (presently at +2KV). Manufac- 
tured parts are put in anti-static coated plastic tubes to protect them 
in shipment. All assembly facilities are meticulously inspected for 
adherence to ESD procedures. 

Solutions to Design Needs 

Supertex has a proven track record in the development and 
production of custom and semi-custom high voltage integrated 
circuits. Since its inception in 1 976, Supertex has provided custom 
solutions for computers, military, telecommunications, medical 
instrumentation, and consumer products. Based on its pioneering 
HVCMOS® technology, and supported by a staff with uniquely 
diverse expertise and experience, Supertex provides the research 
and development environment which provides its customers with 
the most advanced solutions to custom and semi-custom HVIC 
requirements. A thorough understanding of customer require- 
ments by our application engineers and circuit designers results in 
practical and commercially viable solutions. Working closely with 
its customers, Supertex develops meaningful time lines and 
specifications for production and provides continuous progress 
updates to ensure quality solutions on a timely basis. 

If your product requires a custom or semi-custom high voltage 
integrated circuit, Supertex can provide you with the resources 
necessary to accomplish your goals. Contact your nearest Super- 
tex sales office or the Sunnyvale headquarters directly to begin 
creating the solution to your custom or semi-custom HVIC require- 
ments. 



11-2 



HV03 
HV05 



64-Channel Serial To Parallel Converter 
With Open Drain Outputs 

Ordering Information 



Device 


Recommended 
Operating 
V pp Max 


Package Options 


80-Lead 
Quad Cerpak 
Gullwing 


80-Lead 
Quad Plastic 
Gullwing 


80-Lead 
35mm TAB 
Tape 


Die 


80-Lead Quad 
Cerpak Gullwing 

(MIL-STD-883 Processed*) 


HV03 


220V 


HV0322DG 


HV0322PG 


HV0322T 


HV0322X 


RBHV0322DG 


300V 


HV0330DG 


HV0330PG 


HV0330T 


HV0330X 




HV05 


220V 


HV0522DG 


HV0522PG 


HV0522T 


HV0522X 


RBHV0522DG 


300V 


HV0530DG 


HV0530PG 


HV0530T 


HV0530X 





*For Hi-Rel process flows, please refer to page 5-3 in the Databook. 

Features 

□ HVCMOS® technology 

□ Output voltages up to 300V using a ramped supply 

□ Sink current minimum 1 00 mA 

□ Shift register speed 8 MHz 

□ Latched outputs 

□ Output polarity and blanking 

□ CMOS compatible inputs 

□ Forward and reverse shifting options 

Absolute Maximum Ratings 1 



Supply voltage, V DD 




-0.5Vto+15V 


Supply voltage, V PP 2 




-0.5V to +31 5V 


Logic input levels 


-0.5V to V DD +0.5V 


Ground current 3 




6.0A 


Continuous total power dissipation 4 


Ceramic 
Plastic 


1900mW 
1200mW 


Operating temperature range Commercial 

Military 


-40°C to +85°C 
-55°C to+125°C 


Storage temperature range 




-65°Cto+150°C 



Notes: 

1 . All voltages are referenced to GND. 

2. These devices have been designed to be used in applications which either 
switch the V PP supply to ground before changing the state of the high voltage 
outputs or limit the current through each output. 

3. Connection to all power and ground pads is required. Duty cycle is limited by 
the total power dissipated in the package. 

4. For operation above 25 D C ambient derate linearly to 85 Q C at 1 5mW/°C. 



General Description 

The HV03 and HV05 are low voltage serial to high voltage parallel 
converters with open drain outputs. These devices have been 
designed for use as drivers for AC-electroluminescent displays. 
They can also be used in any application requiring multiple output 
high voltage current sinking capabilities such as driving inkjet and 
electrostatic printheads, plasma panels, vacuum fluorescent, or 
large matrix LCD displays. 

These devices consist of a 64-bit shift register, 64 latches, and 
control logic to perform the polarity select and blanking of the 
outputs. Data is shifted through the shift register on the high to low 
transition of the clock. The HV03 shifts in the counterclockwise 
direction when viewed from the top of the package and the HV05 
shifts in the clockwise direction. A data output buffer is provided 
for cascading devices. This output reflects the current status of 
the last bit of the shift register. Operation of the shift register i s not 
affected by the LE (latch enable), BL (blanking), or the POL 
(polarity) inputs. Transfer of data from the shift register to the latch 
occurs when the LE (latch enable) input is high. The data in the 
latch is stored when LE is low. 

The HV03 and HV05 have been designed to be used in systems 
which either switch off the high voltage supply before changing 
the state of the high voltage outputs or limit the current through 
each output. 



fill 



11-3 



HV03/HV05 



■DD 


U . 11IW1HV lllirrHUT 

DD rr'j wuiiciii 






25 


mA 


fr, u = 8MHz. fn»T 4 = 4MHz 

CLK •""w" "-i 'DATA 

LE = LOW 


DDQ 


Quiescent Vqq Supply Current 






0.25 


mA 


All V, N = 0V 


'o(OFF) 


Off State Output Current 






100 


uA 


All outputs high, All SWS parallel 


'IH 


High-Level Logic Input Current 






10 


uA 


V| H = V DD 


l,L 


Low-Level Logic Input Current 






-10 


uA 


V, = OV 


V™, 

v OH 


High-Level Output Data Out 


V™ -1V 

V DD 1 v 






v 


ID™ ,t = -100uA 


V OL 


Low-Level Output 


HVout 






15 


V 


IHV OUT = +100mA 


Data Out 






1 


V 


ID OUT = +100nA 


Voo 


HV OUT Clamp Voltage 






-1.5 


V 


l OL = -100mA 



AC Characteristics 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


Conditions 


f CLK 


Clock Frequency 






8 


MHz 




t w 


Clock Width High or Low 


62 






ns 




tsu 


Data Setup Time Before Clock Falls 


25 






ns 






Data Hold Time After Clock Falls 


10 






ns 




•wLE 


Width of Latch Enable Pulse 


62 






ns 




'dle 


LE Delay Time Falling Edge of Clock 


25 






ns 




•sLE 


LE Setup Time Before Falling Edge of Clock 


30 






ns 




<D 


Delay Time from V pp Low Until 
Change in LE, POL, BL Is Allowed 


100 






ns 




t SL 


Setup Time from Falling Edge LE to V PP Rise 


200 






ns 




t SB 


Setup Time from BL Selected to V PP Rise 


150 






ns 




'sp 


Setup Time from POL Selected to V PP Rise 


100 






ns 




'dhl 


Delay Time Clock to Data High to Low 






100 


ns 




'dlk 


Delay Time Clock to Data Low to High 






100 


ns 





Recommended Operating Conditions 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


V DD 


Logic supply voltage 


10.8 


12 


13.2 


V 


Vpp 


High voltage supply 


HV0322/HV0522 


-0.3 




220 


V 


HV0330/HV0530 


-0.3 




300 


V 


V IH 


High-level input voltage 


V DD -2V 




V DD 


V 


V,L 


Low-level input voltage 







2.0 


V 


dV/dt 


Vpp ramp rate 






80 


V/us 


T A 


Operating free-air temperature 


-40 




+85 


°c 



11-4 



HV03/HV05 



Input and Output Equivalent Circuit 



V D D o- 



Input O n^v- 



GND O- 



Logic Inputs 



V DD o- 




Data Out 



3 



GND O- 



Logic Data Output 



HV, N - 



)HV UT 




-= GND 



High Voltage Outputs 



Typical Operating Conditions 

Sink Current @ 25 C 





180 




160 




140 




120 


< 


100 


£ 








o 


80 




60 




40 




20 






































V DD = 


14V =d 
















1 V DD - 1 




















2V ===== 




— v DD 


= 11V 





























































































































fill 



1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 

VoutOO 



11-5 



HV03/HV05 



Switching Waveforms 



Data 
In 



Data Valid 1 



) (XXXXXX) O^KXX 




Output Control Waveforms 



V PP 



Latch Enable 



Blanking 



Polarity 



Transparent 
Stored Data 



10% 



10% 



X 



■t SL - 



X 



X 



-'sp- 



11-6 



HV03/HV05 



Functional Block Diagram 



POL 



BL o- 



Latch Enable o- 



Data Input 



Clock 



64 bit 
Static Shift 



64 Latches 





o Output 1 



o Output 2 



60 Additional 
Outputs 



oOutput 63 



-o Output 64 



-o Data Out 



Function Table 





Inputs 






Outputs 




Function 


Data 


CLK 


LE 


BL 


POL 


Shift Reg 

1 2... 64 


HV Outputs 

1 2. .64 


Data Out 

* 


All on 


X 


X 


X 


L 


L 




L 


L...L 




All off 


X 


X 


X 


L 


H 


* * * 


H 


H...H 




Invert mode 


X 


X 


L 


H 


L 










Load S/R 


HorL 


I 


L 


H 


H 


HorL *...* 


* 


* * 


* 


Load Latches 


X 


X 


H 


X 


X 


* * * 




* 


Transparent 


L 


1 


H 


H 


H 


L *...* 


H 


* * 




Latch mode 


H 


I 


H 


H 


H 


H *...* 


L 


* * 


* 



fill 



Notes: 

H = high level, L = low level, X = irrelevant, i= high-to-low transition. 

• = dependent on previous stage's state before the last CLK or last LE high. 



11-7 



Pin Configurations 

PG and DG Packages 



HV03 






HV05 






Pin 


Function 


Pin 


Function 


Pin 


Function 


Pin 


Function 


1 


GND 


41 


GND 


1 


GND 


41 


GND 


2 


GND 


42 


GND 


2 


GND 


42 


GND 


3 


HV OUT 59 


43 


HV OUT 23 


3 


HV ol/r 6 


43 


HV OUT 42 


4 


HV 0UT 60 


44 


HV OUT 24 


4 


HV OUT 5 


44 


HV 0UT 41 


5 


HV 0UT 61 


45 


HV OUT 25 


5 


HV 0UT 4 


45 


HV OUT 40 


6 


HV OUT 62 


46 


HV OUT 26 


6 


HV OUT 3 


46 


HVQUT39 


7 


HV OUT 63 


47 


HV OUT 27 


7 


HV 0UT 2 


47 


HV OUT 38 


8 


HV OUT 64 


48 


HV OUT 28 


8 


HVourl 


48 


HVQUT37 


9 


POL 


49 


HVQUT29 


9 


POL 


49 


HV OUT 36 


10 


Data Out 


50 


HVou^O 


10 


Data Out 


50 


HV OUT 35 


11 


CLK 


51 


HVou T 31 


11 


CLK 


51 


HV OUT 34 


12 


GND 


52 


HV OUT 32 


12 


GND 


52 


HV 0UT 33 


13 


Ydd 


53 


HV OUT 33 


13 


Ydd 


53 


HV OUT 32 


14 


LE 


54 


HVQUT34 


14 


LE 


54 


HV OUT 31 


15 


Data In 


55 


HVQUT35 


15 


Data In 


55 


HV OUT 30 


16 


BL 


56 


HV OUT 36 


16 


Bl 


56 


HV OUT 29 


17 


HV 0UT 1 


57 


HV OUT 37 


17 


HV OUT 64 


57 


HV OUT 28 


18 


HV OUT 2 


58 


HV OUT 38 


18 


HV OUT 63 


58 


HVQUT27 


19 


HV OUT 3 


59 


HV 0UT 39 


19 


HV OUT 62 


59 


HV OUT 26 


20 


HV 0UT 4 


60 


HV OUT 40 


20 


HVourl 


60 


HV OUT 25 


21 


HV 0UT 5 


61 


HVQUT41 


21 


HV OUT 60 


61 


HV OUT 24 


22 


HV 0UT 6 


62 


HV OUT 42 


22 


HV OUT 59 


62 


HV OUT 23 


23 


GND 


63 


GND 


23 


GND 


63 


GND 


24 


GND 


64 


GND 


24 


GND 


64 


GND 


25 


HV OUT 7 


65 


HV OUT 43 


25 


HV OUT 58 


65 


HVQUT22 


26 


HV OUT 8 


66 


HV OUT 44 


26 


HV OUT 57 


66 


HV OUT 21 


27 


HV OUT 9 


67 


HVqut-45 


27 


HV OUT 56 


67 


HV OUT 20 


28 


HV OUT 10 


68 


HV OUT 46 


28 


HVQUT55 


68 


HV OUT 19 


29 


HV 0UT 11 


69 


HV OUT 47 


29 


HV OUT 54 


69 


HVoutIB 


30 


HV 0UT 12 


70 


HV OUT 48 


30 


HV OUT 53 


70 


HV OUT 17 


31 


HV 0UT 13 


71 


HV OUT 49 


31 


HV OUT 52 


71 


HV OUT 16 


32 


HV OUT 14 


72 


HVqutSO 


32 


HVou.51 


72 


HV 0UT 15 


33 


HV OUT 15 


73 


HVogTSI 


33 


HVoutSO 


73 


HVoutU 


34 


HV OUT 16 


74 


HV OUT 52 


34 


HV OUT 49 


74 


HVout-13 


35 


HV 0UT 17 


75 


HV 0UT 53 


35 


HV OUT 48 


75 


HV 0UT 12 


36 


HV 0UT 18 


76 


HVQUT54 


36 


HV OUT 47 


76 


HV 0UT 11 


37 


HV OUT 19 


77 


HV OUT 55 


37 


HVQUT46 


77 


HV OUT 10 


38 


HV OUT 20 


78 


HVQUT56 


38 


HV OUT 45 


78 


HVo^g 


39 


HV 0UT 21 


79 


HV OUT 57 


39 


HV OUT 44 


79 




40 


HV OUT 22 


80 


HV OUT 58 


40 


HV OUT 43 


80 


HVQUT7 



HV03/HV05 



65c 



80 c 




1 



24 



top view 
80-pin Gullwing Package 



11-8 



HV04 
HV06 



64-Channel Serial To Parallel Converter 
With High Voltage CMOS Outputs 

Ordering Information 



Device 


Recommended 
Operating 
V PP Max 


Package Options 


80- Lead 
Quad Cerpak 
Gullwing 


80-Lead 
Quad Plastic 
Gullwing 


80-Lead 
35mm TAB 
Tape 


Die 


80-Lead Quad 
Cerpak Gullwing 

(MIL-STD-883 Processed*) 


HV04 


60V 


HV0406DG 


HV0406PG 


HV0406T 


HV0406X 




80V 


HV0408DG 


HV0408PG 


HV0408T 


HV0408X 


RBHV0408DG 


HV06 


60V 


HV0606DG 


HV0606PG 


HV0606T 


HV0606X 






80V 


HV0608DG 


HV0608PG 


HV0608T 


HV0608X 


RBHV0608DG 



* For Hi-Rel process flows, please refer to page 5-3 in the Databook. 

Features 

□ HVCMOS® technology 

□ Output voltages up to 90V using a ramped supply 

□ Low power level shifting 

Z Shift register speed 8 MHz 

□ Latched data outputs 

□ Output polarity and blanking 

□ CMOS compatible inputs 

□ Forward and reverse shifting options 

Absolute Maximum Ratings 1 



Supply voltage, V DD 


-0.5V to+15V 


Supply voltage, V PP 2 


-0.5V to +90V 


Logic input levels 


-0.5V to V DD +0.5V 


Ground current 3 


3.0A 


High voltage supply current 3 


2.6A 


Continuous total power dissips 


ition 4 Ceramic 1900mW 
Plastic 1200mW 


Operating temperature range 


Commercial -40°C to +85°C 
Military -55°C to +1 25°C 


Storage temperature range 


-65°Cto+150°C 



1. All voltages are referenced to GND. 

2. These devices have been designed to be used in applications which either 
switch the V PP supply to ground before changing the state of the high voltage 
outputs or limit the current through each output. 

3. Connection to all power and ground pads is required. Duty cycle is limited by 
the total power dissipated in the package. 

4. For operation above 25°C ambient derate linearly to 85°C at t5mW/°C. 



General Description 

Not recommended for new designs. Please use HV577, with 
improved performance. 

The HV04 and HV06 are low voltage serial to high voltage parallel 
converters with push-pull outputs. These devices have been 
designed for use as drivers for AC-electroluminescent displays. 
They can also be used in any application requiring multiple output 
high voltage current sourcing and sinking capabilities such as 
driving plasma panels, vacuum fluorescent, or large matrix LCD 
displays. 

These devices consist of a 64-bit shift register, 64 latches, and 
control logic to perform the polarity select and blanking of the 
outputs. HVoutl is connected to the first stage of the shift register 
through the polarity and blanking logic. Data is shifted through the 
shift register on the low to high transition of the clock. The HV04 
shifts in the counterclockwise direction when viewed from the top 
of the package and the HV06 shifts in the clockwise direction. A 
data output buffer is provided for cascading devices. This output 
reflects the current status of the last bit of the shift register 
(HVout64). Operation of the shift reg ister is not affected by the LE 
(latch enable), BL (blanking), or the POL (polarity) inputs. Trans- 
fer of data from the shift register to the latch occurs when the LE 
(latch enable) input is high. The data in the latch is stored when 
LE is low. 

The HV04 and HV06 have been designed to be used in systems 
which either switch off the high voltage supply before changing 
the state of the high voltage outputs or limit the current through 
each output. 



ill 



11-9 



HV04/HV06 



Electrical Characteristics (over recommended operating conditions unless noted) 
DC Characteristics 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


Conditions 


'dd 


V 0D Supply Current 






25 


mA 


f cu< = 8MHz, f DATA = 4MHz 
LE = LOW 


'ddq 


Quiescent V Supply Current 






0.25 


mA 


All V |N = 0V 


'pp 


, — 

High Voltage Supply Current 






0.50 


mA 


V pp = 80V All outputs high 


0.50 


mA 


V pp = 80V All outputs low 


',H 


High-Level Logic Input Current 






10 


uA 


V = V 

* IH DD 


'■L 


Low-Level Logic Input Current 






-10 


uA 


v, = ov 


V OH 


High-Level Output 


HV OUT 


74 






V 


V pp = 80V, IHV OUT = -20mA 
ID OUT = -100uA 




Data Out 


V - 1V 

DD 






V 


V 0L 


Low-Level Output 


HV 0UT 






6 


V 


V pp = 80V, IHV OUT = +10mA 
ID OUT = + 100uA 




Data Out 






1 


V 


Voc 


HV 0UT Clamp Voltage 






V P p + 1-5 


V 


l OL = +10mA 


-1.5 


V 


l OL = -20mA 



AC Characteristics 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


Conditions 


'cLK 


Clock Frequency 






8 


MHz 






Clock Width High or Low 


62 






ns 




Vi 


Data Setup Time Before Clock Rises 


25 






ns 




<H 


Data Hold Time After Clock Rises 


10 






ns 




We 


Width of Latch Enable Pulse 


62 






ns 




'dle 


LE Delay Time Rising Edge of Clock 


25 






ns 




>SLE 


LE Setup Time Before Rising Edge of Clock 


30 






ns 




«D 


Delay Time from V pp Low Until 
Change in LE, POL, BL Is Allowed 


100 






ns 




«SL 


Setup Time from LE Rise to V pp Rise 


200 






ns 






Setup Time from BL Selected to V pp Rise 


150 






ns 




W 


Setup Time from POL Selected to V pp Rise 


100 






ns 


' 


w 


Delay Time Clock to Data High to Low 






100 


ns 




'dlh 


Delay Time Clock to Data Low to High 






100 


ns 





Recommended Operating Conditions 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


V DD 


Logic supply voltage 


10.8 


12 


13.2 


V 


V pp 


High voltage supply 


-0.3 




80 


V 


V ,H 


High-level input voltage 


V - 2V 

DD 




V DD 


V 


V ,L 


Low-level input voltage 







2.0 


V 


dV/dt 


V pp ramp rate 






80 


V/us 


T A 


Operating free-air temperature 


-40 




+85 


°C 



11-10 



Input and Output Equivalent Circuits 



HV04/HV06 



Vdd o- 



Input o vw- 



GND O- 



Logic Inputs 



Vdd o- 



3 



i Data Out 



GND o- 



Logic Data Output 



Vpp o- 



>HV 0U T 



GND O- 



High Voltage Outputs 



Typical Performance Curves 



Typical HV04/06 Sink Current @ 25°C 




Typical HV04/06 Source Current @ 25 °C 

50 i 1 1 1 1 1 1 1 1 1 Vpp = 80V 

60V 




11-11 



Switching Waveforms 



HV04/HV06 




Output Control Waveforms 



Transparent 

Latch Enable stored Data 



Blanking 



Polarity 



10% 



X 

)( 
)( 



10% 



X 



X 



'SB 



X 



11-12 



HV04/HV06 



Functional Block Diagram 



POL o- 
BL o- 



Latch Enable o- 



Data Input 



Clock 















RA hit 

Static Shift 
Register 




64 Latches 















; = £^> ' 3D l f~ HVout2 



V PP 

: — r^ 3 HVout1 



60 Additional 
Outputs 



= Q^_ ^j^> 6>— o HV OUT 63 



HV OUT 64 



-o Data Out 



Function Ta 


ible 


Function 


Inputs 


Outputs 


Data 


CLK 


LE 


BL 


POL 


Shift Reg 

1 2.. .64 


HV Outputs 

1 2.. .64 


Data Out 

* 


All on 


X 


X 


X 


L L 




H H...H 




All off 


X 


X 


X 


L 


H 


* * * 


L L...L 


* 


Invert mode 


X 


X 


L 


H 


L 


* • • 




* 


Load S/R 


HorL 


T 


L 


H 


H 


HorL *...* 




* 


Load 
Latches 


X 


HorL 


H 


H 


H 


* • * 


• * • 


* 


X 


HorL 


H 


H 


L 


* * * 


* * * 


• 


Transparent 
Latch mode 


L 


T 


H 


H 


H 


L *...* 


L 


* 


H 


T 


H 


H 


H 


H 


H 





Notes: 

H = high level, L = (ow level, X - irrelevant, T - low-to-high transition^ 

• ■ dependent on previous stage's state before the last CLK or last LE high. 



11-13 



HV04/HV06 



Pin Configurations 

PG and DG Packages 



HV04 



Pin 


Function 


Pin 


Function 


1 


GND 


41 


GND 


2 


Vpp 


42 


V PP 


3 


HV OUT 59 


43 


HV OUT 23 


4 


HV OUT 60 


44 


HV OUT 24 


5 


HV 0UT 61 


45 


HV OUT 25 


6 


HV OUT 62 


46 


HV OUT 26 


7 


HV OUT 63 


47 


HV OUT 27 


8 


HV OUT 64 


48 


HV OUT 28 


9 


POL 


49 


HV OUT 29 


10 


Data Out 


50 


HV OUT 30 


11 


CLK 


51 


HV 0UT 31 


12 


GND 


52 


HV OUT 32 


13 


v DD 


53 


HV OUT 33 


14 


LE 


54 


HV OUT 34 


15 


Data In 


55 


HV OUT 35 


16 


BL 


56 


HV OUT 36 


17 


HV 0UT 1 


57 


HV OUT 37 


18 


HV OUT 2 


58 


HV OUT 38 


19 


HV OUT 3 


59 


HV OUT 39 


20 


HV OUT 4 


60 


HV OUT 40 


21 


HV OUT 5 


61 


HV 0UT 41 


22 


HV OUT 6 


62 


HV OUT 42 


23 


Vpp 


63 


V P p 


24 


GND 


64 


GND 


25 


HV OUT 7 


65 


HVQUT43 


26 


HV OUT 8 


66 


HV OUT 44 


27 


HV 0UT 9 


67 


HV OUT 45 


28 


HV OUT 10 


68 


HV OUT 46 


29 


HV 0UT 11 


69 


HV OUT 47 


30 


HV 0UT 12 


70 


HV OUT 48 


31 


HV 0UT 13 


71 


HV OUT 49 


32 


HV OUT 14 


72 


HV OUT 50 


33 


HV OUT 15 


73 


HV OUT 51 


34 


HV OUT 16 


74 


HV OUT 52 


35 


HV 0UT 17 


75 


HV OUT 53 


36 


HV OUT 18 


76 


HV OUT 54 


37 


HV OUT 19 


77 


HV OUT 55 


38 


HVOUJ20 


78 


HV OUT 56 


39 


HV OUT 21 


79 


HV 0UT 57 


40 


HV OUT 22 


80 ' 


HV OUT 58 



HV06 






Pin 


Function 


Pin 


Function 


1 


GND 


41 


GND 


2 


V PP 


42 


Vpp 


3 


HV 0UT 6 


43 


HV OUT 42 


4 


HV OUT 5 


44 


HV 0UT 41 


5 


HV 0UT 4 


45 


HV OUT 40 


6 


HV 0UT 3 


46 


HV OUT 39 


7 


HV 0UT 2 


47 


HV OUT 38 


8 


HV OUT 1 


48 


HV OUT 37 


9 


POL 


49 


HV 0UT 36 


10 


Data Out 


50 


HVout 35 


11 


CLK 


51 


HV OUT 34 


12 


GND 


52 


HV OUT 33 


13 


v DD 


53 


HV OUT 32 


14 


LE 


54 


HV OUT 31 


15 


Data In 


55 


HV OUT 30 


16 


BL 


56 


HV OUT 29 


17 


HV OUT 64 


57 


HV OUT 28 


18 


HV OUT 63 


58 


HV OUT 27 


19 


HV OUT 62 


59 


HV OUT 26 


20 


HV 0UT 61 


60 


HV OUT 25 


21 


HVout 60 


61 


HV OUT 24 


22 


HV OUT 59 


62 


HV OUT 23 


23 


Vpp 


63 


Vpp 


24 


GND 


64 


GND 


25 


HV OUT 58 


65 


HV OUT 22 


26 


HV OUT 57 


66 


HV OUT 21 


27 


HV OUT 56 


67 


HV OUT 20 


28 


HV 0UT 55 


68 


HV OUT 19 


29 


HV OUT 54 


69 


HV 0UT 18 


30 


HV 0UT 53 


70 


HV OUT 17 


31 


HV OUT 52 


71 


HV 0UT 16 


32 


HV 0UT 51 


72 


HV OUT 15 


33 


HV OUT 50 


73 


HV OUT 14 


34 


HV OUT 49 


74 


HV OUT 13 


35 


HV OUT 48 


75 


HV 0UT 12 


36 


HV OUT 47 


76 


HV 0UT 11 


37 


HV OUT 46 


77 


HV OUT 10 


38 


HV OUT 45 


78 


HV OUT 9 


39 


HV OUT 44 


79 


HV OUT 8 


40 


HV OUT 43 


80 


HV OUT 7 



Package Outline 

64 41 





jiiiiiii 








V 

H 


Rni= 


Index 






iiiiiiii 





1 24 



top view 

80-pin Gullwing Package 



11-14 



HV04H 
HV06H 



64-Channel Serial To Parallel Converter 
With Ruggedized High Voltage CMOS Outputs 



Ordering Information 



Device 


Recommended 
Operating 
V pp Max 


Package Options 


80- Lead 
Quad Cerpak 
Gullwing 


80-Lead 
Quad Plastic 
Gullwing 


80-Lead 
35mm TAB 
Tape 


Die 


80-Lead Quad 
Cerpak Gullwing 

(MIL-STD-883 Processed*) 


HV04H 


60V 


HV04H06DG 


HV04H06PG 


HV04H06T 


HV04H06X 




80V 


HV04H08DG 


HV04H08PG 


HV04H08T 


HV04H08X 


RBHV04H08DG 


HV06H 


60V 


HV06H06DG 


HV06H06PG 


HV06H06T 


HV06H06X 




80V 


HV06H08DG 


HV06H08PG 


HV06H08T 


HV06H08X 


RBHV06H08DG 



1 For Hi-Ret process flows, please refer to page 5-3 in the Databook. 



Features 

D HVCMOS® technology 
C Output voltages up to 80V 

□ Low power level shifting 

Z Shift register speed 8 MHz 

□ Latched data outputs 

□ Output polarity and blanking 
Z CMOS compatible inputs 

Z Forward and reverse shifting options 

Absolute Maximum Ratings 1 



Supply voltage, V DD 




-0.5Vto+15V 


Supply voltage, V PP 




-0.5V to +80V 


Logic input levels 


-0.5V to V DD +0.5V 


Ground current 3 




3.0A 


High voltage supply current 2 




2.6A 


Continuous total power dissipat 


ion 3 Ceramic 
Plastic 


1900mW 
1200mW 


Operating temperature range 


Commercial 
Military 


-40°C to +85°C 
-55°Cto+125°C 


Storage temperature range 




-65°Cto+150°C 



General Description 

Not recommended for new designs. Please use HV577, with 
improved performance. 

The HV04H and HV06H are low voltage serial to high voltage 
parallel converters with push-pull outputs. These devices have 
been designed for use as drivers for AC-electroluminescent 
displays. They can also be used in any application requiring 
multiple output high voltage current sourcing and sinking capa- 
bilities such as driving plasma panels, vacuum fluorescent, or 
large matrix LCD displays. 

These devices consist of a 64-bit shift register, 64 latches, and 
control logic to perform the polarity select and blanking of the 
outputs. HVoutl is connected to the first stage of the shift register 
through the polarity and blanking logic. Data is shifted through the 
shift register on the low to high transition of the clock. The HV04H 
shifts data in the counterclockwise direction when viewed from the 
top of the package and the HV06H shifts in the clockwise 
direction. A data output buffer is provided for cascading devices. 
This output reflects the current status of the last bit of the shift 
registerJjVout64). Operation of the shift register is no t affected 
by the LE (latch enable), BL (blanking), or the POL (polarity) 
inputs. Transfer of data from the shift register to the latch occurs 
when the LE (latch enable) is high. The data in the latch is stored 
when LE is low. 

The HV04H and HV06H devices are ruggedized versions of our 
standard HV04 and HV06. They are designed to be used in 
circuits where ramping of the high voltage supply is not feasible. 
Care must betaken to limit the load capacitance and surge current 
in any particular application. 



ill 



1 All voltages are referenced to ground. 

2, Connection to all power and ground pads is required. Duty cycle is limited by 
the total power dissipated in the package. 

3. For operation above 25°C ambient derate linearly to 85°C at 1 5mW/°C. 



11-15 



HV04H/HV06H 

ElGCtrical Characteristics (over recommended operating conditions unless noted) 
DC Characteristics 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


Conditions 


'do 


V DD Supply Current 






25 


mA 


f CLK = 8MHz,f DATA = 4MHz 

Lfc = LvJW 


'ddq 


Quiescent V DD Supply Current 








mA 


All V IN = 0VorV DD 


1 

Ipp 


High Voltage Supply Current 






u.ou 


mA 


\/ _ QA\/ All rtntrttitc hinh 

Vpp — ouv nil uuipuib niyn 


0.50 


mA 


V PP = 80V All outputs low 


1 

'IH 


High-Level Logic Input Current 








ii A 


V IH - V DD 


k. 


Low-Level Logic Input Current 






- 1 U 


|IA 


\/ — n\/ 
V, L - ov 


VI 

V OH 


High-Level Output 


HV 0UT 


7A 






w 

V 


V — An\/ IH\/ — -OflmA 
Vpp — ouv, invQUT — fcUfiiM 

ID OUT = -100uA 


Data Out 


V DD -1V 






V 


Vol 


Low-Level Output 


HV OUT 






6.0 


V 


V pp = 80V, IHV OUT = +1 0mA 
ID 0UT = +100|iA 


Data Out 






1.0 


V 


Voc 


hv out Clamp Voltage 






V PP + 1 .5 


V 


l 0L = +10mA 


-1.5 


V 


l OL = -20mA 



AC Characteristics 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


Conditions 


*CLK 


Clock Frequency 






8 


MHz 




t w 


Clock Width High or Low 


62 






ns 




t S u 


Data Setup Time Before Clock Rises 


25 






ns 




•h 


Data Hold Time After Clock Rises 


10 






ns 




twLE 


Width of Latch Enable Pulse 


62 






ns 




tDLE 


LE Delay Time Rising Edge of Clock 


25 






ns 




l SLE 


LE Setup Time Before Rising Edge of Clock 


30 






ns 




toN. toFF 


Time from Latch Enable to HV OUT 






50 


ns 




l DHL 


Delay Time Clock to Data High to Low 






100 


ns 




tDLH 


Delay Time Clock to Data Low to High 






100 


ns 





Recommended Operating Conditions 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 




Logic supply voltage 


10.8 


12 


13.2 


V 


V P p 


High voltage supply 


-0.3 




80 


V 


V,H 


High-level input voltage 


V DD -2V 




v DD 


V 


V,L 


Low-level input voltage 







2.0 


V 


T A 


Operating free-air temperature 


-40 




+85 


°c 



11-16 



HV04H/HV06H 



Input and Output Equivalent Circuits 



Vdo o- 



Input 



GND O- 



Logic Inputs 



Vdd o- 



i Data Out 



3 



GND O- 



Logic Data Output 



Vpp o- 




JHVqut 



3 



GND o- 



High Voltage Outputs 



Typical Performance Curves 

Typical HV04H/06H Source Current @ 25° C 

25 I 1 1 1 1 1 1 1 1 1 




1 23456789 10 



V out (v) 



Typical HV04H/06H Source Current @ 25° C 




o i 1 1 1 1 1 * 1 1 1 

123456789 10 
Vp P -V out (v) 



11-17 



Switching Waveforms 



HV04H/HV06H 



Data Input 



Clock 



Data Out 



Latch Enable 



HV 0UT 
w/ S/R LOW 



HVOUT 
w/ S/R HIGH 



I" 



Data Valid 



-•su ■ 



50%^ 



_t WL 



- l WH- 



50% 



-tDLH ■ 



50% 



- 'DHL - 



-*DLE ■ 



50% 



— t WLE „ 



50% 



-«SLE- 




10% 



90% 



V,H 



V H 

Vol 

Vqh 
Vol 

V,H 



V H 

V 0L 



V H 

Vol 



11-18 



HV04H/HV06H 



Functional Block Diagram 



POL o- 
BL o- 



Latch Enable o- 



Data Input 



Clock 



64 bit 
Static Shift 
Register 



64 Latches 



to— ^ 





HV 0UT 1 



HV OUT 2 



60 Additional 
Outputs 



HV OUT 63 



■o HV OUT 64 



-o Data Out 



Function Ti 


able 


Function 


Inputs 


Outputs 


Data 


CLK 


LE 


BL 


POL 


Shift Reg 

1 2. ..64 


HV Outputs 

1 2... 64 


Data Out 


All on 


X 


X 


X 


L 


L 




H H...H 


* 


All off 


X 


X 


X 


L 


H 




L L...L 




Invert mode 


X 


X 


L 


H 


L 








Load S/R 


HorL 


T 


L 


H 


H 


HorL *...* 


* * * 




Load 
Latches 


X 


HorL 


T 


H 


H 








X 


HorL 


T 


H 


L 




* * * 


* 


Transparent 
Latch mode 


L 


t 


H 


H 


H 


L 


L 




H 


t 


H 


H 


H 


H *...* 


H 





Notes: 

H = high level, L = tow level, X = irrelevant. T = low-to-high transition. 

* = dependent on previous stage's state before the last CLK or last LE high. 



11-19 



HV04H/HV06H 



Pin Configurations 

PG and DG Packages 

HV04H 



HV06H 



Pin 


Function 


Pin 




Pin 


Function 


Pin 


Funotinn 
ruiiuum i 


1 


GND 


41 


GND 


1 


GND 


41 


GND 


2 


Vpp 


42 


Vpp 


o 


Vpp 


AO 


Vpp 


3 


HV OUT 59 


43 


HVqut 23 


3 


HVqut 6 


43 


HVqut 42 


A 

4 


1_IW CA 

Hv 0UT 60 


44 


HV OU T 24 


4 


HVqut 5 


44 


HV ut 4 1 


E 

o 


MV OUT 61 


AC 

4o 


Ll\/ OC 

HVqut 25 


5 


LJV/ A 

HV OU T 4 


45 


HVqut 4 


3 


HV™ -r fiP 

n v OUT 0<£ 


46 


HV 76 
n v OUT m 


Q 


HV 1 


Aft 


HV OQ 
nv OUT oy 


7 


HV™ rr 63 

OUT 


47 


HV™ , T 27 
nv OUT 


7 


HV™ rr 2 
nv OUT ' 


47 


HV™ rr 38 

n v OUT 00 


8 


HV™ ~ 64 


48 


HV™ ~ 2R 
nv OUT '° 


3 


HV 1 


4R 


HV- 17 
nvQur o/ 


9 


POL 


49 


HV™ rr 29 

rlVQur « 


g 


POL 


49 


HV„ _ Ifi 
nvour oo 


10 


Data Out 


50 


HV™ rr 30 
OUT 


10 


Data Out 


50 


HV™rr 35 
OUT 


11 


CLK 


51 


HV,-urr 31 

OUT " ' 


11 


CLK 


51 


HV™rr 34 

OUT <rt 


12 


GND 


52 


HV™rr 32 

OUT ^ 


12 


GND 


52 


HV™ rr 33 

OUT dJ 


13 


V™, 

*DD 


53 


HV™~ 33 

OUT 


13 


Vrm 

V DD 


53 


HV™ rr 32 

* 1 v OUT ^ 


1 A 
14 


1 c 
LIT 


04 


Ll\/ Oil 


i A 




CA 

04 


/ o-t 

HVqut 31 


ID 


Data In 


55 


HVqut 35 


15 


Data In 


55 


HVqut 30 


16 


BL 


56 


HVqut 36 


16 


BL 


56 


HVqut 29 


17 


HV 0UT 1 


57 


HVqut 37 


17 


HVout 6 4 


57 


HVqut 28 


To 


LJW O 


CO 

oo 


HVqut 38 


18 


LJ\/ fiO 

HVqut 63 


58 


HVqut 27 


is* 


|_l V/ O 


CO 


t_]W oo 
HV OUT 39 


19 


HV OU t 62 


59 


HVqut 26 


o/v 
20 


Ml/ ' 

HVout4 


60 


HVqut 40 


20 


HVqut 61 


60 


HVqut 25 


OH 

21 


LJV/ C 

HV OUT 5 


61 


HVour41 


21 


HVqut 60 


61 


HVqut 24 


oo 
22 


HVout-6 


62 


HVqut 42 


22 


HVqut 59 


62 


HVqut 23 




Vpp 


DO 


Vpp 


OO 
tO 


Vpp 


CO 

DO 


Vpp 


24 


GND 


GA 
OH 


nun 


OA 


O IN U 


AA 

D*T 




do 


HV OUT 7 


OO 


L1W A O 

HVqut 43 


25 


HVqut 58 


65 


HVqut 22 


Oft 


LIV/ Q 


DO 


HVqut 44 


26 


HVout57 


66 


HVqut 21 


0*7 

2/ 


LiV/ O 

HV OUT 9 


67 


HVqut 45 


27 


HVqut 56 


67 


HVqut 20 


oo 

£-0 


n V 0UT 1 


68 


HVqut 46 


28 


HVqut 55 


68 


HVqut 1 9 


oo 

29 


LIV/ 1 -1 

nv OUT 1 1 


69 


HVqut 47 


29 


HVqut 54 


69 


HVqut 18 


Oft 


LIV/ 4 o 

nv OUT 12 


70 


HVqut 48 


30 


HVqut 53 


70 


HVqut 17 


OH 


il \/ j o 

H V oux 1 3 


71 


HVqut 49 


31 


HVqut 52 


71 


HVqut 16 


OO 

32 


LIV/ -4 vl 


72 


HVqut 50 


32 


HVqut 51 


72 


HVou T 15 


•JO 


uvy ic 
nv OUT '° 


/ o 


" v OUT SI 


O.Q 


nvQur ou 


to 


HVOUT I 4 


34 


HVourlB 


74 


HVqut 52 


34 


HVqut 49 


74 


HVqut 13 


35 


HVqutI? 


75 


HVqut 53 


35 


HVqut 4B 


75 


HVqut 12 


36 


HVQUT18 


76 


HVqut 54 


36 


HVqut 47 


76 


HVqut 11 


37 


HVqut 19 


77 


HVqut 55 


37 


HVqut 46 


77 


HVqut 10 


38 


HVOUT20 


78 


HVqut 56 


38 


HVqut 45 


78 


HVqut 9 


39 


HVqut 21 


79 


HVqut 57 


39 


HVqut 44 


79 


HVqut 8 


40 


HVqut 22 


80 


HVqut 58 


40 


HVqut 43 


80 


HVqut 7 



Package Outline 



64 



80 c 




top view 
80-pin Gullwing 



11-20 



HV31 



64-Channel Serial To Parallel Converter 
With Open Drain Outputs 

Ordering Information 



Device 


Package Options 


80- Lead 
Quad Plastic 
Gullwing 


Die 


HV31 


HV3137PG 


HV3137X 



Features 

□ HVCMOS® technology 

G Output voltages up to 375V 

□ Sink current minimum 1 mA 

□ Shift register speed 6 MHz 

□ Latched outputs 

□ CMOS compatible inputs 

□ Forward and reverse shifting options 

Absolute Maximum Ratings 1 

Supply voltage, Vqq 



-0.5V to +9V 



Supply voltage, V PP 


-0.5V to +375V 


Logic input levels 


-0.5V to V DD +0.5V 


Ground current 


0.75A 


Continuous total power dissipation 2 


1200mW 


Operating temperature range 


0°C to +85°C 


Storage temperature range 


-65°Cto+150°C 



Notes: 

1 . All voltages are referenced to GND. 

2. For operation above 25°C ambient derate linearly by 1 5mW/°C up to 85°C. 



General Description 

The HV31 is a low voltage serial to high voltage parallel converter 
with open drain outputs. It has been designed especially for use 
as a driver for electrostatic printers. 

This device consists of a 64-bit shift register, 64 latches, latch 
enable (LE), and output enable (OE). Data is shifted through the 
shift register on the high to low transition of the clock. When the 
DIR pin is set high, the HV31 shifts in the counterclockwise 
direction when viewed from the top of the package. When the Dl R 
pin is set low, the HV31 shifts in the clockwise direction. A serial 
data output buffer is provided for cascading devices. This output 
reflects the current status of the last bit of the shift register. 
Operation of the shift register is not affected by the LE or the OE 
inputs. Transfer of data from the shift register to the latch occurs 
when the LE input is high. The data in the latch is stored when LE 
is low. 



fill 



11-21 



Electrical Characteristics (over recommended operating conditions unless noted) 
DC Characteristics 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


Conditions 


"dd 


V DD Supply Current 






15 


mA 


f CLK = 6MHz,f DATA = 3MHz 
LE = LOW 


'ddq 


Quiescent V DD Supply Current 






250 


uA 


All V, N = 0V 


'o(OFF) 


Off State Output Current at 25°C, per Switch 






100 


nA 


Output high, and at 375V 


',H 


High-Level Logic Input Current 






10 


uA 


V IH = V DD 


k. 


Low-Level Logic Input Current 






-10 


uA 


v, = ov 


V OH 


High-Level Data Out 


v DD -w 






V 


ID OUT = -100uA 


Vol 


Low-Level Output 


HV OUT 






10 


V 


IHV OUT = +1mA 


Data Out 






1 


V 


IDout = +100uA 


Voc 


HV OUT Clamp Voltage 






-3.0 


V 


l OL = -1 mA 


C HVO 


Output Capacitance per Channel 






3 


PF 


V DS = 100V 



AC Characteristics 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


Conditions 


f CLK 


Clock Frequency 






6 


MHz 




tw 


Clock Width High or Low 


83 






ns 




tsu 


Data Setup Time Before Clock Falls 


35 






ns 




«M 


Data Hold Time After Clock Falls 


15 






ns 




twLE 


Width of Latch Enable Pulse 


83 






ns 




l DLE 


LE Delay Time After Falling Edge of Clock 


35 






ns 




*SLE 


LE Setup Time Before Falling Edge of Clock 


40 






ns 




l DHL 


Clock Delay Time Data High to Low 






135 


ns 




•dlh 


Clock Delay Time Data Low to High 






135 


ns 





Recommended Operating Conditions 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


v DD 


Logic supply voltage 


4.5 


5 


5.5 


V 


Vpp 


High voltage supply 


8.0 




375 


V 


V,H 


High-level input voltage 


3.5 




v DD 


V 


V,L 


Low-level input voltage 







0.8 


V 


T A 


Operating free-air temperature 







+85 


°c 



Power-up sequence should be the following: 

1. Connect ground. 

2. Apply V DD . 

3. Set all inputs (Data, CLK. Enable, etc.) to a known state. 

4. Apply Vpp. 

Power-down sequence should be the reverse of the above. 



11-22 



Input and Output Equivalent Circuits 



Vqd O- 



Input 



5 $ 



GND O- 



Logic Inputs 



V DD o- 



Data Out 



GND o- 



Logic Data Output 



HVin 



-o HVqut 




— GND 



High Voltage Outputs 



Switching Waveforms 



Data 
In 



Clock 



Data 
Out 



Data 
Out ' 



Latch 
Enable 



-tsu 



"'WL 



t H 



) (XXXXXX) T^n<XX 



'WH ■ 



X 



-'dhl 



"*DLH 



f 



'dle 



"twLE 



\ 



t S LE 



11-23 



Functional Block Diagram 



Output Enable o- 



LE o- 



Data Input 



Clock 



DIR 



64 bit 
Static Shift 
Register 



64 Latches 




-o HV OU t1 



o HV 0UT 2 



"# 60 Additional 
Outputs 



-o HV ou -r63 



-o Data Out 




o HV OUT 64 



HV31 



Function Table 



Function 


Inputs 


Outputs 


Data 


CLK 


LE 


OE 


DIR 


Shift Reg 

1 2 ... 64 


Latch 

1 2 ... 64 


HV OUT 

1 2 . . . 64 


Dour 


All off 


X 


X 


X 


L 


X 


* * 


* * 


H...H 


* 


Load S/R 


HorL 


I 


L 


L 


H 


H or L...Qn -» Qn+1 


* * 


H...H 


* 




HorL 


I 


L 


L 


L 


HorL...Qn->Qn-1 




H...H 




Load Latch 


HorL 


I 


H 


L 


X 


Hor L...* 


Hor L..* 


H...H 




Output Enable 
Transparent Latch 
Mode 


X 


HorL 


H 


H 


X 


Hor L...* 


HorL...* 


LorH...* 




H 


I 


H 


H 


X 


H...* 


H...* 


L . ..* 




L 


i 


H 


H 


X 


L ...* 


L...* 


H...* 


* 



Notes: 

X - Don't care 

* = Dependent on previous stage's state before the last CLK : High to low transition. 
I = High to low transition 
H = High level 
L = Low level 



11-24 



Pin Configurations 

PG and DG Packages 
HV31 



Pin 


Function 


Pin 


Function 


1 


GND 


41 


N/C 


2 


N/C 


42 


N/C 


3 


HV OUT 59/6 


43 


HVqut 23/42 


4 


HV OUT 60/5 


44 


HVqut 24/41 


5 


HV OUT 61/4 


45 


HVqut 25/40 


6 


HV OUT 62/3 


46 


HVqut 26/39 


7 


HV OUT 63/2 


47 


HVqut 27/38 


8 


HV OUT 64/1 


48 


HVqut 28/37 


9 


DIR 


49 


HVqut 29/36 


10 


Data Out 


50 


HVqut 30/35 


11 


CLK 


51 


HVqut 31/34 


12 


GND 


52 


HVqut 32/33 


13 


V DD 


53 


HVo UT 33/32 


14 


LE 


54 


HVqut 34/31 


15 


Data In 


55 


HVqut 35/30 


16 


OE 


56 


HVqut 36/29 


17 


HV 0UT 1/64 


57 


HVqut 37/28 


18 


HV OUT 2/63 


58 


HVqut 38/27 


19 


HV OUT 3/62 


59 


HVqut 39/26 


20 


HV OUT 4/61 


60 


HVqut 40/25 


21 


HV OUT 5/60 


61 


HVqut 41/24 


22 


HV OUT 6/59 


62 


HVqut 42/23 


23 


N/C 


63 


N/C 


24 


HV OUT GND 


64 


N/C 


25 


HV OUT 7/58 


65 


HVqut 43/22 


26 


HVqutB/57 


66 


HVqut 44/21 


27 


HV ut 9/56 


67 


HVqut 45/20 


28 


HVqut 10/55 


68 


HV 0UT 46/1 9 


29 


HV 0UT 11/54 


69 


HVqut 47/1 8 


30 


HV 0UT 12/53 


70 


HV u T 48/1 7 


31 


HV 0UT 13/52 


71 


HVqut 49/1 6 


32 


HV 0UT 14/51 


72 


HVqut 50/1 5 


33 


HVqut 15/50 


73 


HVqut 51/14 


34 


HVqut 16/49 


74 


HVqut 52/1 3 


35 


HVqut 17/48 


75 


HVqut 53/1 2 


36 


HV 0UT 18/47 


76 


HVqut 54/11 


37 


HV OUT 19/46 


77 


HVqut 55/10 


38 


HVqut 20/45 


78 


HVqut 56/9 


39 


HV OUT 21/44 


79 


HVqut 57/8 


40 


HV 0U t 22/43 


80 


HVqut 58/7 



Package Outline 



64 41 




1 24 
top view 

80-pin Gullwing Package 



Note: 

Pin designation DIR : 
Example: For DIR = 
For DIR = 



= H/L 

: H, Pin 3 is HV 0UT 59 
. L, Pin 3 is HVqut 6 



11-25 



HV33 



32 + 22 Channel Matrix Printhead Driver 
Ordering Information 



Preliminary 



Device 


Package Options 


68 J - Lead 
Ceramic Quad Flatpack 


68 J - Lead 
Plastic Quad Flatpack 


Die 


68 J - Lead 
Ceramic Quad Flatpack 

(MIL-STD-883 Processed*) 


HV33 


HV3304DJ 


HV3304PJ 


HV3304X 


RBHV3304DJ 



For Hi-Rel process flows, please refer to page 5-3 in the Databook 



Features 

□ Separate data (32) and strobe (22) outputs 

□ Independant CLK and BLK functions 

□ 4MHz opertation (either clock) 

□ Latched data outputs 

□ 68-pin QFP 

□ Mil version available 



General Description 

The HV33 is dual serial-to-parallel converter chip originally de- 
signed for driving printheads. Its dual converters have independent 
clock inputs and output blanking logic permitting considerable 
flexibility in driving small matrix arrays with one device. 



Absolute Maximum Ratings 



Supply voltage, V DD 




-0.5V to +7V 


Supply voltage, V PD 




36V 


Supply voltage, V PS 




36V 


Logic input levels 


-0.5V to Vqq + 0.5V 


Continuous total power dissipation 


Ceramic 
Plastic 


1900mW 
1200mW 


Operating temperature range 


Ceramic 
Plastic 


-40°C to +85°C 
0°C to +70°C 


Storage temperature range 




-65°Cto+150°C 



11-26 



HV33 

Electrical Characteristics (over recommended operating conditions unless noted) 
DC Characteristics 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


Conditions 


'dd 


V DD Supply Current 






25 


mA 


f CLK = 4MHz,f DATA = 2MHz 


'ddq 


Quiescent V DD Supply Current 






0.25 


mA 


All V IN = 0V 


Ipp 


High Voltage Supply Current 






0.5 


mA 


Output High and Low 


V OH 


High-Level Data Out 






36 


V 


l OUT = 4mA 


l|H 


High-Level Input Current 






10 


uA 


V IN = High 


k. 


Low-Level Input Current 


-10 






uA 


v IN = ov 



AC Characteristics 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


Conditions 


fcLK 


Clock Frequency 






4 


MHz 




t w 


Clock Width High or Low 


125 






ns 




tsu 


Data Setup Time Before Clock Falls 


50 






ns 




t H 


Data Hold Time After Clock Falls 


20 






ns 




'dhvs 


Delay from -SBL to HV Strobe 






2 


us 


250 pF Load 


'dhvd 


Delay from SCLK/DL to HV Date 






2 


US 


250 pF Load 



Functional Block Diagram 



DLE 



Data In o- 



Data CLK o- 



1 

2 

32-bit 
> Shift 
Register 



32 



32 
Latches 



32 



Mode o 



Strobe In » 




-DSO 



Strobe CLK 



DBL DOE V PD 



Data 
Control 
Logic 



SBL 

L 



Strobe 
Control 
Logic 



Cj>—> HV DATA 1 



' HV DATA 32 



1>-° HV ST robe22 



11-27 



HV34 



64-Channel Serial To Parallel Converter 
With High Voltage Push-Pull Outputs 

Ordering Information 



Device 


Recommended 
Operating 
V pp Max 


Package Options 


80-Lead 
Quad Cerpak 
Gullwing 


80-Lead 
Quad Plastic 
Gullwing 


80-Lead 
35mm TAB 
Tape 


Die 


HV34 


180V 


HV3418DG 


HV3418PG 


HV3418T 


HV3418X 



'For Hi-Rel process flows, please refer to page 5-3 in the Databook. 



Features 

□ HVCMOS® technology 

□ Output voltages up to 180V 

□ Low power level shifting 

□ Shift register speed 



□ Latched data outputs 

Z Output polarity and blanking 

□ CMOS compatible inputs 

□ Forward and reverse shifting options 



Absolute Maximum 

Supply voltage, V DD 



-0.5Vto+15V 



General Description 

The HV34 is a low voltage serial to high voltage parallel converter 
with push-pull outputs. This device has been designed for use as 
a printer driver for ink-jet applications. It can also be used in any 
application requiring multiple output high voltage, low current 
sourcing and sinking capabilities. 

The device consists of a 64-bit shift register, 64 latches, and 
control logic to perform the polarity select and blanking of the 
outputs. A DIR pin controls the direction of data shift through the 
device. With DIR grounded, D, OA is Data-in and D l0B is Data-Out; 
data is shifted from HV 0UT 64 to HV OUT 1 . When Dl R is at logic high, 
D| 0B is Data-in and D, OA is Data-Out: data is then shifted from 
hv out 1 t0 HV 0UT 64. Data is shifted through the shift register on 
the low to high transition of the clock. Data output buffers are 
provided for cascading devices. Operation of the shift regis ter is 
not affected by the LE (latch enable), BL (blanking), or the POL 
(polarity) inputs. Transfer of data from the shift registerto the latch 
occurs when the LE (latch enable) is high. The data in the latch is 
stored during LE transition from high to low. 



Supply voltage, V PP 2 


V DD to+200V 


Logic input levels 


-0.5V to V 0D +0.5V 


Ground current 3 


1.5A 


High voltage supply current 3 


1.3A 


Continuous total power dissipation 4 Ceramic 1900mW 

Plastic 1200mW 


Operating temperature range 


Ceramic -40°C to +85°C 
Plastic 0°C to +70°C 


Storage temperature range 


-65°Cto+150°C 



1 . All voltages are referenced to GNO. 

2. These devices have been designed to be used in applications which either 
switch the Vpp supply to ground before changing the state of the high voltage 
outputs or limit the current through each output. 

3. Connection to all power and ground pads is required. Duty cycle is limited by 
the total power dissipated in the package. 

4. For operation above 25°C ambient derate linearly to 85'C at 1 SmW/°C. 



11-28 



HV34 

Electrical Characteristics (over recommended operating conditions unless noted) 
DC Characteristics 



oynlDUl 


Parameter 


Min 


_yp_ 




Units 


f^onriitinriQ 

vUl IUILIUIIO 


1 

'dd 


V DD Supply Current 










f - 10MH7 f - IOMM7 

t clk - i^ivinz, t data - i^ivinz 
LE = LOW 


l 

'ddq 


Quiescent V DD Supply Current 






of\r\ 

tiUU 


1 1 A 


AIL \/ _ r>\/ r\r \l 

aii v IN - uv or v DD 


1 

Ipp 


High Voltage Supply Current 








50 




\/ „ 1 qaw a 1 1 niitnntQ hinh 

V pp — 1 OU V Ml 1 UU ipu l.o 1 lly 1 1 












n ^n 




\/ — ion\/ All nutniitQ \r\\Ai 
Vpp — lOUV Mil UUipULb IUW 


1... 

■|H 


High-Level Logic Input Current 






10 




V„, - V n n 

V IH V DD 


I.. 


Low-Level Logic Input Current 






-10 


ii A 


V| L - UV 


VoH 


High-Level Output 


HVout 


155 






v 


V nn - 1 80V IHV~, ,-r - -SmA 

v pp — 1 uu v , 11 1 v QUT — 






Data Out 


V„r, -1 V 
DD 1 v 






v 


ID™ ,-r — -1 OOu A 

"-'OUT ' wu r n 


Vol 


Low-Level Output 


HV 0UT 






25 


V 


Vpp = 180V, IHV 0UT = +5mA 






Data Out 






1.0 


V 


ID OUT = +100|iA 


V oc 


HV OUT Clamp Voltage 








V PP +1 .5 


V 


l OL = +5mA 












-1.5 


V 


'ol = -5mA 



AC Characteristics 1 ' 2 (For V DD = 12V: values in parentheses are for V DD = 5V; V pp = 180V, T A = 25°C) 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


Conditions 


f CLK 


Clock Frequency 






12(6) 


MHz 




t w 


Clock Width High and Low 


High 


40(62) 






ns 




Low 


35(42) 






ns 




'su 


Data Setup Time Before Clock Rises 


25(35) 






ns 




t H 


Data Hold Time After Clock Rises 


10(30) 






ns 




f WLE 


Width of Latch Enable Pulse 


62(80) 






ns 




l DLE 


LE Delay Time Rising Edge of Clock 


25(35) 






ns 




'SLE 


LE Setup Time Before Rising Edge of Clock 


30(40) 






ns 




'ON' l OFF 


Time from Latch Enable to HV OUT 






1(1.5) 


us 


C L =20pF 


tDHL 


Delay Time Clock to Data High to Low 






50(110) 


ns 


C u =20pF 


^DLH 


Delay Time Clock to Data Low to High 






75(160) 


ns 


C L =20pF 




All Logic Inputs 






5 


ns 





Notes: 

1 . Shift register speed can be as low as DC as long as Data Set-up and Hold Time meet the spec. 

2. AC Characteristics are guaranteed only under V DD = 12V and V DD = 5V. 



Recommended Operating Conditions 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


V DD 


Logic supply voltage 


V DD = 5V 


4.5 


5.0 


5.5 


V 






V DD =12V 


10.8 


12.0 


13.2 


V 


Vpp 


High voltage supply 


60 




180 


V 


V IH 


High-level input voltage 


V DD -0.9 




V DD 


V 


V IL 


Low-level input voltage 







0.9 


V 


T A 


Operating free-air temperature 









+70 


"C 



Note: 



Power-up sequence should be the following: 

1 . Connect ground. 

2. Apply V DD . 

3. Set all inputs (Data, CLk, Enable, etc.) to a known state. 

4. Apply V pp . 

Power-down sequence should be the reverse of the above. 

11-29 



HV34 



Input and Output Equivalent Circuits 



Vdd o- 



Input 



GND o- 



Logic Inputs 



Vdd o- 



i Data Out 




GND o- 



Logic Data Output 



Vpp o- 



>HV OU T 



GND O- 



High Voltage Outputs 



Switching Waveforms 

Data Input 



Clock 



Diq/Dqi 



Latch Enable 



HVqut 
w/ S/R LOW 



HVout 
w/ S/R HIGH 



50% • 



-t WL . 



Data Valid 



■t H 



50% 



50% 



- l WH- 



■ 50% 



50% 



->DLH • 



-tDHL- 



50% 



^50% ~^ ^50% 



-Idle - 



-'wle- 



' t SLE - 



^1 90% 
NjIO 



10% 



if 



■ *ON ' 



■90% 



50% 



V IL 
V IH 

V H 

Vol 

Vqh 
Vol 

V IH 
Vol 

V 0H 
Vol 

Vqh 
Vol 



11-30 



HV34 



Functional Block Diagram 



POL o- 
BL c- 



Latch Enable o- 



Dioa 



Clock 



DIR 



64 bit 
Static Shift 
Register 



64 Latches 



to 



Vpp 



HVqut-1 



HV 0UT 2 



60 Additional 
Outputs 



' HV OUT 63 




HV OUT 64 



"° DlOB 



Function Table 





Inputs 


Outputs 


Function 


Data 


CLK 


LE 


BL 


POL 


DIR 


Shift Reg 

1 2... 64 


HV Outputs 

1 2... 64 


Data Out 


All on 


X 


X 


X 


L 


L 


X 




H 


H...H 














L 


L...L 




Invert mode 


X 


X 


L 


H 


L 


X 










Load S/R 


H orL 


1 


L 


H 


H 


X 


HorL *...* 






Load 


X 


HorL 


I 


H 


H 


X 


• * • 


* 


* * 




Latches 


X 


HorL 


I 


H 


L 


X 


* » * 




* * 


* 


Transparent 


L 


T 


H 


H 


H 


X 


L 


L 


* * 


* 


Latch mode 


H 


T 


H 


H 


H 


X 


H 


H 


* * 


* 


I/O Relation 


D ,OA 


T 


X 


X 


X 


L 






D,ob 


D,ob 


T 


X 


X 


X 


H 









fill 



Notes: 

H = high level, L = low level, X = irrelevant, T = low-to-high transition^ * high-to-low transition. 
' = dependent on previous stage's state before the last CLK or last LE high. 



11-31 



Pin Configurations 

HV34 



Pin 


Function 


Pin 


Function 


1 


l_IW A H /O/l 

HV 0UT 41/24 


41 


U\/ H IRA 

HV 0UT 1/64 


2 


HV OUT 42/23 


42 


HV OUT 2/63 


3 


HV OUT 43/22 


43 


HV 0UT 3/62 


4 


1 1\ / A A In A 

HV 0UT 44/21 


44 


HV 0UT 4/61 


5 


i IV / A C" lr\n 

HV OUT 45/20 


45 


1 |\ / r- Inn 

HV OUT 5/60 


6 


mi / a a -in. 
H V 0UT 46/1 9 


46 


mi/ cjcn 

HV ut 6/59 


7 


HV OUT 47/18 


47 


HV OUT 7/58 


8 


HV OUT 48/17 


48 


HV 0UT 8/57 


y 


II \ / jqHC 

m v out ^y/i o 


4» 


n Vqut y/^" 


10 


rlvQUj 50/15 


50 


|_J\ / Jft/rr 

MVouT 10/55 


1 1 


HV OUT 51/14 


51 


l_IW 1 H fCA 

HV 0UT i 1/54 


12 


1 |\ / CO/1 o 

H V OUT 52/1 3 


52 


H V 0UT 1 2/53 


13 


HV 0UT 53/12 


53 


■ it| j o tr* r\ 

HV OUT 13/52 


14 


HV 0UT 54/1 1 


54 


HV OUT 14/51 


15 


HV OUT 55/1 


55 


HV OUT 1 5/50 


16 


HV 0UT 56/9 


56 


HV 0UT 1 6/49 


17 


HV 0UT 57/8 


57 


HV 0UT 17/48 


18 


HV 0UT 58/7 


58 


HV 0UT 1 8/47 


19 


Hv 0UT 59/6 


59 


i n j a r\i a n 

" "OUT 1 9 /4 ° 


20 


l it l /-> r\ ir- 

HV 0UT 60/5 


60 


1 it/ r\ r\ iac 

H "out 2 0/ 4 5 


21 


HV OUT 61/4 


61 


1 111 r\A 1 A A 

HV OUT 21/44 


22 


1 ji f /-> f-» in 

HV OUT 62/3 


62 


1 ill r\r\ I Af\ 

HV OUT 22/43 


23 


1 hi nn tr\ 

HV 0UT 63/2 


63 


111/ Afl/iA 

HV OUT 23/42 


24 


HV OUT 64/1 


64 


111 / i-l A I A A 

HV 0UT 24/41 


25 


Vpp 


65 


111/ r\ r- i a r\ 

HV 0UT 25/40 


26 


D|OA 


66 


HV OUT 26/39 


27 


N/C 


67 


HV OUT 27/38 


28 


N/C 


68 


HV OUT 28/37 


29 


BL 


69 


HV OUT 29/36 


30 


POL 


70 


HV OUT 30/35 


31 


V DD 


71 


HV OUT 31/34 


32 


DIR 


72 


HV OUT 32/33 




i Run 

LCI IN U 


/ O 


i-J\/ QO/OO 

n Vqut 33/3^ 


34 


OGND 


74 


HV OUT 34/31 


35 


N/C 


75 


HV OUT 35/30 


36 


N/C 


76 


HV 0UT 36/29 


37 


CLK 


77 


HV OUT 37/28 


38 


LE 


78 


HV OUT 38/27 


39 


D IOB 


79 


HV OUT 39/26 


40 


Vpp 


80 


HV 0UT 40/25 



Note: 

Pin designation for DIR = H/L 

Example: for DIR = H, Pin 1 is HV OUT 41 
for DIR = L, Pin 1 is HV OUT 24 




1 24 



top view 

80-pin Gullwing Package 



11-32 



HV35 



Objective 



275V, 64-Channel Serial to Parallel Converter 
with High Voltage Push-Pull Outputs 

Ordering Information 



Device 


Recommended 
Operating 
V pp Max 


Package Options 


80-Lead 
Quad Cerpak 
Guilwing 


80-Lead 
Quad Plastic 
Guilwing 


80-Lead 
35mm TAB 
Tape 


Die 


HV35 


275V 


HV3527DG 


HV3527PG 


HV3527T 


HV3527X 



*For Hi-Rel process flows, please refer to page 5-3 in the Databook. 



Features 

□ HVCMOS® technology 

□ Output voltages up to 275V 

□ Low power level shifting 

□ Shift register speed 
6MHz @ V DD = 5V 

□ Latched data outputs 

L 1 Output polarity and blanking 
CMOS compatible inputs 

□ Forward and reverse shifting options 



Absolute Maximum Ratings 1 



Supply voltage, V DD 




-0.5V to +6V 


Supply voltage, V PP 2 




V DD to300V 


Logic input levels 


-0.5V to V DD +0.5V 


Ground current 3 




1.5A 


High voltage supply current 3 




1.3A 


Continuous total power dissipation 4 


Ceramic 
Plastic 


1900mW 
1200mW 


Operating temperature range 


Ceramic 
Plastic 


-40°C to +85°C 
0°C to +70°C 


Storage temperature range 




-65°Cto+150°C 



Notes: 

1 . All voltages are referenced to GND. 

2. These devices have been designed to be used in applications which either 
switch the V PP supply to ground before changing the state of the high voltage 
outputs or limit the current through each output. 

3. Connection to all power and ground pads is required, Duty cycle is limited by 
the total power dissipated in the package. 

4. For operation above 25"C ambient derate linearly to 85°C at 1 5mW/°C. 



General Description 

The HV35 is a low voltage serial to high voltage parallel converter 
with push-pull outputs. This device has been designed for use as 
a printer driver for electrostatic applications. It can also be used 
in any application requiring multiple output high voltage, low 
current sourcing and sinking capabilities. 

The device consists of a 64-bit shift register, 64 latches, and 
control logic to perform the polarity select and blanking of the 
outputs. A DIR pin controls the direction of data shift through the 
device. With DIR grounded, D, OA is Data-in and D, 0B is Data-Out; 
data is shifted from HV OUT 64 to HV 0UT 1 . When DIR is at logic high, 
D, 0B is Data-in and D, OA is Data-Out: data is then shifted from 
HV 0UT 1 to HV OUT 64. Data is shifted through the shift register on 
the low to high transition of the clock. Data output buffers are 
provided for cascading devices. Operation of the shift regis ter is 
not affected by the LE (latch enable), BL (blanking), or the POL 
(polarity) inputs. Transfer of data from the shift register to the latch 
occurs when the LE (latch enable) is high. The data in the latch is 
stored during LE transition from high to low. 

A bias pin is used to ensure that the device operates at full V PP 



fill 



11-33 



Electrical Characteristics (over recommended operating conditions unless noted) 
DC Characteristics 



Symbol 


Parameter 


Min 


TvD 


Max 


Units 


Conditions 


'DD 


Vnn SuddIv Current 

DD Mr/ 






25 


mA 


f„ „ = 6MHz !„„, = 3MHz 

'CLK 'DATA ™- 

LE = LOW 


'DDQ 


Quiescent Vi-mi SuddIv Current 






200 


uA 


All V,k, = 0V or V™ 

* IN w v v DD 


Ipp 


High Voltage Supply Current 






0.50 


mA 


Vpp = 275V All outputs high 






0.50 


mA 


V PP = 275V All outputs low 


>M 


High-Level Logic Input Current 






10 


uA 


V |H = Vqq 


III 


Low-Level Logic Input Current 






-10 


uA 


V IL = OV 


V 0H 


High-Level Output 


HV OUT 


200 






V 


Vpp = 275V, IHV OUT = -1 mA 
ID OUT = -100uA 


Data Out 


V D0 -1V 






V 


Vol 


Low-Level Output 


HV OUT 






10 


V 


IHV 0UT =1mA, V DD = 5V 


Data Out 






1.0 


V 


ID OUT =100uA 


Voc 


HV OUT Clamp Voltage 






V PP +1 .5 


V 


Iol = +5mA 


-1.5 


V 


I l = -5mA 



AC Characteristics 12 (For v DD = sv ; v pp = 275V, T A = 25°C) 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


Conditions 


'cLK 


Clock Frequency 






6 


MHz 




t w 


Clock Width High and Low 


High 


62 






ns 




Low 


42 






ns 




'su 


Data Setup Time Before Clock Rises 


35 






ns 




t H 


Data Hold Time After Clock Rises 


30 






ns 




We 


Width of Latch Enable Pulse 


80 






ns 




l DLE 


LE Delay Time Rising Edge of Clock 


35 






ns 




'SLE 


LE Setup Time Before Rising Edge of Clock 


40 






ns 




'on. 'off 


Time from Latch Enable to HV OUT 






1.5 


us 


C L =20pF 


'dhl 


Delay Time Clock to Data High to Low 






80 


ns 


C L =20pF 


'dlh 


Delay Time Clock to Data Low to High 






80 


ns 


C L =20pF 


t„t, 


All Logic Inputs 






5 


ns 





Notes: 

1 . Shift register speed can be as low as DC as long as Data Set-up and Hold Time meet the spec. 

2. AC Characteristics are guaranteed only under V DD = 5V. 



Recommended Operating Conditions 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


V DD 


Logic supply voltage 


4.5 


5.0 


5.5 


V 


Vpp 


High voltage supply 


60 




275 


V 


V,H 


High-level input voltage 


V DD -0.9 




Vdd 


V 


v, L 


Low-level input voltage 







0.9 


V 




Operating free-air temperature 









+70 


°C 



Power-up sequence should be the following: 

1 . Connect ground. 

2. Apply V DD . 

3. Set all inputs (Data, CLK, Enable, etc.) to a known stale. 

4. Apply Vpp. 

Power-down sequence should be the reverse of the above. 



11-34 



HV35 



Input and Output Equivalent Circuits 



V D D o- 



Input o vw- 



GND O- 



Logic Inputs 



Vdd o- 



Data Out 



3 



GND o- 



Logic Data Output 



HVin 



-oHVqut 



— GND 



High Voltage Outputs 



Switching Waveforms 



Data Input 
Clock 

(Dioa/Diob) 
Data OUT 



Latch Enable 



HV 0UT 
w/ S/R LOW 



HV 0UT 
w/ S/R HIGH 



50% 



Data Valid 



- l su • 



■ t H 



-t WL . 



50% 







^^ 50% 



•twH- 



- l DLH ■ 



50% 



-'dhl- 



^50% 



- l WLE- 



50% 



■'SLE- 



.90% 
10% 



• t FF - 



10% 



- 'ON - 



■90% 



50% 



V IH 
V,L 



VOH fi| 

Vol 

Voh 
Vol 

V IH 
Vol 

Voh 
Vol 

Vqh 
Vol 



11-35 



Functional Block Diagram 



HV35 



POL o- 
BL o- 



Latch Enable o- 
Dioa o- 

Clock o- 

DIR c- 



64 bit 
Static Shift 
er 



64 Latches 



=o-=£>[ 



4o 



HV 0UT 1 



HV OUT 2 



60 Additional 
Outputs 



i HV OUT 63 



HV OUT 64 



-o D| OB 



Function Table 





Inputs 


Outputs 


Function 


Data 


CLK 


LE 


BL 


POL 


DIR 


Shift Reg 

1 2.. .64 


HV Outputs 

1 2... 64 


Data Out 

* 


All on 


X 


X 


X 


L 


L 


X 


* * * 


H H...H 


* 


All off 


X 


X 


X 


L 


H 


X 




L L...L 




Invert mode 


X 


X 


L 


H 


L 


X 








Load S/R 


HorL 


t 


L 


H 


H 


X 


HorL *...* 






Load 


X 


HorL 


I 


H 


H 


X 


* * * 


* * * 


* 


Latches 


X 


H or L 


I 


H 


L 


X 


* * * 






Transparent 


L 


t 


H 


H 


H 


X 


L 


L 


* 


Latch mode 


H 


T 


H 


H 


H 


X 


H *...* 


H 


* 


I/O Relation 


D I0A 


T 


X 


X 


X 


L 






D ,OB 


D ,OB 


T 


X 


X 


X 


H 









H = high level, L = low level, X = irrelevant, t = low-to-high transition^! = high-to-low transition. 
• = dependent on previous stage's state before the last CLK or last LE high. 



V BIAS Table 



V BIAS Voltage 


V pp Operating Voltage 


V B1A s = °V/V pp 


V pp = 200V 


V B14S = 80±5V 


V pp = 275V 




V pp can be used with a voltage divider 
to get V Blfls or a separate voltage supply 
can be used for V..... 



11-36 



Pin Configurations 



Package Outline 



HV35 



HV35 



Pin 




Pin 


Funrtiftn 
rui i^jiiui i 


1 


HV™ 41/24 
n v 0UT 4 i'*-** 


41 


H V„, ,-r 1 /64 

nv OUT 


2 


HV™ ,-r 42/23 

1 1 v OUT n£ - /£ - lJ 


42 


H V™ ,-r 2/63 

' 1 v OUT ^ 


3 


HV™ ,-r 43/22 

1 1 v OUT 


43 


H V™ , T 3/62 

n v OUT ut 


4 


HV,-,, ,-r 44/21 

r 1 v OUT 1 


44 


HV ftl ,-r 4/61 

n v OUT ' 


5 


HV„ — 45/9fi 
n v out ta/tw 


45 


HV„ 5/RO 




HV~, rr 46/1 Q 

OUT ^" ' 


46 


HV„, ,-r 6/59 
i i v OUT 




HV 47/1 ft 
n v OUT 4 ' ' ' ° 


47 


HV 7/5ft 
nv OUT //0u 


3 


HV~ .,. 4R/1 7 
n v OUT HO/ 1 ' 


48 


HV« fl/57 
nv OUT 0/0 ' 


9 


HV™ .-r 49/1 6 

i i v OUT ^ ' 


49 


HV™ ,-r 9/56 

OUT «-"-' 


10 


HV„. m 50/1 5 


50 


HV,,. , T 1 0/55 

OUT 


11 


HV^.rr 51/14 

OUT 


51 


HV. irr 11/54 

OUT o" 


12 


HV„, 52/13 
n v OUT 1 ° 


52 


HV™ 1 2/53 
n v OUT 


I o 


HV W1 9 
n v OUT ' ^ 


oo 


HV 1 1/R9 
nv OUT lO'Ot 


14 


HV™ ~. 54/1 1 
n v OUT 1 1 


54 


HV T 14/51 
nv OUT ,H/ Oi 


1 s 


r!V 0UT 00/ ,u 


oo 


hv 1 c;/^n 
iiVqijj i d/ju 


I O 




cc 

oo 


HV 1 R/4Q 


17 


HV~ 57/ft 
n v OUT ° ' ' ° 


57 


HV„ 17/4ft 
n v OUT 1 ' /HO 


18 


HV„ 5R/7 
n v OUT 00/ ' 


58 


H V™ ,. 1 ft/47 
nv 0UT lo/ ^' 


19 


H V™ 5Q/6 

i iv OUT " 


59 


HV™ 1 Q/46 
OUT 


90 


HV RCl/^ 
OUT OU/O 


fin 


HV 9(V4R 

nVQy-r £UY*tO 


91 


L_J\/ AIM 

" V OUT 01/4 


#?i 


H\/ 91My*l 
MV OUT ^l' 44 




nV OUT O^* 3 


R9 
Oc 


HV 99/4*5 




UV fiQ/9 
MV 0UT O* 3 '* 


OO 


HV 9Q/>10 
MV OUT ^0/4^ 




HV R4/1 
nv 0UT OT/ ' 


R4 
Of 


HV 94/41 
nv OUT I 


9t; 
to 


w 

V PP 


OO 


HV DRIAC\ 

n Vqut ^o/4*J 


26 


U I0A 


RR 
OD 


HV 9fi/^Q 
v OUT ^-°'oo 


97 


N/f** 


R7 
Of 


HV 97/Qfl 

nv uT tt'/oo 


9fi 


M/P 


OO 


HV 9ft/'57 
n v OUT 


9Q 


rT 

DL 


RQ 

oy 


HV 9Q/**fi 
"'OUT ^ y '00 


ou 


POL 


7H 


hv ^n/v^ 


O I 


V DD 


71 


HV ^1/^4 

rtVQ|J-r o I/O** 


32 


DIR 


72 


HV '59/'5'5 


33 


^BIAS 


73 


HV OUT 33/32 


34 


GND 


74 


HV OUT 34/31 


35 


N/C 


75 


HVqut 35^30 


36 


N/C 


76 


HV 0UT 36/29 


37 


CLK 


77 


HV 0UT 37/28 


38 


LE 


78 


HV OUT 38/27 


39 


D IOB 


79 


HV 0UT 39/26 


40 


V PP 


80 


HV 0UT 40/25 



Note: 

Pin designation for DIR = H/L 

Example: tor DIR * H, Pin 1 is HV 0UT 41 
for DIR > L, Pin 1 is HV OUT 24 




fill 



11-37 



^ Super tex inc. 



HV36 



High Voltage PIN Diode Driver 
Ordering Information 



Device 


Package 


20 Pin Ceramic DIP 


28 Pin Ceramic J-Lead 


HV3622 


HV3622C 


HV3622DJ 



Features 

□ Processed with HVCMOS® technology 

□ 5V CMOS logic - low power dissipation 
DMOS output voltage up to 220V 

□ Low power level shifting - 5V to 220V 
Z Source current 10mA 

Output fault detection 

□ Latched data output 



PIN diodes in applications such as frequency-hopping radios, 
microwave communication systems and phased array radar. 

Used as a microwave or RF switch, the HV3622 has 4 high- 
voltage P-channel outputs: PD , PD,, PD 2 and PD3. Additional 
controls are Chip Select (CS) and Output Enable (OE) functions. 
The HV3622 also has an output fault detection function that 
protects the outputs from damage by putting them into a high 
impedance state when a short is detected. The HV3622 provides 
4 low-voltage outputs— DRV , DRV, , DRV 2 and DRV 3 — that drive 
the gates of the 4 N-channel FETs in the VN2222NC device. See 
the diagram below for an example of the push-pull output struc- 
ture that these two devices provide. 

For detailed electrical characteristics of the VN2222NC, please 
see the VN22C data sheet in Chapter 8. Currently, the HV3622 is 
only available in through-hole and surface-mount ceramic pack- 
ages that are suitable for military applications, while the VN22C 
is offered in both ceramic quad and discrete packages. For 
commercial product availability, please consult the factory. 



Absolute Maximum Ratings 



Supply Voltage, V cc 


-0.5V to +7.0V 


Logic Input Voltage -0 


3V to VCC + 0.3V 


Supply Voltage V UL 


-5.0V 


Supply Voltage V PP 


+230V 


Max Power Dissipation 


0.8W 


Junction Temperature 


+150 °C 


Storage Temperature Range 


-65 °Cto+150 °C 


Operating Temperature Range 


-55 °C to +125 °C 


Lead Soldering Temperature for 10 Seconds 


+300 °C 



General Description 

The HV3622 is a monolithic high-voltage quad-output driver that 
is designed to be used in conjunction with the Supertex VN2222NC* 
a separate N-channel DMOS FET quad array, whose device char- 
acterics are briefly described below. Together, these devices per- 
form a 220V push-pull function that is especially suited for driving 



' VN2222NC is an N-channel DMOS FET quad array recommended for use in 
conjunction with HV36 outputs to form four 220V push-pull outputs. Each of the 
four devices has a max R D s(ON) of 1-2511, min l D(ON) of 5.0 amps, and BV DSS 
of 220V. 



Push-Pull Configuration 

1 I 



5V 
Digital ^ 
Control 



Vcc 


V HIGH 


CS 


FAULT 


ENA 




— HV36 D ™ 

OE PD0 

• 
• 

DO - D3 PD3 




DRV0 

• 


GND 


• 

DRV3 



OV LL 




11-38 



HV36 

Electrical Characteristics (over recommended operating conditions unless noted) 
DC Characteristics 



Symbol 


Parameter 


Min 


Max 


Units 


Conditions 


'ccq 


Maximum Quiescent V cc Supply Current 




1.0 


mA 


V cc = 5.5V All ouputs open 


'llq 


Maximum Quiescent V LL Supply Current 




4.0 


mA 


V u = -3.5V D RV(N) high or low 


'ppq 


Maximum Quiescent V PP Supply Current 




100 


uA 


V PP = 220V P D(N) high or low 


l|H 


High-level logic current 




10 


\iA 


H = V cc 


l, L 


Low-level loqic current 




10 


HA 


L=0V 


VpH 


Minimum high-level logic output voltage 
(fault detect) 


4.4 




V 


V cc = 4.5V, Ioh = 20hA 


v FL 


Maximum low-level logic output voltage 
(fault detect) 




0.1 


V 


V cc = 5.5V, Iol=-20hA 


V H 


Minimum P D(N) high-level output voltage 


198 




V 


V PP = 203V, l OH =10mA 


v DH 


Minimum P D(N) high-level output voltage 


92.5 




V 


V PP = 100V, V DH =10mA 


DH 


Minimum D RV ^ N j high-level output voltage 


4 




V 


Vrr-= 4.5V, lnu=100uA 


V DL 


Maximum D RvrN , low-output voltage 




-2.3 


V 


V LL =-2.5V, l DL =-500uA 


V TH(min) 


Minimum fault threshold for P D(N , output high 


0.5 x V PP 
fault 




V 


P D(N) = HIGH, 61 = V cc 


VTH(max) 


Maximum fault threshold for P D(N) output high 


0.85 x V PP 
fault 




V 


P D(N) = HIGH, OE = V cc 


V TL(min) 


Minimum fault threshold for P D(N) output Hi-Z 


V,p DN )=0V 




V 


P D(N) = Hi-Z, OE = V oc 


V TL(max) 


Maximum fault thresholdfor P D(N) output Hi-Z 




V (PDN) = 25 


V 


P D(N) =Hi-Z,OE = V cc 



AC Characteristics (over recommended operating conditions unless noted) 



Symbol 


Parameter 


Min 


Max 


Units 


Conditions 


twcs 


Minimum CS pulse to latch data 


100 




nSEC 


V cc = 4.5V, ENA = 0V 


twENA 


Minimum ENA pulse width to latch data 


100 




nSEC 


V cc = 4.5V, CS = 0V 


•woe 


OE pulse width 


10 


50 


us 


V cc = 4.5V, OE = 0V, 
V PP = 220V 

P 0(N) LOAD = 20K to GND 


16 


50 


US 


V PP = 220V, 

P D(N) LOAD = 20K and 

1500pFtoGND 


40 


50 


us 


V PP = 100V, 

P D(N) LOAD = 20K and 

1500pFtoGND 


TT 


Input transition rise and fall times 





200 


nSEC 


V cc = 4.5V 


Tsui 


Minimum set-up time D N and CS to ENA 


150 




nSEC 


V cc = 4.5V 


Tsu2 


Minimum set-up time ENA to OE falling edge 


150 




nSEC 


V cc = 4.5V 


TH 


Minimum hold time 


5 




nSEC 


V CC =4.5V 


CIN 


Maximum input capacitance 




10 


PF 


Not tested, reference only 


TO 


— 

P D(N) transition time from OE low to 

Pd(N) high/low 


1 


15 


us 


V PP = 220V 

P D(N) output loaded by 

20K ohms&1500pFtoGND 




40 


uS 


V PP = 100V, 

P 0(N) output loaded by 

20K ohms& 1500pFtoGND 



urn 



11-39 



HV36 



Recommended Operating Conditions 



Symbol 


Parameter 


Mln 


Max 


Units 


V CC 


Logic Supply Voltage 


4.5 


5.5 


V 




DC Logic Input Voltage 





Vcc 


V 


V LL 


V LL Supply Voltage 


-3.5 


-2.5 


V 


Vpp 


V PP Supply Voltage 


100 


220 


V 




High-State Continuous P D(N) Source Current 




10 


mA 


T A 


Ambient Operating Temp 


-55 


+ 125 


°C 


CL 


D RV(N) Load Capacitance 





0.006 





1 . V w rise time (dv/dt) should be less than 50V/uS. 

2. Power-up sequence should be the following: 

A) Connect ground; 

B) Apply V^; 

C) Apply V^; 

D) Apply V u ; 

E) Set all inputs to a known state. Power-down sequence should be the reverse of the above. 



Function Table 



Input 


Out) 


>ut 


CS 


ENA 


OE 


Data 

D (N) 


Level 2 


Internal 
Latch Q(N) 


P D(N) 


D RV(N) 


Fault 


H 


X 


H 


X 


Pass 


Previous State 


Previous State 


Previous State 


VFH 


X 


H 


H 


X 


Pass 


Previous State 


Previous State 


Previous State 


VFH 


L 


L 


H 


H 


Pass 


Set 


Previous State 


Previous State 


VFH 


L 


L 


H 


L 


Pass 


Reset 


Previous State 


Previous State 


VFH 


L 


L 


H>L 


H 


P/F 


Set 


VDH 


VDL 


VFH 


L 


L 


H>L 


L 


P/F 


Reset 


Hl-Z 


VDH 


VFH 


H 


X 


H>L 


X 




Previous State 
















P/F 


Set 


VDH 


VDL 


VFH 










P/F 


Reset 


Hl-Z 


VDH 


VFH 


X 


H 


H>L 


X 




Previous State 
















Pass 


Set 


VDH 


VDL 


VFH 










Pass 


Reset 


Hl-Z 


VDH 


VFH 


X 


X 


H 


X 


Fail 




Hl-Z 


VDL 


VFL 


(At Power Up) 


X 


X 


X 


X 


P/F 


Set 


VDH 


VDL 


VFH 



Notes: 

1 . X indicates "Don't Care" input state (L or H). 

2. The output threshold is internally tested for each P D(N) output; the pass condition occurs when OE = H and: 

A) P D (N) driving high with output > V TH (M ax>. or mav occurs if P D(N) driving high and output > V TH (MlN) and < V-n_ (MAX) . 

OR 

B) Pd(n> driving Low with output < V TH ( MiN j, or may occur if Pn(N) driving low and output < V TH <max) ar| d < Vtl {min>- 
The f ail condition occurs when OE = H and conditions for "pass" are not satisfied. 

3. Fault output = V FL indicates a fault has been detected in at le ast one of the P D(N) output loads when OE = H. All other outputs shall function normally when a fault 
condition has been detected for one of the outputs. The Fault output shall remain in the low state, regardless of the state of the output which initiated the fault status, until 
the next falling edge of OE. Whenever OE = L, the Fault output is forced to V FH , and the fault latch is reset. If the fault condition persists, the fault response repeats each 
time the OE input is set to H. 

4. H>L indicates falling edge (H to L). 

5. Hl-Z indicates no current is sourced to output Pq(N)- 

6. P/F indicates "Pass" or Tail" fault threshold conditions. 



11-40 



Functional Block Diagram 



v PP O Vu_ 

Vcc O -i 

•# GND 



OE O- 



Do O- 



ENA 

CS 



D, O- 



<— CjSet 

T 



D 2 O- 



D 3 O- 



Q 

Latch 
Set 



ii-C 



Q 

Latch 



Q 

Latch 



i— CjSet 

z 



Timing Diagram 



Q 

Latch 



•-q Set 



FF 
CLK 
Set 



FF 
"-ClCLK 



Sel 
Y 



FF 
CLK 
Set 



FF 
L-ClCLK 
Set 



Power-Up 
Circuit 



HV36 



Drive Circuit 



Gate Control 
Circuit 



Voltage 
Sense 



Drive Circuit 
1 



Drive Circuit 
2 



Drive Circuit 
3 



4 



Vpp 



-O Pdo 



-O D RV0 



-O P D 1 
-O D RV1 



-O P D2 

-O D RV 2 



— O PD3 
— O D RV3 



-O Fault 



DATA LOW 

andCS 



OE 



Pdin) 



Drv(N) 



« t wcs 1 

7 







-tsui- 



10% X 12%^ 



-tWENA- 



-'WOE- 



-'SU2- 



-tOH- 



11-41 



Pin Configurations 



20 Pin, 300 Mil Wide Package 



Pin 


Function 


Pin 


Function 


1 


D, 


11 


Pdo 


2 


D 2 


12 


D RV1 


3 


D 3 


13 


D RV2 


4 


V LL 


14 


Vpp 


5 


GND 


15 


Vcc 


6 


Drv3 


16 


ENA 


7 


D RV2 


17 


OE 


8 


P D3 


18 


CS 


9 


Pd2 


19 


Fault 


10 


Pdi 


20 


D 


-Lead Package 






Pin 


Function 


Pin 


Function 


1 


D, 


15 


PD, 


2 


D 2 


16 


PD„ 


3 


D 3 


17 


NC 


4 


NC 


18 


DRV, 


5 


v LL 


19 


DRV 


6 


GND 


20 


NC 


7 


NC 


21 


Vpp 


8 


DRV 3 


22 


NC 


9 


DRV 2 


23 


Vcc 


10 


NC 


24 


EN 


11 


PD 3 


25 


OE 


12 


NC 


26 


CS 


13 


PD 2 


27 


Fault 


14 


NC 


28 


Do 


00 Mil Wide Package 






Pin 


Function 


Pin 


Function 


1 


S 


11 


S 


2 


S 


12 


S 


3 


S 


13 


NC 


4 


Gi 


14 


D 4 


5 


G 2 


15 


D 3 


6 


G 3 


16 


D 2 


7 


G 4 


17 


D, 


8 


S 


18 


NC 


9 


S 


19 


S 


10 


S 


20 


S 



Package Outline 



H 

s 



20 Pin, 300 Mil Wide DIP 
HV3622C 



is] [24] I21I [ioj 



- + - 



iH 
E 

-a 
1 



[sj Lej izj LeJ L§J N N 

28-pin J-Lead Package 
HV3622DJ 





J 20 1 




XI 


1 3 


ifi 


LX 


XI 


LX 


X 


LX 


X 


LX 


X 


LX 


X 


1 9 


121 


LX 


X 



20 Pin, 300 Mil Wide DIP 
VN2222NC 



11-42 



HV38 



Preliminary 



32-Channel Gray-Shade Display Column Driver 
Ordering Information 



Device 


Package Options 


64-Lead 3-sided 
Plastic Gullwing 


80-Lead 
Ceramic Gullwing 


Die 


80-Lead Ceramic Gullwing 

(MIL-STD-883 Processed*) 


HV38 


HV3806PG 


HV3806DG 


HV3806X 


RBHV3806DG 



For Hi-Rel process flows, refer to page 5-3 of the Databook. 



Features 

□ 5V CMOS inputs 

□ Up to 60V modulation voltage 

□ Capable of 1 6 levels of gray shading 

□ 16MHz data throughput rate 

C 32 Outputs per device (can be cascaded) 

7 Minimum 15 mA high-voltage output source/sink capability 

□ Pin-programmable shift direction (DIR) 

□ D/A conversion can be performed in as little as 3.2ns 

□ Diodes in output structure allow usage 
in energy recovery systems 

□ Integrated high-voltage CMOS technology 

□ Available in 3-sided 64-lead gullwing package or as dice 



Absolute Maximum Ratings 



Supply voltage, V DD ' 


-0.5V to +7.5V 


Supply voltage, V P p,/Vp P2 


-0.5V to +60V 


Logic input levels 1 


-0.5 to V DD + 0.5V 


Ground current 2 


1.5A 


Continuous total power dissipation 3 


Plastic 1200mW 




Ceramic 1500mW 


Operating temperature range 


-40°C to +85°C 


Storage temperature range 


-65°C to+150°C 


Lead temperature 1.6mm (1/16 inch) 


260°C 


from case for 1 seconds 





General Description 

The HV38 is a 32-channel column driver IC designed for gray- 
shade display use. A bidirectional shift register working on both 
clock edges is used to index input data, in groups of 4, into a set 
of data latches. These are compared to the contents of a master 
binary counter. Each time the master counter begins to increment, 
a hold capacitor (C H ) on each channel is charged until the 
contents of the data latches is matched by that in the counter. 
Each channel's C H thus is charged to an individual level, V H , which 
is then transferred to the output by a source-follower structure that 
allows both sourcing and sinking of output current. 

DIR is a shift-direction-select pin which has been provided to allow 
the user to interchange the shift register data input . When the DIR 
input is high, data is shifted in thru D1 to D4 in ascending order 
from HVou T 1 to HV OUT 32. When the DIR input is low, data is 
shifted in descending order from HV OUT 32 to HV 0UT 1. 

In the HV38, the ramp generator circuitry (V R ) obtains its (low- 
current) bias from V PP1 . This allows the output bias, V PP2 , to be 
ramped down to zero when output current is not required, thus 
saving energy. 



ill 



1 . All voltages are referenced to V ss . 

2. Duty cycle is limited by the total power dissipated in the package. 

3. For operation above 25°C ambient, derate linearly to 70°C at 1 2mW/°C. 



11-43 



HV38 



Electrical Characteristics (at 25°C, unless otherwise specified) 
Low-Voltage DC Characteristics 



Symbol 


Parameter 


Min 


Typ 1 


Max 


Units 


Conditions 


Vqq 


Low-voltage supply 


4.5 


5.0 


5.5 


V 


f sc = 8MHz 


'dd 


Vqq supply current (active) 




6.0 


10.0 


mA 


f cc = 6MHz 
f data = 8MHz 


'dds 


Vqq supply current (standby) 






100 


uA 


All V 1N = 0V, V DD = min 




High-level input voltage 


V D d-1 




V DD 


V 




v IL 


Low-level input voltage 







1 


V 




I.H 


High-level input current 




1.0 


50 


UA 


V IH = V DD 


l,L 


Low-level input current 




-1.0 


-50 


uA 


V| L = OV 


C|N 


Input capacitance (data, LC, SC, CC) 






10 


PF 


V IN = 0V,f=1MHz 


T A 


Operating free-air temperature 


-40 




85 


°C 




Vqh 


High-level output voltage 


Vdo-1 






V 


'oh = -4mA, V DD = min 


Vol 


Low-level output voltage 






0.4 


V 


l 0L = 4mA, V DD = min 


'oh 


High-level output current 






-4.0 


mA 




IdL 


Low-level output current 






4.0 


mA 





Note 1. All typical values are at V 00 = 5.0V. 



High-Voltage DC Characteristics 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


Conditions 


V PP 


High-voltage supply 


-0.3 




60 


V 




lp P 


V P p supply current 






100 


uA 


Vpp = 60V, outputs 
high or low, no load 


V R 


Ramp voltage 







Vpp-2 


V 





Uoh max 


Maximum high-voltage analog output source current 1 






-15 


mA 


Vpp = 60V 


'aoh 


High-voltage analog output source current 1 


-10 






mA 


Vpp = 60V 

V R = 30V, V AO = 25V 


-100 






uA 


V AO = 28.75V 


l AOL max 


Maximum high-voltage analog output sink current 2 






15 


mA 


V PP = 60V 


Iaol 


High-voltage analog output sink current 2 


10 






mA 


Vp P = 60V 

V R = 30V, V AO = 25V 


100 






uA 


V AO = 31.25V 



Notes: 

1 . Either by N-CH transistor or P-CH output diode. 

2. Either by P-CH transistor or N-CH output diode. 

3. Power-up sequence should be the following: 
1 . Connect ground. 

2 Apply V DD . 

3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 

4. Apply V PP . 

Power-down sequence should be the reverse of the above. 



11-44 



HV38 



Electrical Characteristics 

AC Characteristics (V DD = 5V, T A = 25°C) 
Logic Timing 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


Conditions 


f sc 


Shift clock operating frequency 






8 


MHz 




'din 


Data-in frequency 






16 


MHz 




'ss 


Ascent/Descent pulse to shift clock setup time 




20 




ns 




l HS 


Ascent/Descent pulse to shift clock hold time 




40 




ns 




w 


Ascent pulse width 




55 




ns 






Data to shift clock setup time 









ns 






Data to shift clock hold time 




50 




ns 




two 


Data-in pulse width 




55 




ns 




'wLC 


Load count pulse width 




200 




ns 




'dlcr 


Load count to ramp delay 






100 


ns 




•dlcc 


Load count to count clock delay 




70 




ns 




Wc 


Load count pulse width 




200 




ns 




l DSL 


Shift clock to load count delay time 




200 




ns 




tcsc 


Shift clock cycle time 






125 


ns 




tccc 


Count clock cycle time 


190 






ns 




'wee 


Count clock pulse width 


90 






ns 





Vramp Timing 



Symbol 


Parameter 


Min 


Typ 


Max 


Units 


Conditions 


*CR 


Cycle time of ramp signal 


8 






US 




•rr 


Ramp rise time 


3 






us 




Ihr 


Ramp hold time 


2 






US 




t F R 


Ramp fall time 


3 






us 




'dRRP2 


Rise time delay from V R to V PP2 


TBD 






us 




f HP2 


V PP2 hold time 


TBD 






us 




'rP2 


V PP2 ramp-up time 


TBD 






us 




'fP2 


V PP2 ramp-down time 


TBD 






us 




WrP2 


Fall time delay from V R to V PP2 


TBD 






us 





11-45 



HV38 



Timing Diagrams 

(a) Basic System Timing 




(b) Detailed Device Timing 




Data 
(D1-D4) 



NEXT LOADING CYCLE - 



r^x^j - 



V DATA V DATA N/ DATA ^ ^~\V DATA V DATA V DATA V DATA V DATA V ^~\f 
A SET 1 A SET2 A SET 3 A A SET 31 A SET 32 /\ SET 1 A SET 2 A SET 3 A A 



DATA 
SET 31 



Load Count 
(LC) 



k-tDSL — 



Count Clock 
(CC) 



' cc c - 
7 Count ^ h A ~nnnt\ 



Clock 1 Clock 16 



11-46 



HV38 



Pin Definitions 



Pin # 


Name 


Function 


27-30 


D1-D4 


Inputs for binary-format parallel data 


26 


Shift clock 


Triggers data on both rising and falling edges. This implies that the data rate is always twice the clock 
rate (data rate = 16MHz max if clock rate = 8MHz max) 


22 


Ascent 


Input pin for the Ascent pulse (when DIR is high). Output pin for Descent pulse (when DIR is low). 


43 


Descent 


Input pin for the Descent pulse (when DIR is low). Output pin for the Ascent pulse (when DIR is high). 


40 


I c\ac\ f"!m int 


Inntit fnr a nulce* uuhnco ricinn oHnp rai icoq data frnm tt\o inmit latfhao tn ontor tho rnmnaratnr latz-hoc 

and whose falling edge initiates the conversion of this binary data to an output level (D-to-A). 


42 


Count Clock 


Input to the count clock generator whose increments are compared to the data in the comparator latches. 


18,47 


V R 


High-voltage ramp input for charging the output stage hold capacitors (C H ). This input can be linear or 
non-linear as desired. 


32 


DIR 


When this pin is connected to V DD , input data is shifted in ascending order, i.e. corresponding to HV 0UT 1 
to HV OUT 32. When connected to LVGND, input data is shifted in descending order, i.e. corresponding to 

nv OUT J ^ TO nv OU"P ■ 


Q1 
o I 


LVOINU 


This is ground for the logic section. It may be connected to the HVGND pin, or kept separate in energy 
recovery circuits. 




nvuiNU 


i nib ib yruuiitj iui uits iiiyii-vuiiayt? ^uuipmj becuon. \i may ue conneciea io ine lvoinu pin, or Kept 
separate in energy recovery circuits. 


19,46 


Vpp 1 


This innut hiasps thp IpvpI translators anri thp P-rhannpl transistors that rhamp thp hnlHinn ran? (C. .\ 


17,48 


V pp 2 


This input biases the output source followers. It can be set equal to V PP 1 or can be ramped (especially in 
energy recovery schemes). 


1-16 
49-64 


HV 0UT 1- 
HV OUT 32 


High-voltage source-follower outputs. 


33 




Low-voltage logic power supply. 




EL Panel Connections 



Data Bus — 
(4) ZZ 
DIR = LOW 
V R , Vpp, , Vpp 2 
LVGND, HVGND, — 
SC, LC, CC, Descent 



LVGND, HVGND, ~ 
SC, LC, CC, Ascent 
DIR = HIGH 



Data Bus 
(4) 

















32 1 




32 


1 




32 


1 



EL 
Panel 
(Example) 



1 32 




1 


32 




1 32 




N 






=> 





I! 



11-47 



HV38 



Theory of Operation 

The HV38 has two primary functions: 

1 ) Loading data from the data bus and, 

2) Gray-shade conversion 

(converting latched data to output voltages). 

Since the device was developed initially for electroluminescent 
displays, the operation will be described in terms that pertain to 
that technology. As shown by the Typical EL Drive Scheme, 
several HV38 packages are mounted at the top and bottom of a 
display panel. Data exists on a 4-bit bus (adjacent PC board 
traces) at top and bottom. The D1 through D4 inputs of each chip 
take data from the bus when either an ASCENT or DESCENT 
pulse is present at the chip. These pulses therefore act as a 
combination CHIP SELECT and LOCATION STROBE. Because 
of the way the chip HV 0UT pins are sequenced, data on the bus at 
the bottom of the display panel will be entered into the left-most 
chip as HV OUT 1 HV 0UT 2 etc. up to HV OUT 32. The ASCENT pulse 
will accomplish this with DIR = High. 

Loading Data from Data Bus 

Here is the full data-entry sequence: 

1) The microcontroller puts data on the bus (4 bits) 

2) To enter the data into the 32 sets of 4 latches on the first chip, 
the shift clock rises. This positive transition is combined with 
the ASCENT pulse (sometimes called a SEED BIT) and is 
generated only once to strobe the data into the first set of 
latches. (These latches eventually send data to the HV OUT 1). 
The data on the bus then changes, the shift clock falls, and this 
negative transition is combined with the ASCENT pulse, which 
is now propagated internally, to strobe the new data into the 
next set of 4 latches (which will end up as HV OUT 2). This 
internal ASCENT pulse therefore runs at twice the shift clock 
rate. 

3) When the last set of 4 latches in the first chip has been loaded 
(HV OUT 32), the ASCENT pulse leaves chip 1 and enters chip 
2. The exit pin is called DESCENT and the chip 2 entry pin is 
ASCENT. For chips at the top of the panel things are reversed: 
DIR is low, entry pins are DESCENT and exit pins are AS- 
CENT, because the data-into-latches sequence is in descend- 
ing order, HV OUT 32 down to HV 0UT 1. 



4) The buses may of course be separate, and data can be strobed 
in on an interleaved basis, etc. , but those complications will be 
left to systems designers. 

When data has been loaded into all 32 outputs of all chips (top and 
bottom of the display panel), the load count pin is pulsed. On its 
rising transition, all the data in the input latches is transferred to 
a like number of comparator latches, (thus leaving the data 
latches ready to receive new data during the following opera- 
tions). After the transfer, the load count pin is brought low. This 
transition begins the events that convert the binary data into a 
gray-shade level. 

Gray-shade Conversion 

1 ) The COUNT CLOCK is started. This external signal is applied 
to the COUNT CLOCK pin, causing the counter on each chip 
to increment from binary 0000 to 1 1 1 1 (0 to 1 5). 

2) At the same time, the V B voltage is applied to all chips, via 
charging transistors, causing the HOLD CAPACITORS (C H ) on 
each output to experience a rise in voltage. 

3) If each set of comparator latches held binary 1111 (a count of 
1 5), the V R voltage would charge each C H to the full value of V R . 
The voltage followers on each output would thus present this 
level as a maximum-brightness output to the panel. 

4) On the other hand, if the count in the comparator latches is less 
than maximum, when the COUNT CLOCK had incremented 
the master countertoa value that matched the latch value, that 
particular charging transistor would be cut off, leaving that C H 
at some other value of voltage (gray-shade level). 

It should be clear that : 

a) Data continues until all latches in all chips are loaded. The shift 
clock and the internal ASCENT/DESCENT pulses last for the 
same duration. 

b) Count clock endures for 1 6 counts after load count goes low. 



Function Table 



Sequence 


Function 


DIR 


Data-in 
(D1 - D4) 


Ascent 


Descent 


Shift 
Clock 


Load 
Count 


Count 
Clock 


Vr 


1 


Shift Data 

from HV OUT 1 to 32 


H 


H/L 




Output 


_n_ 


L 


L 


L 


2 


Shift Data 

from HV OUT 32 to 1 


L 


H/L 


Output 




_n_ 


L 


L 


L 


3 


Load Shift Register 


X 


X 


Pre-defined by 1 or 2 


_n_ 


L 


L 


L 


4 


Load Counter 


X 


X 


L 


_n_ 


L 


L 


5 


Counting/Voltage 
Conversion 


X 


X 


L 


L 




Initiates 

V RAMP 



11-48 



HV38 



Functional Block Diagram 



See Output Stage detail below 



Dir - 
Dlr - 




Seed I/O 
Buffers 
(Left) 



Internal 




Shift 


Strobe 




Clock 


Generator 




Generator 



eS3 



MM 



Dir Dir 

J_L 



Direction- 
ality 



Load 


Count 


Count 


Clock 


Buffers 


Generator 



Seed I/O 
Buffers 
(Right) 



-Dir 
-5if 



H ED 



Descent 



" Uses both clock edges. 



Output Stage Detail 




fill 



11-49 



Pin Configuration 



HV38 



64-Pin 
Pin 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

17 

18 

19 

20 

21 

22 



PG Package 
Function 

HV 0UT 1 

HV 0UT 2 

HV 0UT 3 

HV OUT 4 

HV OUT 5 

HV 0UT 6 

HV 0UT 7 

HV 0UT 8 

HV 0UT 9 

HV OUT 10 

HV 0UT 11 

HV 0UT 12 

HV OUT 13 

HV OUT 14 

HV OUT 15 

HV OUT 16 

Vpp 2 

Vq 
Vrp, 
HVGND 
NC 

ASCENT 



Pin Function 

23 NC 
NC 
NC 

Shift Clock 
D 4 



24 
25 
26 
27 
28 
29 
30 
31 
32 
33 
34 
35 
36 
37 
38 
39 
40 
41 
42 
43 
44 



D 2 

E>i 

LVGND 

DIR 

V DD 

NC 

NC 

NC 

NC 

NC 

NC 

Load Count 
NC 

Count Clock 

DESCENT 

NC 



Pin Function 

45 HVGND 

V PP1 
V R 

Vpp 2 

HV 0UT 17 
HV 0UT 18 
HV OUT 19 
HV OUT 20 
HV 0UT 21 
HV 011T 22 



, n nnn n n n nnnnnnnnn, 



46 
47 
48 
49 
50 
51 
52 
53 
54 
55 
56 
57 
58 
59 
60 
61 
62 
63 
64 



v OUT< 

HV OUT 23 
HV OUT 24 
HV OUT 25 
HV OUT 26 
HV OUT 27 
HV OUT 28 
HV OUT 29 
HV OUT 30 
HV OUT 31 
HV OUT 32 



*Pins 65 to 80 are NC (ceramic only) 



Gray Shade Decoding Scheme 



Brightest 
Shade No. 


D4 


D3 


D2 


D1 




15 




1 


1 


1 


Brightest 


14 




1 


1 







13 




1 





1 




12 




1 










11 







1 


1 




10 







1 







9 










1 




8 















7 





1 


1 


1 




6 





1 


1 







5 





1 





1 




4 





1 










3 








1 


1 




2 








1 







1 











1 



















Dimmest 




25 40 
top view 

3-sided Plastic QFP 64-pin Gullwing Package 



64 



41 




top view 
80-pin Gullwing Package 
80-pin Ceramic Gullwing Package 



11-50 



^ Superteic inc. 



HV41 
HV42 



32-Channel Serial To Parallel Converter 
With P-Channel Open Drain Outputs 

Ordering Information 



Device 


Package Options 


44 J-Lead Quad 
Ceramic Chip Carrier 


44 J-Lead Quad 
Plastic Chip Carrier 


Die 


44 J-Lead Quad 
Ceramic Chip Carrier 

(MIL-STD-883 Processed*) 


HV41 


HV4122DJ 


HV4122PJ 


HV4122X 


RBHV4122DJ 


HV42 


HV4222DJ 


HV4222PJ 


HV4222X 


RBHV4222DJ 



* For Hi-Rel process flows, please refer to page 5-3 in the Databook 



Features 

□ Processed with HVCMOS® technology 

□ Output voltages to -225V 

□ Source current minimum 80mA 

□ Shift register speed 8MHz 

□ Strobe and enable inputs 

□ CMOS compatible inputs 

□ Forward and reverse shifting options 

□ 44-lead plastic and ceramic surface mount packages 

□ Hi-Rel processing available 

□ Can be used with the HV51 and HV52 to provide 
200V push-pull operation 



Absolute Maximum Ratings 



Supply voltage, V DD 1 




+0.5V to -15.5V 


Off state output voltage 1 




+0.5V to -250V 


Logic input levels 1 


+0.5V to V DD - 0.5V 


Ground current 2 




1.5A 


Continuous total power dissipation 4 Ceramic 

Plastic 


1500mW 
1200mW 


Operating temperature range 


Commercial 
Military 


-40°C to +85°C 
-55°Cto+125°C 


Storage temperature range 




-65°Cto+150°C 


Lead temperature 1.6mm (1/1 f 
from case for 1 seconds 


i inch) 


260°C 



Notes: 

1 . All voltages are referenced to Vgg. 

2. Duty cycle is limited by the total power dissipated in the package. 

3. For operation above 25°C ambient, derate linearly to 85°C at 15mW/°C. 



General Description 

The HV41 and HV42 are low voltage serial to high voltage parallel 
converters wtih P-Channel open drain outputs.These devices 
have been designed for use as drivers for AC electroluminescent 
displays. They can also be used in any application requiring 
multiple output high voltage current source capabilities such as 
driving inkjet and electrostatic print heads, plasma panels, or 
vacuum fluorescent displays. 

These devices consist of a 32-bit shift register and control logic to 
perform the Output Enable and All-ON functions. Data is shifted 
through the shift register on the logic high to low transition of the 
clock. The HV41 shifts in the counterclockwise direction when 
viewed from the top of the package and the HV42 shifts in the 
clockwise direction. A data output buffer is provided for cascading 
devices. This output reflects the current status of the last bit of the 
shift register. Operation of the shift register is not affected by the 
OE (Output Enable) or the STR (Strobe) inputs. 

For applications requiring active pull down as well as pull up, the 
HV41 and HV42 can be paired with the HV52 and HV51 devices, 
respectively. 



11-51 



HV41/HV42 

Electrical Characteristics (over recommended operating conditions unless noted) 
DC Characteristics (voltages referenced to V ss ) 



^umhnl 
>■» y 1 1 1 u\j ■ 


Paramptpr 

rai oiiicici 


Min 


Max 


Units 


Conditions 


'dd 


Vqq supply current 

• 




-15 


mA 


f CLK = 8 MHz 
Fdata = 4 MHz 


'ddq 


Quiescent V DD supply current 




-100 


uA 


ALL V IN = 0V 


'o(OFF) 


Off state output current 




-100 


HA 


All SWS parallel 


I.H 


High-level logic input current 




-1 


|iA 


V ]H = -12V 


k 


Low-level logic input current 




+1 


uA 


V lL = OV 


V OH 


High-level output data out 


V DD + 1.0V 




V 


l Dou , = -100uA 


Vol 


Low-level output voltage 


HVout 




-30.0 


V 


l HVout = -80mA 


Data out 




-1.0 


V 


l Dou , = -100(iA 


Vqc 


HV OUT clamp voltage 




+1.5 


V 


l OL = +80mA 


AC Characteristics (@ v DD = -12V, v ss = ov) 


Symbol 


Parameter 


Mm 


Max 


Units 


Conditions 


'cLK 


Clock frequency 




8 


MHz 




'WH^WL 


Clock width high or low 62 




ns 




•su 


Data set-up time before clock rises 


50 




ns 




t H 


Data hold time after clock rises 


20 




ns 




toN 


Turn ON time, HV 0UT from enable 




400 


ns 


R L = 1 0K to -225V 


l DHL 


Delay time clock to data high to low 




100 


ns 


C L = 15pF 


l DLH 


Delay time clock to data low to high 




100 


ns 


C L = 15pF 



Recommended Operating Conditions 



Symbol 


Parameter 


Min 


Norn 


Max 


Units 


V DD 


Logic supply voltage 


-10.8 


-12 


-13.2 


V 


Voo 


Output off voltage 


+0.3 




-225 


V 


V,H 


High-level input voltage (LOGIC "1") 


V DD + 2V 




v DD 


V 


V,L 


Low-level input voltage (LOGIC "0") 







-2.0 


V 


fci_K 


Clock frequency 






8 


MHz 


T A 


Operating free-air temperature 


Commercial 


-40 




+85 


C 


Military Hi-Rel (RB) 


-55 




+125 


°C 



Note : All voltages are referenced to V ss . 



11-52 



HV41/HV42 

Input and Output Equivalent Circuits 



Vss o- 



Input o- 



Vdd o- 



Logic Inputs 



Vss o- 




• Data Out 



Vdd o- 



Logic Data Output 



- Vss 



>HV OU T 



High Voltage Output 



Switching Waveforms 

— - (XXX X xxxx> ~ 

tsu t H ►] 

— \ y \ 



Clock 



Data Out 
Data Out 

Enable 
HVout 



- { WH- 



-t WL . 



- 50% 



^| ^50% 



*DLH 



4^50% 



*DHL 

^50% 



2V 

V SS 
V SS-12 

Vss 



V SS-12 

V SS 
V SS-12 

V SS 
V SS-12 



Voo 



ill 



11-53 



Functional Block Diagram 



V S S o- 
Strobe o- 
Output Enable o- 



Dala Input o- 



Clock o- 



DataOut o- 



32-Bit 
Static Shift 



=D =0 



D =D 



=D =t> 



4> 



HV41/HV42 



-o HV 0UT 1 



I o 



HV 0UT 2 



(Outputs 3 to 30 
not shown) 



-o HV OUT 31 



HV OUT 32 



Function Table 





Inputs 


Outputs 


Function 


Dl 


CLK 


OE 


STR 


Shift Reg 


H V Outputs 


Data Out 




1 2... 32 


1 2... 32 


* 


All on 


X 


X 


X 


L 


* * * 


All On 


* 


All off 


X 


X 


L 


H 


* * * 


All Off 




Load S/R 


HorL 


1 


L 


H 


HorL *...* 


OnorOff *...* 




Output enable 


X 


HorL 


H 


H 


* * * 


On or Off *...* 


* 



Notes: 

X = Not relevant to the output state. 

* - Dependent on previous stage's state before the last CLK : High to low transition. 

A logic high bit in the shift register will turn on the corresponding output when the strobe and output enable inputs are both high. 
1 = High-to-low transition, -12V to V ss 
H = High level = -12V 
L = Low level = 0V 



11-54 



HV41/HV42 



Pin Configurations 

HV41 

44 Pin J-Lead Package 



Pin 


Function 


Pin 


Function 


1 


HV OUT 17 


23 


Output Enable 


2 


HV OUT 18 


24 


Clock 


3 


HV 0UT 19 


25 


V ss 


4 


HV 0UT 20 


26 


V DD 


5 


HVqut 21 


27 


Strobe 


6 


HV 0UT 22 


28 


Data In 


7 


HV 0UT 23 


29 


HV 0UT 1 


8 


HV 0UT 24 


30 


HV OUT 2 


9 


HV 0UT 25 


31 


HV 0UT 3 


10 


HV 0UT 26 


32 


HVqut 4 


11 


HV OUT 27 


33 


HVqut 5 


12 


HV 0UT 28 


34 


HVqut 6 


13 


HV OUT 29 


35 


HVqut 7 


14 


HV OUT 30 


36 


HVqut 8 


15 


HV OUT 31 


37 


HVqut 9 


16 


HV 0UT 32 


38 


HVqut 10 


17 


N/C 


39 


HVqut 11 


18 


Data Out 


40 


HVqut 12 


19 


N/C 


41 


HVqut 13 


20 


N/C 


42 


HVqut 14 


21 


N/C 


43 


HVqut 15 


22 


N/C 


44 


HVqut 16 



Package Outline 



[40 
|44 

Q 

[I 

LI 

d 



39l[3il[37l|36l[3^|Ml[3i1|32l[iT|[30][29| 



26] 
25l 



- 23j 

iil 



20 1 



top view 
44-pin J-Lead Package 



HV42 

44 Pin J-Lead Package 



Pin 


Function 


Pin 


Function 


1 


HVqut 16 


23 


Output Enable 


2 


HVqut 15 


24 


Clock 


3 


HVqut 14 


25 


V SS 


4 


HVqut 13 


26 


V DD 


5 


HVqut 12 


27 


Strobe 


6 


HVqut 11 


28 


Data In 


7 


HV 0U T 10 


29 


HVout 32 


8 


HV OUT 9 


30 


HV 0UT 31 


9 


HV 0U T 8 


31 


HVqut 30 


10 


HVqut 7 


32 


HVqut 29 


11 


HVqut 6 


33 


HVqut 28 


12 


HVqut 5 


34 


HVqut 27 


13 


HVqut 4 


35 


HVqut 26 


14 


HVqut 3 


36 


HVqut 25 


15 


HVqut 2 


37 


HVqut 24 


16 


HVqut 1 


38 


HVqut 23 


17 


N/C 


39 


HVqut 22 


18 


Data Out 


40 


HVqut 21 


19 


N/C 


41 


HVqut 20 


20 


N/C 


42 


HVqut 19 


21 


N/C 


43 


HVqut 18 


22 


N/C 


44 


HVqut 17 



11-55 



HV45 
HV46 



32-Channel Serial To Parallel Converter 
with P-Channel Open Drain Outputs 



Ordering Information 



Device 


Recommended 
Operating 
V pp Max 


Package Options 


44 J-Lead Quad 
Ceramic Chip Carrier 


44 J-Lead Quad 
Plastic Chip Carrier 


44 Quad Plastic 
Gullwing 


Die 


HV45 


-300 


HV4530DJ 


HV4530PJ 


HV4530PG 


HV4530X 


-220 


HV4522DJ 


HV4522PJ 


HV4522PG 


HV4522X 


HV46 


-300 


HV4630DJ 


HV4630PJ 


HV4630PG 


HV4630X 


-220 


HV4622DJ 


HV4622PJ 


HV4622PG 


HV4622X 



Features 

□ Processed with HVCMOS Technology 

□ Output voltages to -300V 

□ Source current minimum 60 mA 
~ Shift register speed 8 MHz 

□ Polarity and blanking inputs 

□ CMOS compatible inputs 

□ Forward and reverse shifting options 

□ 44-lead plastic and ceramic surface mount packages 

□ Hi-Rel processing available 

□ Can be used with the HV55 and HV56 to provide 300V 
push pull operation 

Absolute Maximum Ratings 



Supply voltage, V DD 1 


+0.5Vto-16V 


Off state output voltage HV4530/HV4630 


+0.5Vto-315V 


HV4522/ HV4622 


+0.5V to -220V 


Logic input levels 1 +0.5V to V DD - 0.3V 


Ground currrent 2 


1.5A 


Continuous total power dissipation 4 Ceramic 

Plastic 


1500mW 
1200mW 


Operating temperature range Ceramic 

Plastic 


-40°C to +85°C 
0°C to +70°C 


Storage temperature range 


-65°Cto+150°C 


Lead temperature 1 .6mm (1/16 inch) 
from case for 1 seconds 


260°C 


Notes: 

1 . All voltages are referenced to Vss. 

2 Duty cycle is limited by the total power dissipated in the package. 



3. For operation above 25°C ambient, derate linearly to 70"C at 1 2mW/°C. 



General Description 

The HV45 and HV46 are low-voltage serial to high-voltage 
parallel converters with P-Channel open drain outputs. These 
devices have been designed for use as drivers for AC-elec- 
troluminescent displays. They can also be used in any application 
requiring multiple output high-voltage current source capabilities 
such as driving inkjet and electrostatic print heads, plasma 
panels, or vacuum fluorescent displays. 

These devices consist of a 32-bit shift register, 32 data latches, 
and control logic to perform polarity and blanking functions. Data 
is shifted through the shift register on the logic high-to-low 
transition of the clock. The HV45 shifts in the counterclockwise 
direction when viewed from the top of the package and the HV46 
shifts in the clockwise direction. A data output buffer is provided 
for cascading devices. This output reflects the current status of 
the last bit of the shift register. The data in the shift register is 
latched when the latch enable pin is brought to logic high and then 
returned to ground. If the latch enable pin is held high, the latch 
becomes transparent and the shift register data is directly reflected 
in the outputs. 

For applications requiring active pull down as well as pull up, the 
HV45 and HV46 can be paired with the HV55 and HV56 devices, 
respectively. 



11-56 



HV45/HV46 

Electrical Characteristics (over recommended operating conditions unless noted) 
DC Characteristics 



Symbol 


Parameter 


Min 


Max 


Units 


Conditions 


'dd 


V DD supply current 




-15 


mA 


f ci_K = 8 MHz 
Fdata = 4 MHz 


'ddq 


Quiescent V DD supply current 




-100 


HA 


V| N = V ss or V DD 


'o(OFF) 


Off state output current 




-100 


uA 


All SWS parallel 


l,H 


High-level logic input current 




-1 


uA 


V IH = V DD 


I.L 


Low-level logic input current 




+1 


uA 


V|L = V SS 


V 0H 


High-level output data out 


V DD+ 1.0V 








Vol 


Low-level output voltage 


HVqut 




-30.0 


V 


l HVout = -60mA 


Data out 




-1.0 


V 


l Dout = -100u.A 


V oc 


HV OUT clamp voltage 




+1.5 


V 


l 0L = +60mA 



AC Characteristics (V DD = 12V, T c = 25°C) 



Symbol 


Parameter 


Min 


Max 


Units 


Conditions 


f CLK 


Clock frequency 




8 


MHz 




twH^WL 


Clock width high or low 


62 




ns 




t S u 


Data set-up time before clock rises 


50 




ns 




t H 


Data hold time after clock rises 


20 




ns 




l ON 


Turn ON time, HV OUT from enable 




400 


ns 


R L =10K to V DO MAX 


( DHL 


Delay time clock to data high to low 




100 


ns 


C L = 15pF 


'dlh 


Delay time clock to data low to high 




100 


ns 


C L = 15pF 


l DLE 


Delay time clock to LE low to high 


50 




ns 




{ WLE 


Width of LE pulse 


50 




ns 




'SLE 


LE set-up time before clock falls 


50 




ns 





am 



Recommended Operating Conditions 



Symbol 


Parameter 


Min 


Max 


Units 


V DD 


Logic supply voltage 


-10.8 


-13.2 


V 


Voo 


Output off voltage 


HV4530 and HV4630 


+0.3 


-300 


V 


HV4522 and HV4622 


+0.3 


-220 


V 


V IH 


High-level input voltage (LOGIC "1") 


V DD + 2V 


V DD 


V 


V IL 


Low-level input voltage (LOGIC "0") 





-2.0 


V 


*CLK 


Clock frequency 




8 


MHz 


T A 


Operating free-air temperature 


Commercial 





70 


°C 


Military Hi-Rel (RB) 


-55 


+125 


°C 



Note 1: All voltages are referenced to V ss . 



11-57 



HV45/HV46 



Input and Output Equivalent Circuits 



v S s o- 



Input O i %AA, 



Vdd o- 



Logic Inputs 



Vss o- 




' Data Out 



Vdd o- 



Logic Data Output 



vss 



>HV UT 



High Voltage Output 



Switching Waveforms 



Data Input 



Data Valid 



V SS 



Clock 50% 



-twH- 



Data Out 



Latch Enable 



HVout 
w/S/R HIGH 



t H 



50% 



- 50% 



yr 



50% 



-*DLH • 



50% 



->DHL- 



-^50% 



-Idle - 



-'wle- 



50% 



50% 



10%. 



'on ■ 



v ss 

^SS-12 

V SS 
V SS-12 

V SS 
V SS- 12 

V SS 
V SS- 12 



Voo 



11-58 



Functional Block Diagram 



Vss o- 

Polarity o- 

Blanking o- 

Latch Enable o- 



Data Input o- 



Clock o- 



DataOut o- 



32-Bit 
Shift 
Register 



Latch 



Latch 



Latch 



Latch 



=0=0 



=r>=t> 



-o HV 0UT 1 



1 o 



HV 0UT 2 



(Outputs 3 to 30 
not shown) 



3D — 



hd HV 0UT 31 



-O HV OUT 32 



HV45/HV46 



Function Table 





Inputs 


Outputs 


Function 


Data 


CLK 


LE 


BL 


POL 


Shift Reg 

1 2.. .32 


HV Outputs 

1 2. ..32 


Data Out 

* 


All on 


X 


X 


X 


L 


L 


* * * 


H H...H 


* 


All off 


X 


X 


X 


L 


H 


* * * 


L L...L 


* 


Invert mode 


X 


X 


L 


H 


L 


* * * 


* * * 




Load S/R 


HorL 


I 


L 


H 


H 


HorL *...* 


* * * 




Load 


X 


HorL 


T 


H 


H 


* * * 


* * * 




latches 


X 


HorL 


T 


H 


L 


* * * 


+ * * 




Transparent 


L 


j. 


H 


H 


H 


L *...* 


L 




latch mode 


H 


I 


H 


H 


H 


H *...* 


H 


* 



fill 



Notes: 

H = high level, L = low level, X = irrelevant, i = high-to-low transition, t = low-to-high transition, -12V to V ss . 
* = dependent on previous stage's state before the last CLK or last LE high. 



11-59 



Pin Configurations 



HV45 

44 Pin J-Le